Channel threshold regulation and control method and GAA NS device
Through in-situ epitaxial doping and thermal diffusion technology of the germanium silicon layer, the channel threshold voltage is regulated in the GAA NS device, solving the problem of limited regulation range in the existing technology and maintaining high mobility performance.
Patent Information
- Application Number
- CN202510708150.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-12
AI Technical Summary
The channel threshold voltage control range of existing GAA NS devices is limited, making it difficult to effectively control through high-k/metal gate, and direct doping affects mobility.
By using in-situ epitaxial doping of the germanium silicon layer combined with thermal diffusion technology, a slight doping is formed on the surface of the silicon layer. By controlling the depth and concentration of the doping elements, the channel threshold voltage can be regulated while maintaining the stability of the mobility.
It achieves effective regulation of the channel threshold voltage, expands the regulation range, lowers the threshold voltage, reduces carrier scattering and on-state current reduction, and maintains the high mobility performance of the device.
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Figure CN120640716A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of device manufacturing, and in particular to a method for regulating the channel threshold and a GAA NS device. Background Art
[0002] CMOS continues to shrink along with Moore's law and faces more serious short-channel effects. The gate-all-around (GAA) nanosheet (NS) device with a horizontal channel is an ideal choice for technologies of 3 nm and below. The bulk silicon horizontal GAA device can effectively control the short-channel effects in an extremely short channel, thereby significantly reducing the serious leakage phenomenon in the channel, reducing the operating voltage of the device, and achieving low-voltage and low-power operation.
[0003] Currently, the mainstream GAA NS devices use intrinsic Si as the channel material, and the threshold voltage regulation is mainly completed by high-k / metal gates. However, due to the too narrow gap of the channel stack after the channel is released, the thickness of the high-k / metal gate that can be filled is limited; therefore, the regulation range during the threshold voltage regulation by the high-k / metal gate is limited.
[0004] In view of this, the present invention is specifically proposed. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for regulating the channel threshold and a GAA NS device, which can not only achieve channel threshold adjustment but also have little impact on the mobility.
[0006] The present invention provides a method for regulating the channel threshold, including the following steps:
[0007] S1: Epitaxially grow a germanium-silicon layer and a silicon layer on the surface of the substrate in sequence to form a stack, and perform doping during the epitaxial growth of the germanium-silicon layer;
[0008] S2: Heat-treat the substrate on which the stack is formed to make the doping elements in the germanium-silicon layer enter the surface of the silicon layer.
[0009] In step S1, the thickness of the germanium-silicon layer can be 5-20 nm, and the material of the germanium-silicon layer is Si 1-x Ge x (0.1 < x < 0.5); the thickness of the silicon layer can be 5-20 nm; the number of periods of the germanium-silicon / silicon stack can be 3-6 periods. The specific thickness, material, and number of layers of the germanium-silicon layer and the silicon layer can be reasonably determined according to actual needs.
[0010] When pre-forming an NMOS, the doping element is phosphorus or arsenic; when pre-forming a PMOS, the doping element is boron. The doping concentration of the doping elements in the germanium-silicon layer can be 10 18 -10 19 / cm3 .
[0011] Doping is performed by introducing an impurity precursor during epitaxy; when the doping element is phosphorus or arsenic, the impurity precursor is phosphine or arsine, the flow rate is 100-200 sccm, and the time is 10-300s; when the doping element is boron, the impurity precursor is borane, the flow rate is 10-100 sccm, and the time is 10-300s.
[0012] In step S2, the heat treatment temperature is 400-600° C., the heat treatment time is 30 seconds to 10 minutes, and the depth of the doping element into the silicon layer is controlled to be 1-3 nm.
[0013] It can be understood that during heat treatment, the doping elements in the silicon germanium layer will diffuse from both the upper and lower directions; that is, the doping elements in the first silicon germanium layer will penetrate downward into the upper surface of the substrate and upward into the lower surface of the first silicon layer; the doping elements in the second silicon germanium layer will penetrate downward into the upper surface of the first silicon layer and upward into the lower surface of the second silicon layer, and so on.
[0014] Correspondingly, the dopant element is distributed within a depth of 1-3 nm from the substrate's top surface; the dopant element is distributed within a depth of 1-3 nm from the bottom and top surfaces of the first through second-to-last silicon layers; and the dopant element is distributed within a depth of 1-3 nm from the bottom surface of the topmost silicon layer. This creates a unique structure in which the nanosheet channel surface is lightly doped while the center of the nanosheet channel remains intrinsic material.
[0015] The present invention can effectively adjust the doping concentration of the device channel by selecting and adjusting the process parameters of the doping and heat treatment, thereby achieving regulation of the device channel threshold voltage.
[0016] After step S2, the following steps are also included: adopting the mainstream GAA NS process, completing subsequent processes in sequence, and manufacturing a GAA NS device.
[0017] The present invention's channel threshold control method employs in-situ epitaxial doping of a silicon-germanium layer, then uses thermal diffusion to restrict impurities to the surface of the silicon channel layer. This creates a slight inversion effect on the channel surface, reducing the threshold voltage. Furthermore, by lightly doping only the channel surface, it avoids the excessive impurities that can form within the channel, leading to carrier scattering and reduced on-state current, often associated with direct in-situ epitaxial doping of the silicon channel layer.
[0018] The present invention also provides a GAANS device, comprising a substrate and a silicon layer (ie, a nanosheet channel) stacked on the substrate, wherein doping elements are distributed on the surface of the silicon layer.
[0019] Doping elements are distributed on the upper surface and / or lower surface of the silicon layer; the doping elements are located at a depth of 1-3 nm from the upper surface and / or lower surface of the silicon layer. It is understood that the doping depth of the doping elements in the silicon layer should be less than 50% of the thickness of the silicon layer, and the doping depth can be 5-40% of the thickness of the silicon layer. The doping concentration of the doping elements in the silicon layer is 1×10 17 -5×10 18 / cm 3 .
[0020] Except for the above-mentioned special structure, the other structures of the GAA NS device of the present invention are basically the same as those of the GAA NS device in the art; the above-mentioned special structure can be manufactured by the channel threshold control method of the present invention, and other structures can be manufactured using the mainstream GAA NA process in the art.
[0021] The channel threshold control method of the present invention performs in-situ doping and heat treatment on the stacked germanium silicon layers, so that the surface of the nanosheet channel of the GAA NS device is slightly doped, while the middle of the nanosheet channel is still intrinsic material, which can achieve channel threshold adjustment while having little impact on mobility. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 is a schematic diagram of a process for forming a stacked layer on a substrate surface;
[0024] Figure 2 Schematic diagram of the process of doping and heat treating the silicon germanium layer;
[0025] Figure 3 Schematic diagram of the mainstream GAA NA process flow;
[0026] Figure 4 Schematic diagram of the mainstream GAANA process.
[0027] Description of reference numerals:
[0028] 1: substrate; 2: silicon-germanium layer; 3: silicon layer; 4: doping element. DETAILED DESCRIPTION
[0029] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application pertains.
[0030] Note that the terms used herein are merely for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should also be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0031] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.
[0032] Embodiment 1
[0033] I. Channel Threshold Regulation
[0034] 1. Fabrication of Stack
[0035] In combination with Figure 1 , Figure 2 As shown, a germanium-silicon layer 2 and a silicon layer 3 are sequentially epitaxially grown on the surface of the substrate 1 to form a stack; wherein, the number of periods of the germanium-silicon / silicon stack is 3 - 6 periods, the thickness of the germanium-silicon layer 2 is 5 - 20 nm, and the material of the germanium-silicon layer 2 is Si 1-x Ge x (0.1 < x < 0.5); the thickness of the silicon layer 3 is 5 - 20 nm. The specific thickness, material, and number of layers of the germanium-silicon layer 2 and the silicon layer 3 can be reasonably determined according to actual needs.
[0036] In-situ doping is performed during the epitaxial growth of the germanium-silicon layer 2; wherein, when pre-forming NMOS, the doping element 4 is phosphorus or arsenic; when pre-forming PMOS, the doping element 4 is boron. The doping concentration of the doping element 4 in each germanium-silicon layer 2 is 10 18 -10 19 / cm 3 .
[0037] Doping is carried out by introducing impurity precursors during epitaxy; when the doping element 4 is phosphorus or arsenic, the impurity precursor is phosphine or arsine, the flow rate is 100 - 200 sccm, and the time is 10 - 300 s; when the doping element 4 is boron, the impurity precursor is borane, the flow rate is 10 - 100 sccm, and the time is 10 - 300 s.
[0038] 2. Heat treatment
[0039] The laminated substrate 1 is heat-treated at a temperature of 400-600° C. for a time of 30 seconds to 10 minutes.
[0040] The above heat treatment can make the doping elements 4 in the silicon germanium layer 2 penetrate into the surface of the silicon layer 3; by properly selecting and adjusting the above doping and heat treatment process parameters, the doping elements 4 can penetrate into the silicon layer 3 to a depth of 1-3 nm.
[0041] 3. Make devices
[0042] Combine Figure 3 、 Figure 4 As shown, after the above heat treatment, the mainstream GAA NS process is adopted to complete the subsequent processes in sequence; the details are as follows:
[0043] 1) Forming a fin active area structure
[0044] Photolithography and etching are performed to form a fin-type active area structure.
[0045] 2) Shallow Trench Isolation
[0046] Using STI process, a high filling ratio film (low temperature film) is deposited on the substrate 1 forming the fin structure as a shallow trench isolation layer, and a chemical mechanical polishing process (CMP) is used for planarization, low temperature annealing, etching, and exposing the Si 1-x Ge x / Si stacked structure.
[0047] 3) Deposition and etching to form a pseudo gate
[0048] A silicon oxide gate oxide layer and an amorphous silicon film are deposited and etched to form a dummy gate (i.e., a false gate).
[0049] 4) Preparation of side walls and inner side walls
[0050] A dielectric film is deposited on the substrate 1 where the pseudo gate is formed, and then etched to form a primary sidewall. The source and drain are self-aligned and etched to the substrate. Then, the SiGe layer at both ends of the source and drain is precisely etched isotropically to form a filling groove for the inner sidewall. Then, a low-κ (Low-κ) insulating dielectric is isotropically deposited on the inner sidewall, and the Low-κ dielectric is self-aligned and etched under the mask of the primary sidewall of the gate to ensure that the Si nanosheet channel at the source and drain ends is exposed.
[0051] 5) SiGe source-drain selective epitaxy
[0052] After the inner sidewall is formed, the SiGe source and drain are grown using epitaxial growth technology, followed by deposition of a dielectric film, etching to form a secondary sidewall, and source and drain doping.
[0053] 6) False gate removal
[0054] An interlayer dielectric layer (ILD0, silicon oxide, silicon nitride or a stacked layer thereof) is deposited, subjected to a chemical mechanical polishing (CMP) process to expose the dummy gate, and then removed by etching.
[0055] 7) Nanosheet release
[0056] Use high selectivity and damage-free etching to remove the SiGe layer 2 (Si 1-x Ge x ), exposing the silicon layer 3 (i.e., the nanosheet).
[0057] 8) HKMG filling
[0058] A high-k layer is deposited, followed by metal deposition as gate metal, excess gate metal is removed using a chemical mechanical planarization (CMP) process, and an interlayer dielectric (ILD) is filled.
[0059] 9) Contact hole etching and filling
[0060] Photolithography and etching of the interlayer dielectric (ILD) to form contact holes, cleaning and removing the natural oxide layer in the contact holes, filling the contact holes with contact metal and performing silicidation annealing.
[0061] 10) Deposition of metal layer M1
[0062] Deposit a metal layer, perform photolithography and etching, and form the first interconnection metal layer M1.
[0063] The channel threshold control method of this embodiment can effectively adjust the doping concentration of the device channel by selecting and adjusting the process parameters of the above-mentioned doping and heat treatment, thereby realizing the control of the device channel threshold voltage; at the same time, the threshold voltage is controlled in combination with high-k / metal gate, further increasing the control range.
[0064] 2. GAANS devices
[0065] Combine Figure 1-Figure 4 As shown, the GAANS device of this embodiment includes a substrate 1 and a silicon layer 3 (ie, nanosheet) stacked on the substrate 1 , and a doping element 4 is distributed on the surface of the silicon layer 3 .
[0066] When preforming an NMOS, the doping element 4 is phosphorus and arsenic; when preforming a PMOS, the doping element 4 is boron.
[0067] Doping elements 4 are distributed on the upper surface and / or lower surface of the silicon layer 3; the doping elements 4 are located at a depth of 1-3 nm from the upper surface and / or lower surface of the silicon layer 3, and the doping depth of the doping elements 4 in the silicon layer 3 can be 5-40% of the thickness of the silicon layer 3. The doping concentration of the doping elements 4 in the silicon layer 3 is 1×10 17 -5×10 18 / cm 3 .
[0068] More specifically, in the GAANS device of this embodiment, the doping element 4 is distributed at a depth of 1-3 nm on the upper surface of the substrate 1; the doping element 4 is distributed at a depth of 1-3 nm on the lower surface and 1-3 nm on the upper surface of the first to penultimate silicon layers 3; and the doping element 4 is distributed at a depth of 1-3 nm on the lower surface of the topmost silicon layer 3.
[0069] The GAANS device of this embodiment has a special structure in which the surface of the nanosheet channel (i.e., silicon layer 3) is slightly doped, while the middle of the nanosheet channel is still made of intrinsic material (i.e., silicon); except for the above special structure, the rest of the structure is basically the same as the GAANS device in this field.
[0070] This embodiment employs in-situ epitaxial doping of the silicon-germanium layer, then uses thermal diffusion to restrict impurities to the surface of the silicon channel layer. This results in a slight inversion of the channel surface, lowering the threshold voltage. Furthermore, by lightly doping only the channel surface, this avoids the excessive impurities that would form within the channel, leading to carrier scattering and reduced on-state current, often associated with direct in-situ epitaxial doping of the silicon channel layer. This achieves channel threshold regulation while minimizing the impact on mobility.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A channel threshold control method, characterized in that: The steps include: S1: epitaxially growing a germanium-silicon layer and a silicon layer on the substrate surface to form a stack, and doping is performed during the epitaxial growth of the germanium-silicon layer; S2: Heat-treating the substrate forming the stacked layer so that the doping elements in the germanium silicon layer enter the surface of the silicon layer.
2. The channel threshold control method according to claim 1, wherein: The thickness of the germanium silicon layer is 5-20 nm; the thickness of the silicon layer is 5-20 nm.
3. The channel threshold control method according to claim 1, wherein: The material of the silicon germanium layer is Si 1-x Ge x ; Among them, 0.1 <x<0.5。 4. The channel threshold control method according to claim 1, wherein: When NMOS is pre-formed, the doping element is phosphorus or arsenic; when PMOS is pre-formed, the doping element is boron.
5. The channel threshold control method according to claim 1, wherein: The doping concentration of the doping element in the SiGe layer is 10 18 -10 19 / cm 3 .
6. The channel threshold control method according to claim 1, wherein: Doping is performed by introducing an impurity precursor during epitaxy; when the doping element is phosphorus or arsenic, the impurity precursor is phosphine or arsine, the flow rate is 100-200 sccm, and the time is 10-300s; when the doping element is boron, the impurity precursor is borane, the flow rate is 10-100 sccm, and the time is 10-300s.
7. The channel threshold control method according to claim 1, wherein: The heat treatment temperature is 400-600°C; the heat treatment time is 30s-10min.
8. The channel threshold control method according to claim 1, wherein: The depth of the doping elements into the silicon layer is controlled to be 1-3nm.
9. A GAA NS device, characterized in that: The method comprises a substrate and a silicon layer stacked on the substrate, wherein doping elements are distributed on the surface of the silicon layer.
10. The GAA NS device according to claim 9, wherein: The doping concentration of the doping element in the silicon layer is 1×10 17 -5×10 18 / cm 3 .