Source-drain contact laminated layer preparation method and source-drain contact laminated layer structure body
By combining Ta/Mo stacking with Ni layer in semiconductor devices to form NiSi phase, the problem of easy diffusion of single-layer metal silicide in high-temperature process is solved, and a source-drain contact stack with low resistance and high thermal stability is achieved, thereby improving device performance.
Patent Information
- Application Number
- CN202510712174.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-12
AI Technical Summary
As the feature size of semiconductor devices decreases, single-layer metal silicide is prone to silicide agglomeration, interface diffusion and thermal stability degradation in high-temperature processes, resulting in increased contact resistance, which becomes a key factor restricting device performance.
A Ta/Mo stack is combined with a Ni layer, and a two-step annealing treatment is performed to form a NiSi phase. Ta atoms combine with residual O atoms on the surface of the silicon substrate to eliminate interfacial oxygen vacancy traps. The Mo layer acts as a high thermal stability intermediate layer to inhibit the mutual diffusion of Ni and Ta, and promote the uniform formation of NiSi from Ni and Si at low temperatures. At high temperatures, an alloy phase or intermetallic compound is formed to enhance thermal stability.
Effectively reduce contact resistance, improve carrier transport efficiency, enhance the thermal stability of subsequent high-temperature processes, and ensure stable electrical performance of semiconductor devices.
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Figure CN120640756A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a method for preparing a source-drain contact stack and a source-drain contact stack structure. Background Art
[0002] As the feature size of semiconductor devices continues to decrease, source-drain contact resistance has become a key factor restricting device performance.
[0003] In related technologies, although single-layer metal silicide (such as NiSi) has low resistance characteristics, it is prone to silicide agglomeration, interface diffusion and thermal stability degradation in high-temperature processes, resulting in a sharp increase in contact resistance. Summary of the Invention
[0004] In view of the above problems, the present disclosure provides a method for preparing a source-drain contact stack and a source-drain contact stack structure.
[0005] According to a first aspect of the present disclosure, a method for preparing a source-drain contact stack is provided, comprising: forming an insulating layer on a surface of a substrate and etching it to form a contact hole, wherein the silicon surface of the substrate is exposed to the bottom surface of the contact hole; depositing a Ta / Mo stack on the surface of the contact hole, wherein the surface of the contact hole includes the bottom surface and sidewalls of the contact hole; depositing a Ni layer on the surface of the Ta / Mo stack; and performing a two-step annealing treatment to obtain a source-drain contact stack comprising a NiSi phase.
[0006] According to an embodiment of the present disclosure, the insulating layer includes a silicon dioxide layer.
[0007] According to an embodiment of the present disclosure, a Ta / Mo stack is deposited on the surface of the contact hole, including: depositing a Ta layer on the surface of the contact hole, the thickness of the Ta layer is 1nm-5nm; depositing a Mo layer on the surface of the Ta layer, the thickness of the Mo layer is 3nm-5nm.
[0008] According to an embodiment of the present disclosure, depositing a Ta / Mo stack on the surface of the contact hole further includes: performing in-situ doping atom treatment when depositing the Mo layer to embed doping atoms into the Mo layer.
[0009] According to an embodiment of the present disclosure, the doping atoms include B atoms.
[0010] According to an embodiment of the present disclosure, the two-step annealing process includes a first annealing process and a second annealing process, and the annealing temperature of the first annealing process is lower than the annealing temperature of the second annealing process.
[0011] According to an embodiment of the present disclosure, a first annealing treatment is performed to form a NiSi phase, and the annealing temperature of the first annealing treatment is 200°C to 400°C; after the first annealing treatment, a second annealing treatment is performed to activate the Ta / Mo stack, and the annealing temperature of the second annealing treatment is 400°C to 600°C.
[0012] According to an embodiment of the present disclosure, the annealing treatment includes a rapid thermal annealing treatment.
[0013] According to an embodiment of the present disclosure, the thickness of the Ni layer is 5 nm-10 nm.
[0014] According to an embodiment of the present disclosure, the type of the substrate includes at least one of Si or SOI.
[0015] A second aspect of the present disclosure provides a source-drain contact stack structure, characterized in that the source-drain contact stack structure includes: a substrate, a contact hole arranged on the surface of the substrate, the bottom surface of the contact hole exposing the surface of the substrate; a source-drain contact stack located in the contact hole and in contact with the surface of the substrate, the source-drain contact stack including a Ta / Mo stack and a NiSi layer, wherein the source-drain contact stack is prepared by the above method.
[0016] According to the embodiments of the present disclosure, a contact hole is formed on the surface of a substrate, with the silicon surface of the substrate exposed at the bottom of the contact hole. A Ta / Mo stack is deposited on the surface of the contact hole (including the bottom and sidewalls of the contact hole). A Ni layer is deposited on the surface of the Ta / Mo stack. A two-step annealing process is then performed to form a source-drain contact stack comprising a NiSi phase. Ta atoms combine with residual O atoms on the surface of the silicon substrate, eliminating interfacial oxygen vacancy traps and improving carrier transport efficiency. Low-temperature annealing also promotes the uniform formation of NiSi from Ni and Si. High-temperature annealing allows Ta and Mo to diffuse into each other, forming an alloy phase or intermetallic compound with a higher melting point and thermal stability, enhancing the thermal stability of subsequent high-temperature processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0018] Figure 1 A flow chart schematically illustrates a method for preparing a source-drain contact stack according to an embodiment of the present disclosure;
[0019] Figure 2 A schematic diagram of a contact hole according to an embodiment of the present disclosure is schematically shown;
[0020] Figure 3 Schematically shows a schematic diagram of a Ta layer according to an embodiment of the present disclosure;
[0021] Figure 4 Schematic diagram of a Mo:B layer according to an embodiment of the present disclosure is schematically shown;
[0022] Figure 5 Schematically shows a schematic diagram of a Ni layer according to an embodiment of the present disclosure;
[0023] Figure 6 Schematically illustrates a schematic diagram of a stack according to an embodiment of the present disclosure;
[0024] Figure 7 Schematically shows a schematic diagram of a source-drain contact stack according to an embodiment of the present disclosure;
[0025] Figure 8 The figure schematically shows a method for preparing a source-drain contact stack according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0027] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0029] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).
[0030] Figure 1 The flowchart of the method for preparing the source-drain contact stack according to the embodiment of the present disclosure is schematically shown.
[0031] like Figure 1 As shown, the method for preparing the source-drain contact stack of this embodiment includes operations S110 to S140.
[0032] In operation S110 , an insulating layer is formed on a surface of a substrate and etched to form a contact hole, wherein a silicon surface of the substrate is exposed at a bottom surface of the contact hole.
[0033] According to an embodiment of the present disclosure, the source-drain contact resistance refers to the resistance generated in the contact region between the source and drain of a transistor and the semiconductor substrate.
[0034] According to embodiments of the present disclosure, contact holes are small holes etched into an insulating layer (such as a silicon dioxide layer) that connect the source or drain electrode to a metal interconnect. These holes allow current to flow from the source or drain electrode into or out of the transistor, thereby establishing an electrical connection between the transistor and external circuitry.
[0035] According to the embodiments of the present disclosure, silicon dioxide is a good insulating material that can effectively isolate different conductive areas, prevent leakage, and protect the substrate from the influence of the external environment (such as moisture, chemical corrosion, etc.).
[0036] Figure 2 A schematic diagram of a contact hole according to an embodiment of the present disclosure is schematically shown.
[0037] like Figure 2 As shown, the silicon dioxide layer on the substrate is etched to form a contact hole.
[0038] According to an embodiment of the present disclosure, the type of the substrate includes at least one of Si or SOI.
[0039] According to the embodiments of the present disclosure, the silicon substrate has extremely high purity, which can effectively reduce the impact of impurities on device performance. The high-purity silicon substrate can ensure the stability of the electrical characteristics of the semiconductor device and reduce leakage current and noise.
[0040] In operation S120 , a Ta / Mo stack is deposited on a surface of the contact hole, wherein the surface of the contact hole includes a bottom surface and sidewalls of the contact hole.
[0041] According to the embodiments of the present disclosure, a Ta / Mo stack is used, and Ta atoms combine with residual O atoms on the surface of the silicon substrate (forming Ta-O bonds with a binding energy of ~5.2 eV), eliminating interfacial oxygen vacancy traps and improving carrier transport efficiency.
[0042] According to an embodiment of the present disclosure, Ta oxide (Ta 2 O 5 ) has high chemical stability and can suppress failure of the barrier layer caused by high-temperature oxidation.
[0043] In operation S130, a Ni layer is deposited on the surface of the Ta / Mo stack.
[0044] According to the embodiments of the present disclosure, Mo forms a nanocrystalline structure during the annealing process, and its grain boundaries serve as diffusion barriers, preventing Ni atoms from longitudinally penetrating along the Ta grain boundaries.
[0045] According to an embodiment of the present disclosure, the thickness of the Ni layer is 5 nm-10 nm.
[0046] According to an embodiment of the present disclosure, a Ni layer (5 nm-10 nm) is used as a low-temperature silicidation reaction source to form a homogeneous NiSi phase through rapid thermal annealing.
[0047] In operation S140 , a two-step annealing process is performed to obtain a source-drain contact stack including a NiSi phase.
[0048] According to an embodiment of the present disclosure, the annealing process includes a rapid thermal annealing (RTA).
[0049] According to the embodiments of the present disclosure, a two-step annealing process is adopted to promote the uniform formation of NiSi from Ni and Si under low-temperature RTA; Ta and Mo will diffuse with each other at high temperatures to form an alloy phase or intermetallic compound with a higher melting point and thermal stability, thereby enhancing the thermal stability of subsequent high-temperature processes.
[0050] According to the embodiments of the present disclosure, a contact hole is formed on the surface of a substrate, with the silicon surface of the substrate exposed at the bottom of the contact hole. A Ta / Mo stack is deposited on the surface of the contact hole (including the bottom and sidewalls of the contact hole). A Ni layer is deposited on the surface of the Ta / Mo stack. A two-step annealing process is then performed to form a source-drain contact stack comprising a NiSi phase. Ta atoms combine with residual O atoms on the surface of the silicon substrate, eliminating interfacial oxygen vacancy traps and improving carrier transport efficiency. Low-temperature annealing also promotes the uniform formation of NiSi from Ni and Si. High-temperature annealing allows Ta and Mo to diffuse into each other, forming an alloy phase or intermetallic compound with a higher melting point and thermal stability, enhancing the thermal stability of subsequent high-temperature processes.
[0051] According to an embodiment of the present disclosure, a Ta / Mo stack is deposited on the surface of the contact hole, including: depositing a Ta layer on the surface of the contact hole, the thickness of the Ta layer is 1nm-5nm; depositing a Mo layer on the surface of the Ta layer, the thickness of the Mo layer is 3nm-5nm.
[0052] According to an embodiment of the present disclosure, the Ta layer (1 nm-5 nm), as an ultra-thin diffusion barrier layer, preferentially absorbs oxygen impurities on the surface of the silicon substrate to form a dense amorphous interface.
[0053] Figure 3 A schematic diagram of a Ta layer according to an embodiment of the present disclosure is schematically shown.
[0054] like Figure 2 As shown, a Ta layer is deposited on the surface of the contact hole.
[0055] According to an embodiment of the present disclosure, the Mo layer (3 nm-5 nm) serves as a high thermal stability intermediate layer, suppressing Ta / Ni interdiffusion during annealing and reducing interface stress.
[0056] According to the embodiments of the present disclosure, the thickness of the Ta / Mo stack includes but is not limited to the following, and those skilled in the art can select it according to actual needs.
[0057] According to an embodiment of the present disclosure, depositing a Ta / Mo stack on the surface of the contact hole further includes: performing in-situ doping atom treatment when depositing the Mo layer to embed doping atoms into the Mo layer.
[0058] According to an embodiment of the present disclosure, the doping atoms include B atoms.
[0059] According to an embodiment of the present disclosure, B atoms are in-situ doped to ensure that the B atoms are evenly distributed in the Mo layer, thereby lowering the Schottky barrier and reducing the contact resistance.
[0060] According to an embodiment of the present disclosure, in order to further reduce the contact resistance, B atoms are in-situ doped during Mo deposition. After the B atoms are embedded in the Mo lattice gaps, additional electronic states are introduced to enhance the energy band matching with the silicon substrate, reduce the interface barrier height, and reduce the contact resistance.
[0061] According to the embodiments of the present disclosure, the dosage and doping ratio of the in-situ doped B atoms are determined according to the thickness of the Mo layer. The doping atoms include but are not limited to B atoms, and any atoms with a radius similar to that of the B atoms may be used.
[0062] Figure 4 Schematic diagram of a Mo:B layer according to an embodiment of the present disclosure is schematically shown; Figure 5 Schematically shows a schematic diagram of a Ni layer according to an embodiment of the present disclosure; Figure 6 A schematic diagram of a stack according to an embodiment of the present disclosure is schematically shown.
[0063] like Figure 4 As shown, a Mo layer is deposited on the surface of the Ta layer, wherein B atoms are uniformly distributed in the Mo layer.
[0064] like Figure 5 As shown, a Ni layer is deposited on the surface of the Mo layer.
[0065] like Figure 6 As shown, a stack consisting of Si, Ta, Mo, B atoms and Ni is obtained.
[0066] According to an embodiment of the present disclosure, the two-step annealing process includes a first annealing process and a second annealing process, and the annealing temperature of the first annealing process is lower than the annealing temperature of the second annealing process.
[0067] According to the embodiments of the present disclosure, the annealing time and temperature are related to the thickness of the Ta / Mo stack, and a suitable annealing temperature and time can be selected according to the thickness of the Ta / Mo stack.
[0068] According to an embodiment of the present disclosure, a first annealing treatment is performed to form a NiSi phase, and the annealing temperature of the first annealing treatment is 200°C to 400°C; after the first annealing treatment, a second annealing treatment is performed to activate the Ta / Mo stack, and the annealing temperature of the second annealing treatment is 400°C to 600°C.
[0069] Figure 7 The figure schematically shows a source-drain contact stack according to an embodiment of the present disclosure.
[0070] like Figure 7 As shown in FIG, after two-step annealing treatment, NiSi is obtained to obtain a source-drain contact stack containing a NiSi phase, wherein Ta and Mo form a mixed metallization and diffuse with each other when forming NiSi. There is no obvious interface distinction between Ta, Mo and NiSi. The source-drain contact stack can be represented as NiSi (Ta x Mo 1-x ).
[0071] Figure 8 The figure schematically shows a method for preparing a source-drain contact stack according to an embodiment of the present disclosure.
[0072] like Figure 8 As shown, the method for preparing the source-drain contact stack includes S810 to S850.
[0073] In operation S810 , a p-type Si ( 100 ) substrate is prepared, an insulating layer is grown on the substrate, the insulating layer is etched to form a contact hole, and the contact hole is cleaned.
[0074] In operation S820 , a Ta / Mo stack is deposited based on an atomic layer deposition (ALD) technique and B atoms are doped.
[0075] In operation S830, a Ni layer is deposited on the surface of the Ta / Mo stack.
[0076] In operation S840 , a low temperature annealing process is performed to promote Ni and Si to form a NiSi phase.
[0077] In operation S850 , a high temperature annealing process is performed to activate the Ta / Mo stack.
[0078] The second aspect of the present disclosure provides a source-drain contact stack structure, such as Figure 7 As shown, the source-drain contact stack structure includes: a substrate, a contact hole arranged on the surface of the substrate, the bottom surface of the contact hole exposes the surface of the substrate; a source-drain contact stack located in the contact hole and in contact with the surface of the substrate, the source-drain contact stack including a Ta / Mo stack and a NiSi layer, wherein the source-drain contact stack is prepared by the above method.
[0079] Among them, an insulating layer (silicon dioxide layer) is provided on the Si substrate, and a contact hole is formed with the substrate during etching; the Mo layer in the Ta / Mo stack has B atoms evenly distributed.
[0080] According to the embodiments of the present disclosure, a silicon dioxide layer is formed on the surface of a substrate and etched to form a contact hole, wherein the silicon surface of the substrate is exposed to the bottom surface of the contact hole; a Ta / Mo stack is deposited on the surface of the contact hole, wherein the surface of the contact hole includes the bottom surface and sidewalls of the contact hole; a Ni layer is deposited on the surface of the Ta / Mo stack; and a two-step annealing process is performed to obtain a source-drain contact stack containing a NiSi phase. Ta atoms combine with residual O atoms on the surface of the silicon substrate, eliminating interfacial oxygen vacancy traps and improving carrier transport efficiency. Low-temperature annealing also promotes the uniform formation of NiSi from Ni and Si. Ta and Mo will diffuse into each other under high-temperature annealing to form an alloy phase or intermetallic compound with a higher melting point and thermal stability, enhancing the thermal stability of subsequent high-temperature processes.
[0081] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.
[0082] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A method for preparing a source-drain contact stack, characterized in that: The method comprises: forming an insulating layer on the surface of the substrate and etching the insulating layer to form a contact hole, wherein the silicon surface of the substrate is exposed at the bottom surface of the contact hole; Depositing a Ta / Mo stack on the surface of the contact hole, wherein the surface of the contact hole includes the bottom surface and sidewalls of the contact hole; Depositing a Ni layer on the surface of the Ta / Mo stack; A two-step annealing process is adopted to obtain a source-drain contact stack including a NiSi phase.
2. The method according to claim 1, characterized in that Depositing a Ta / Mo stack on the surface of the contact hole comprises: Depositing a Ta layer on the surface of the contact hole, wherein the thickness of the Ta layer is 1 nm to 5 nm; A Mo layer is deposited on the surface of the Ta layer, and the thickness of the Mo layer is 3nm-5nm.
3. The method according to claim 2, characterized in that Depositing a Ta / Mo stack on the surface of the contact hole further comprises: When the Mo layer is deposited, an in-situ dopant atom treatment is performed to embed dopant atoms into the Mo layer.
4. The method according to claim 3, characterized in that The doping atoms include B atoms.
5. The method according to claim 1, characterized in that The two-step annealing process includes a first annealing process and a second annealing process, wherein an annealing temperature of the first annealing process is lower than an annealing temperature of the second annealing process.
6. The method according to claim 5, characterized in that The first annealing treatment is performed to form the NiSi phase, wherein the annealing temperature of the first annealing treatment is 200° C. to 400° C.; After the first annealing treatment, the second annealing treatment is performed to activate the Ta / Mo stack. The annealing temperature of the second annealing treatment is 400° C. to 600° C.
7. The method according to claim 5, characterized in that The annealing treatment includes rapid thermal annealing.
8. The method according to claim 1, characterized in that The thickness of the Ni layer is 5nm-10nm.
9. The method according to claim 1, characterized in that The substrate is made of at least one of Si and SOI.
10. A source-drain contact stacked structure, characterized in that: The source-drain contact stacked structure comprises: substrate, a contact hole provided on the surface of the substrate, wherein the bottom surface of the contact hole exposes the surface of the substrate; a source-drain contact stack located in the contact hole and in contact with the surface of the substrate, the source-drain contact stack comprising a Ta / Mo stack and a NiSi layer, Wherein, the source-drain contact stack is prepared by the method according to any one of claims 1-9.