BCD device and manufacturing method thereof

Abstract

The invention discloses a BCD device and a manufacturing method thereof. The BCD device comprises a substrate; the epitaxial layer is arranged on the substrate; the first isolation structure and the second isolation structure are arranged in the epitaxial layer at intervals; the high-voltage device is arranged in the epitaxial layer surrounded by the first isolation structure; the low-voltage device is arranged in the epitaxial layer surrounded by the second isolation structure; the transverse carrier suppression layer is arranged in the epitaxial layer between the first isolation structure and the second isolation structure; and the buried oxide layer is arranged in an area, corresponding to the high-voltage device, in the substrate. Longitudinal and transverse efficient isolation can be considered at the same time, potential leakage paths of current carriers are blocked as much as possible, and therefore the insulation requirement in a high-voltage scene is met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a BCD device and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor power integrated circuit technology, the BCD (Bipolar-CMOS-DMOS) process is widely used in high-voltage power scenarios such as DC-DC power supplies and motor drives because it integrates the advantages of bipolar devices, CMOS devices, and DMOS devices.

[0003] Traditional physical isolation solutions (such as deep trench isolation (DTI) or single PN junction isolation) have at least the following disadvantages: they only rely on physical blocking or junction isolation mechanisms in a single direction and cannot achieve efficient isolation in both the vertical and lateral directions at the same time, resulting in potential leakage paths for carriers inside the device that are not effectively blocked, making it difficult to meet the stringent insulation performance requirements in high-voltage scenarios. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the current problems, the present application provides a BCD device, including: substrate; an epitaxial layer, disposed on the substrate; A first isolation structure and a second isolation structure are spaced apart and arranged in the epitaxial layer; a high-voltage device, disposed in the epitaxial layer surrounded by the first isolation structure; a low-voltage device, disposed in the epitaxial layer surrounded by the second isolation structure; a lateral carrier suppression layer, disposed in the epitaxial layer between the first isolation structure and the second isolation structure; A buried oxide layer is provided in a region of the substrate corresponding to the high-voltage device.

[0006] In some embodiments of the present application, the substrate is further provided with a first heat dissipation groove structure distributed along the edge of the high-voltage device, the first heat dissipation groove structure extends from the side of the substrate away from the epitaxial layer into the substrate and passes through the substrate, the first heat dissipation groove structure is connected to the high-voltage device at one end close to the epitaxial layer, and this end is also respectively connected to the buried oxide layer, the first isolation structure and the lateral carrier suppression layer, and the end of the first heat dissipation groove structure away from the epitaxial layer is used to connect to an external heat sink.

[0007] In some embodiments of the present application, the first heat dissipation groove structure includes a metal heat conductor and an insulating layer arranged on the side wall of the metal heat conductor, the end of the metal heat conductor close to the epitaxial layer is connected to the high-voltage device, and the end away from the epitaxial layer is connected to the external heat dissipation plate, and the end of the insulating layer close to the epitaxial layer is connected to the buried oxide layer, the first isolation structure and the lateral carrier suppression layer.

[0008] In some embodiments of the present application, a size of the first heat dissipation trench structure gradually decreases from an end close to the substrate to an end close to the epitaxial layer.

[0009] In some embodiments of the present application, at least one second heat dissipation groove structure is provided in the substrate below the buried oxide layer, and the second heat dissipation groove structure extends from the side of the substrate facing away from the epitaxial layer into the substrate to pass through the buried oxide layer and be connected to the high-voltage device, and the end of the second heat dissipation groove structure facing away from the epitaxial layer is used to be connected to an external heat sink.

[0010] In some embodiments of the present application, the lateral carrier suppression layer is a heavily doped region of the first conductivity type, and the lateral carrier suppression layer also penetrates the epitaxial layer and extends into the substrate.

[0011] In some embodiments of the present application, the high-voltage device includes a DMOS device, and the low-voltage device includes a CMOS device and a Bipolar device.

[0012] In another aspect, the present application provides a method for manufacturing the BCD device described in any one of the above, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a buried oxide layer in the substrate, wherein the buried oxide layer is located in a region of the substrate corresponding to a high-voltage device to be subsequently formed; forming a lateral carrier suppression layer and a first isolation structure and a second isolation structure spaced apart in the epitaxial layer, wherein the lateral carrier suppression layer is located in the epitaxial layer between the first isolation structure and the second isolation structure; A high-voltage device is formed in the epitaxial layer surrounded by the first isolation structure, and a low-voltage device is formed in the epitaxial layer surrounded by the second isolation structure.

[0013] In some embodiments of the present application, further comprising: forming a patterned mask layer on the back side of the substrate, wherein the mask layer defines a pattern of trenches to be formed and distributed along the edge of the high-voltage device; Etching is performed based on the mask layer to form a trench distributed along the edge of the high-voltage device, wherein the trench extends from a side of the substrate facing away from the epitaxial layer into the substrate and penetrates the substrate, wherein an end of the trench close to the epitaxial layer exposes the high-voltage device, and the buried oxide layer, the first isolation structure, and the lateral carrier suppression layer are also exposed at the same end; depositing an insulating material on a sidewall of the trench to form an insulating layer; The grooves in the insulating layer are filled with a metal heat conductive material to form a metal heat conductor.

[0014] In some embodiments of the present application, a lateral carrier suppression layer is formed in the epitaxial layer, including: forming the lateral carrier suppression layer by tilted ion implantation, the angle of the tilted implantation is 30° to 60°, and the lateral carrier suppression layer is a heavily doped region of the first conductivity type.

[0015] In the BCD device and its manufacturing method according to the embodiments of the present application, the buried oxide layer serves as a vertical isolation structure, forming a vertical insulation barrier in the region of the substrate corresponding to the high-voltage device, achieving vertical electrical isolation between the high-voltage region and the substrate. A lateral carrier suppression layer, located between the first and second isolation structures, effectively suppresses lateral diffusion of carriers, forming a lateral isolation barrier. The hybrid isolation mechanism created by these two elements overcomes the limitation of traditional physical isolation (such as DTI or single PN junction isolation) that relies solely on isolation in a single direction. It achieves efficient isolation in both vertical and lateral directions, minimizing potential leakage paths for carriers and thus meeting the insulation requirements of high-voltage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0017] Figure 1 A cross-sectional schematic diagram of a BCD device according to a specific embodiment of the present application is shown.

[0018] Figure 2 A partial cross-sectional schematic diagram of a BCD device according to a specific embodiment of the present application is shown.

[0019] Figure 3A flow chart showing a method for manufacturing a BCD device according to a specific embodiment of the present application is shown.

[0020] Figures 4A to 4C The cross-sectional view of a BCD device and a manufacturing method thereof according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0022] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0023] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0024] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein should be interpreted accordingly.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] Traditional physical isolation solutions (such as deep trench isolation (DTI) or single PN junction isolation) have at least the following disadvantages: they only rely on physical blocking or junction isolation mechanisms in a single direction and cannot achieve efficient isolation in both the vertical and lateral directions at the same time, resulting in potential leakage paths for carriers inside the device that are not effectively blocked, making it difficult to meet the stringent insulation performance requirements in high-voltage scenarios.

[0027] Therefore, in view of the existence of the aforementioned technical problems, the present invention proposes a BCD device, comprising: substrate; an epitaxial layer, disposed on the substrate; A first isolation structure and a second isolation structure are spaced apart and arranged in the epitaxial layer; a high-voltage device, disposed in the epitaxial layer surrounded by the first isolation structure; a low-voltage device, disposed in the epitaxial layer surrounded by the second isolation structure; a lateral carrier suppression layer, disposed in the epitaxial layer between the first isolation structure and the second isolation structure; A buried oxide layer is provided in a region of the substrate corresponding to the high-voltage device.

[0028] In the BCD device of this application, a buried oxide layer serves as a vertical isolation structure, forming a vertical insulation barrier in the region of the substrate corresponding to the high-voltage device, achieving vertical electrical isolation between the high-voltage region and the substrate. A lateral carrier suppression layer, located between the first and second isolation structures, effectively suppresses lateral diffusion of carriers, forming a lateral isolation barrier. This hybrid isolation mechanism, created by combining these two elements, transcends the limitations of traditional physical isolation (such as DTI or single PN junction isolation) that relies solely on isolation in a single direction. It achieves efficient isolation in both vertical and lateral directions, minimizing potential carrier leakage paths and thus meeting the insulation requirements of high-voltage scenarios. In order to thoroughly understand the present application, detailed steps and structures will be provided in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods. Example

[0029] This application provides a BCD device, below, refer to Figure 1 and Figure 2 The BCD device of this application is introduced and explained in detail.

[0030] Specifically, if Figure 1 As shown, BCD devices include: substrate 101; Epitaxial layer 102, disposed on substrate 101; The first isolation structure 103 and the second isolation structure 104 are spaced apart and arranged in the epitaxial layer 102; The high-voltage device 110 is disposed in the epitaxial layer 102 surrounded by the first isolation structure 103; A low voltage device 120 is disposed in the epitaxial layer 102 surrounded by the second isolation structure 104; A lateral carrier suppression layer 105 is disposed in the epitaxial layer 102 between the first isolation structure 103 and the second isolation structure 104; The buried oxide layer 106 is disposed in a region of the substrate 101 corresponding to the high-voltage device 110 .

[0031] In this embodiment, the buried oxide layer 106 serves as a vertical isolation structure, forming a vertical insulation barrier in the region of the substrate 101 corresponding to the high-voltage device 110, achieving vertical electrical isolation between the high-voltage region and the substrate 101. The lateral carrier suppression layer 105, located between the first isolation structure 103 and the second isolation structure 104, effectively suppresses the lateral diffusion of carriers, forming a lateral isolation barrier that prevents crosstalk between the high-voltage and low-voltage regions and reduces the risk of lateral leakage. This hybrid isolation mechanism, created by combining these two elements, transcends the limitations of traditional physical isolation (such as DTI or single PN junction isolation) that relies solely on isolation in a single direction. It achieves efficient isolation in both vertical and lateral directions, minimizing potential carrier leakage paths and thus meeting the insulation requirements of high-voltage scenarios.

[0032] Furthermore, the traditional DTI process requires complex deep trench etching and filling steps, which not only increases process costs but also easily introduces mechanical stress within the device, affecting device reliability. The BCD device of this embodiment achieves vertical electrical isolation by providing a buried oxide layer 106 in the region of the high-voltage device 110 corresponding to the substrate 101. This replaces the traditional DTI structure and reduces the high cost and mechanical stress associated with deep trench etching and filling.

[0033] Furthermore, conventional isolation structures (such as PN junction isolation) have insufficient ability to suppress lateral carrier diffusion, leading to crosstalk between the high-voltage and low-voltage regions, posing a risk of lateral leakage. In this embodiment, a lateral carrier suppression layer 105 between the first isolation structure 103 and the second isolation structure 104 effectively suppresses lateral carrier diffusion, resolving the crosstalk and lateral leakage issues between the high-voltage and low-voltage regions.

[0034] In some embodiments, the substrate 101 may be any suitable semiconductor substrate, such as a bulk silicon substrate. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be double-side polished silicon wafers (DSP), or may be ceramic substrates such as alumina, quartz or glass substrates, etc.

[0035] In some embodiments, the substrate 101 has a first conductivity type, wherein the first conductivity type may be P-type or N-type, which is not limited thereto. Exemplarily, the substrate 101 is a P-type substrate.

[0036] In some embodiments, the first isolation structure 103 and the second isolation structure 104 may both be shallow trench isolation structures.

[0037] In some embodiments, the high-voltage device 110 may include a DMOS device, and the low-voltage device 120 may include a CMOS device and a Bipolar device.

[0038] In some embodiments, the lateral carrier suppression layer 105 is a heavily doped region of the first conductivity type and is formed by tilted ion implantation with an angle of 30° to 60°. For example, the lateral carrier suppression layer 105 is a heavily doped P-type region.

[0039] The doping concentration of the lateral carrier suppression layer 105 is usually 10 18 cm -3 ~10 20 cm -3 .

[0040] In addition, if Figure 1 As shown, the lateral carrier suppression layer 105 also penetrates the epitaxial layer 102 and extends into the substrate 101 .

[0041] In some embodiments, as Figure 1 As shown, the substrate 101 is also provided with a first heat dissipation groove structure 107 distributed along the edge of the high-voltage device 110. The first heat dissipation groove structure 107 extends from the side of the substrate 101 away from the epitaxial layer 102 into the substrate 101 and passes through the substrate 101. The end of the first heat dissipation groove structure 107 close to the epitaxial layer 102 is connected to the high-voltage device 110, and the end is also respectively connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105. The end of the first heat dissipation groove structure 107 away from the epitaxial layer 102 is used to connect to an external heat sink.

[0042] On the one hand, the first heat dissipation groove structure 107 is distributed along the edge of the high-voltage device 110 and penetrates the substrate 101. Its bottom end is connected to the external heat dissipation plate, and the top end extends upward and connected to the high-voltage device 110. It can directly conduct heat from the high-voltage device 110 to reduce thermal resistance.

[0043] On the other hand, the top of the first heat dissipation groove structure 107 is also connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105, forming a coordinated isolation entity with the hybrid isolation structure composed of the lateral carrier suppression layer 105 and the buried oxide layer 106, further blocking the potential leakage path of carriers and enhancing the insulation performance under high-voltage scenarios.

[0044] Exemplarily, the top of the first heat dissipation trench structure 107 is connected to the outer edge of the buried oxide layer 106, and the first heat dissipation trench structure 107 is connected to the outer edge of the buried oxide layer 106 to form a continuous isolation entity, thereby achieving vertical electrical isolation between the high-voltage DMOS region and the substrate 101 through a physical barrier, effectively blocking the vertical leakage path.

[0045] For example, the top of the first heat dissipation groove structure 107 is connected to the bottom of the first isolation structure 103 to form a continuous physical isolation barrier, which extends downward from the top surface of the epitaxial layer 102 to the bottom surface of the substrate 101, and can block the diffusion channel of lateral carriers in all directions, effectively reducing lateral leakage current, thereby meeting the stringent requirements of high-voltage application scenarios on insulation performance.

[0046] For example, the top of the first heat dissipation groove structure 107 is connected to the bottom of the lateral carrier suppression layer 105 to form a continuous physical isolation barrier. The barrier extends downward from the top surface of the epitaxial layer 102 to the bottom surface of the substrate 101, which can block the diffusion channel of lateral carriers in all directions and effectively reduce the lateral leakage current, thereby meeting the stringent requirements of high-voltage application scenarios on insulation performance.

[0047] It is particularly worth noting that when the top of the first heat dissipation groove structure 107 is simultaneously connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105, a complete isolation system covering three-dimensional space can be formed, thereby comprehensively improving the device's voltage resistance and insulation performance, and meeting the application requirements of high-voltage power integrated circuits.

[0048] In some embodiments, as Figure 1 As shown, the first heat dissipation groove structure 107 includes a metal heat conductor 1072 and an insulating layer 1071 arranged on the side wall of the metal heat conductor 1072. The end of the metal heat conductor 1072 close to the epitaxial layer 102 is connected to the high-voltage device 110, and the end away from the epitaxial layer 102 is connected to the external heat dissipation plate. The end of the insulating layer 1071 close to the epitaxial layer 102 is connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105.

[0049] The first heat dissipation groove structure 107 directly connects the high-voltage device 110 and the external heat sink through the internal metal heat conductor 1072, constructing an efficient heat conduction path and significantly reducing thermal resistance; at the same time, the external insulation layer 1071 ensures electrical isolation from the surrounding semiconductor materials to avoid the formation of a leakage path, thereby maintaining the electrical insulation performance of the device while improving the heat dissipation efficiency, and meeting the dual requirements of high-voltage BCD devices for thermal management and electrical isolation.

[0050] It is worth noting that the insulating layer 1071 of the first heat dissipation trench structure 107 is respectively connected to at least one of the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105 to form a more comprehensive isolation system to enhance the device's withstand voltage and insulation performance.

[0051] The material of the metal heat conductor 1072 can be copper, tungsten, etc., which is not limited.

[0052] In some embodiments, as Figure 1 As shown, the first heat dissipation trench structure 107 gradually decreases in size from the end closest to the substrate 101 to the end closest to the epitaxial layer 102. This design can create a larger heat dissipation contact area on the substrate 101 side, enhancing the efficiency of heat removal from the high-voltage device 110. This allows the heat generated during operation of the high-voltage device 110 to quickly diffuse and dissipate toward the substrate 101 through the first heat dissipation trench structure 107, significantly improving the overall heat dissipation capability, helping to lower the operating temperature of the high-voltage device 110, and reducing performance degradation caused by heat accumulation, thereby improving the reliability and operational stability of the high-voltage device 110.

[0053] Of course, the present application is not limited to the first heat dissipation groove structure 107 adopting the above-mentioned morphology. It can also adopt other morphologies, such as a cylindrical structure with uniform dimensions along its extension direction, etc., and the present application does not limit this.

[0054] In some embodiments, as Figure 2 As shown, at least one second heat dissipation groove structure 108 is also provided in the substrate 101 below the buried oxide layer 106. The second heat dissipation groove structure 108 extends from the side of the substrate 101 facing away from the epitaxial layer 102 into the substrate 101 to pass through the buried oxide layer 106 and be connected to the high-voltage device 110. The end of the second heat dissipation groove structure 108 facing away from the epitaxial layer 102 is used to be connected to an external heat sink.

[0055] The second heat dissipation groove structure 108 is dispersedly distributed below the high-voltage device 110, forming a "lattice-type" heat dissipation solution. The top end of the second heat dissipation groove structure 108 extends upward through the buried oxide layer 106 and is connected to the bottom surface of the high-voltage device 110 to be close to the heat core area. The bottom end is connected to the external heat dissipation plate to quickly dissipate heat. By increasing the density of the heat dissipation path (i.e., increasing the number of the second heat dissipation groove structures 108), the local accumulated heat below the high-voltage device 110 can be targeted and directed, effectively solving the local hot spot problem in the high-voltage working scenario.

[0056] The material of the second heat dissipation trench structure 108 may be copper, tungsten, etc., which is not limited.

[0057] In some embodiments, the size of the second heat dissipation groove structure 108 can be larger than the size of the first heat dissipation groove structure 107. Specifically, the first heat dissipation groove structure 107 is arranged in a ring shape along the edge of the high-voltage device 110, which can form a surround heat dissipation for the peripheral area of ​​the high-voltage device 110; the second heat dissipation groove structure 108 is located within the area enclosed by the first heat dissipation groove structure 107 and is arranged corresponding to the bottom of the high-voltage device 110, and can directly act on the core heating area of ​​the high-voltage device 110. By making the size of the second heat dissipation groove structure 108 larger than the first heat dissipation groove structure 107, a wider heat dissipation channel can be formed in the core heating area at the bottom of the high-voltage device 110, significantly increasing the heat dissipation contact area and heat conduction cross-section of this area, enhancing the ability to quickly remove heat from the core area, and preventing heat accumulation in the core area.

[0058] Of course, the present application is not limited to the first heat dissipation groove structure 107 and the second heat dissipation groove structure 108 having only the above-mentioned size relationship. The two can also have other size relationships, for example, the size of the first heat dissipation groove structure 107 is consistent with the size of the second heat dissipation groove structure 108, etc. The present application does not limit this. Example

[0059] Below, reference Figures 1 to 3 、 Figure 4A to Figure 4C The manufacturing method of the BCD device of the present application is described in detail.

[0060] For example, Figure 3 As shown, the manufacturing method of the BCD device of the present application includes the following steps: First, perform step 1, such as Figure 4A As shown, a substrate 101 is provided.

[0061] The provided substrate 101 may be any suitable semiconductor substrate 101, such as a bulk silicon substrate 101. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be double-side polished silicon wafers (DSPs), or ceramic substrates 101 such as alumina, quartz or glass substrates 101, etc.

[0062] In a specific embodiment, the substrate 101 is a silicon-on-insulator (SOI) substrate. Then, execute step 2, such as Figure 4AAs shown, an epitaxial layer 102 is formed on a substrate 101 .

[0063] On the substrate 101, an epitaxial layer 102 can be formed by an epitaxial growth process such as vapor phase epitaxy, liquid phase epitaxy, and molecular beam epitaxy. The material of the epitaxial layer 102 can be the same as or different from the material of the substrate 101. For example, a silicon epitaxial layer 102 can be grown on the substrate 101. Then, execute step 3, such as Figure 4B As shown, a buried oxide layer 106 is formed in the substrate 101 . The buried oxide layer 106 is located in a region of the substrate 101 corresponding to a region where a high-voltage device 110 will be formed subsequently.

[0064] For example, oxygen ions are introduced into the target area of ​​substrate 101, corresponding to the target region where high-voltage devices 110 will be subsequently formed, through a selective oxygen ion implantation process. High-temperature annealing then drives the oxygen ions to aggregate, forming a localized buried oxide layer 106 (BOX). This process constructs the insulating buried layer only in the areas required for high-voltage devices 110, while retaining the bulk silicon structure in the low-voltage devices 120. This avoids the high cost and process complexity of a full-sheet SOI substrate 101 while leveraging the insulating properties of buried oxide 106 to form a reliable vertical electrical isolation barrier in the high-voltage device 110 region. This effectively blocks the vertical leakage path between the high-voltage region and substrate 101, improving the device's withstand voltage performance. Furthermore, the selective implantation and annealing process is compatible with traditional BCD process steps, eliminating the need for additional complex steps and ensuring the feasibility and stability of the process. Then, execute step 4, such as Figure 4B As shown, a lateral carrier suppression layer 105 and a first isolation structure 103 and a second isolation structure 104 are formed in the epitaxial layer 102 . The lateral carrier suppression layer 105 is located in the epitaxial layer 102 between the first isolation structure 103 and the second isolation structure 104 .

[0065] In some embodiments, the first isolation structure 103 and the second isolation structure 104 may both be shallow trench isolation structures.

[0066] Specifically, a first isolation structure 103 and a second isolation structure 104 spaced apart can be formed in the epitaxial layer 102 through a shallow trench isolation (STI) process: first, photoresist is deposited on the surface of the epitaxial layer 102 and the target areas of the first isolation structure 103 and the second isolation structure 104 are defined through a photolithography process, and the surface of the epitaxial layer 102 to be etched is exposed after exposure and development; then, a dry etching process is used to etch the exposed area to form a shallow trench in the epitaxial layer 102 with a depth matching the isolation requirements; then, an insulating medium (such as silicon dioxide) is filled into the trench through a chemical vapor deposition (CVD) process to ensure that the trench is completely filled to avoid voids; finally, a chemical mechanical polishing (CMP) process is used to remove excess insulating medium outside the trench so that the top surface of the insulating medium is flush with the surface of the epitaxial layer 102, thereby forming the first isolation structure 103 and the second isolation structure 104 coplanar with the surface of the epitaxial layer 102. This process constructs independent device area boundaries in the shallow surface layer of the epitaxial layer 102 through the physical separation effect of shallow trench isolation, providing an insulating isolation basis for the subsequent partitioned integration of high-voltage devices 110 and low-voltage devices 120, and effectively preventing surface electrical interference between different device areas.

[0067] For example, the formation of the lateral carrier suppression layer 105 within the epitaxial layer 102 is achieved by the following steps: first, after completing the shallow trench isolation (STI) process, a layer of photoresist of uniform thickness is deposited on the surface of the epitaxial layer 102, and an opening region is formed through a photolithography process, which precisely covers the target region between the first isolation structure 103 and the second isolation structure 104. Subsequently, ion implantation equipment is used to perform tilted ion implantation, with the implantation angle controlled within the range of 30° to 60° to ensure that the implanted ions are effectively distributed in the lateral region between the first isolation structure 103 and the second isolation structure 104, while avoiding damage to the interior of the isolation structure. The implanted ions are of the first conductivity type, and the implantation energy and dose are precisely set according to the target doping concentration and distribution depth, forming a heavily doped region of the first conductivity type. This tilted implantation process, by precisely controlling the implantation angle, forms a heavily doped region of the first conductivity type with a specific concentration distribution within the epitaxial layer 102 between the first isolation structure 103 and the second isolation structure 104, effectively suppressing lateral carrier diffusion, enhancing the lateral isolation performance of the device, and avoiding electrical interference with adjacent device regions.

[0068] The first conductivity type may be P-type or N-type, which is not limited. For example, the implanted ions are P-type ions, such as boron ions, and accordingly the lateral carrier suppression layer 105 is a heavily doped P-type region.

[0069] The doping concentration of the lateral carrier suppression layer 105 is usually 10 18 cm -3 ~1020 cm -3 .

[0070] In addition, if Figure 4B As shown, the lateral carrier suppression layer 105 also penetrates the epitaxial layer 102 and extends into the substrate 101 .

[0071] In some embodiments, the buried oxide layer 106 and the lateral carrier suppression layer 105 may be formed in steps or simultaneously, which is not limited. Then, execute step 5, such as Figure 4C As shown, a high voltage device 110 is formed in the epitaxial layer 102 within the first isolation structure 103 , and a low voltage device 120 is formed in the epitaxial layer 102 within the second isolation structure 104 .

[0072] After completing the preparation of the first isolation structure 103 and the second isolation structure 104, when forming the high-voltage device 110 in the epitaxial layer 102 area within the first isolation structure 103 and the low-voltage device 120 in the epitaxial layer 102 area within the second isolation structure 104, the existing mature process combination in the semiconductor manufacturing field can be used, and the specific implementation method is not specifically limited.

[0073] In some embodiments, the high-voltage device 110 may include a DMOS device, and the low-voltage device 120 may include a CMOS device and a Bipolar device. Then, if Figure 4C As shown, the manufacturing method also includes: forming a first heat dissipation groove structure 107 distributed along the edge of the high-voltage device 110 in the substrate 101, the first heat dissipation groove structure 107 extends from the side of the substrate 101 away from the epitaxial layer 102 into the substrate 101, and passes through the substrate 101, the end of the first heat dissipation groove structure 107 close to the epitaxial layer 102 is connected to the high-voltage device 110, and the end is also respectively connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105, and the end of the first heat dissipation groove structure 107 away from the epitaxial layer 102 is used to connect to an external heat sink.

[0074] On the one hand, the first heat dissipation groove structure 107 is distributed along the edge of the high-voltage device 110 and penetrates the substrate 101. Its bottom end is connected to the external heat dissipation plate, and the top end extends upward and connected to the high-voltage device 110. It can directly conduct heat from the high-voltage device 110 to reduce thermal resistance.

[0075] On the other hand, the top of the first heat dissipation groove structure 107 is also connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105, forming a coordinated isolation entity with the hybrid isolation structure composed of the lateral carrier suppression layer 105 and the buried oxide layer 106, further blocking the potential leakage path of carriers and enhancing the insulation performance under high-voltage scenarios.

[0076] Exemplarily, the top of the first heat dissipation trench structure 107 is connected to the outer edge of the buried oxide layer 106, and the first heat dissipation trench structure 107 is connected to the outer edge of the buried oxide layer 106 to form a continuous isolation entity, thereby achieving vertical electrical isolation between the high-voltage DMOS region and the substrate 101 through a physical barrier, effectively blocking the vertical leakage path.

[0077] For example, the top of the first heat dissipation groove structure 107 is connected to the bottom of the first isolation structure 103 to form a continuous physical isolation barrier, which extends downward from the top surface of the epitaxial layer 102 to the bottom surface of the substrate 101, and can block the diffusion channel of lateral carriers in all directions, effectively reducing lateral leakage current, thereby meeting the stringent requirements of high-voltage application scenarios on insulation performance.

[0078] For example, the top of the first heat dissipation groove structure 107 is connected to the bottom of the lateral carrier suppression layer 105 to form a continuous physical isolation barrier. The barrier extends downward from the top surface of the epitaxial layer 102 to the bottom surface of the substrate 101, which can block the diffusion channel of lateral carriers in all directions and effectively reduce the lateral leakage current, thereby meeting the stringent requirements of high-voltage application scenarios on insulation performance.

[0079] It is particularly worth noting that when the top of the first heat dissipation groove structure 107 is simultaneously connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105, a complete isolation system covering three-dimensional space can be formed, thereby comprehensively improving the device's voltage resistance and insulation performance, and meeting the application requirements of high-voltage power integrated circuits.

[0080] In some embodiments, as Figure 4C As shown, a metal heat conductor 1072 and an insulating layer 1071 are arranged on the side wall of the metal heat conductor 1072, the end of the metal heat conductor 1072 close to the epitaxial layer 102 is connected to the high-voltage device 110, and the end away from the epitaxial layer 102 is connected to the external heat sink, and the end of the insulating layer 1071 close to the epitaxial layer 102 is connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105.

[0081] Taking the formation of the first heat dissipation groove structure 107 distributed along the edge of the high-voltage device 110 in the substrate 101 as an example, it is specifically implemented by the following process: first, a patterned mask layer is formed on the back side of the substrate 101, and the mask layer defines the pattern of the groove to be formed along the edge of the high-voltage device 110; then, etching is performed based on the mask layer to form a groove distributed along the edge of the high-voltage device 110, and the groove extends from the side of the substrate 101 away from the epitaxial layer 102 into the substrate 101 and penetrates the substrate 101. The end of the trench close to the epitaxial layer 102 exposes the high-voltage device 110, and the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 103 are also exposed at this end. 5. An insulating material is deposited on the sidewall of the trench to form an insulating layer 1071, which forms an electrical insulating barrier to avoid short circuit with the surrounding semiconductor materials. At the same time, the end of the insulating layer 1071 close to the epitaxial layer 102 is connected to the buried oxide layer 106, the first isolation structure 103 and the lateral carrier suppression layer 105; a metal thermal conductive material is filled in the trench in the insulating layer to form a metal thermal conductor 1072. The filling can be dense and the surface can be flattened by electroplating or physical vapor deposition (PVD) combined with chemical mechanical polishing (CMP) process, so that the top end of the metal thermal conductor 1072 is directly connected to the high-voltage device 110, and the bottom end of the metal thermal conductor 1072 is connected to the external heat sink formed subsequently.

[0082] In some embodiments, as Figure 1 As shown, the first heat dissipation trench structure 107 gradually decreases in size from the end closest to the substrate 101 to the end closest to the epitaxial layer 102. This design can create a larger heat dissipation contact area on the substrate 101 side, enhancing the efficiency of heat removal from the high-voltage device 110. This allows the heat generated during operation of the high-voltage device 110 to quickly diffuse and dissipate toward the substrate 101 through the first heat dissipation trench structure 107, significantly improving the overall heat dissipation capability, helping to lower the operating temperature of the high-voltage device 110, and reducing performance degradation caused by heat accumulation, thereby improving the reliability and operational stability of the high-voltage device 110.

[0083] Of course, the present application is not limited to the first heat dissipation groove structure 107 adopting the above-mentioned morphology. It can also adopt other morphologies, such as a cylindrical structure with uniform dimensions along its extension direction, etc., and the present application does not limit this. Then, if Figure 2 As shown, the manufacturing method also includes: forming at least one second heat dissipation groove structure 108 in the substrate 101 below the buried oxide layer 106, the second heat dissipation groove structure 108 extends from the side of the substrate 101 away from the epitaxial layer 102 into the substrate 101 to penetrate the buried oxide layer 106 and be connected to the high-voltage device 110, and the end of the second heat dissipation groove structure 108 away from the epitaxial layer 102 is used to connect to an external heat sink.

[0084] The second heat dissipation groove structure 108 is dispersedly distributed below the high-voltage device 110, forming a "lattice-type" heat dissipation solution. The top end of the second heat dissipation groove structure 108 extends upward through the buried oxide layer 106 and is connected to the bottom surface of the high-voltage device 110 to be close to the heat core area. The bottom end is connected to the external heat dissipation plate to quickly dissipate heat. By increasing the density of the heat dissipation path (i.e., increasing the number of the second heat dissipation groove structures 108), the local accumulated heat below the high-voltage device 110 can be targeted and directed, effectively solving the local hot spot problem in the high-voltage working scenario.

[0085] The material of the second heat dissipation trench structure 108 may be copper, tungsten, etc., which is not limited.

[0086] In some embodiments, the size of the second heat dissipation groove structure 108 can be larger than the size of the first heat dissipation groove structure 107. Specifically, the first heat dissipation groove structure 107 is arranged in a ring shape along the edge of the high-voltage device 110, which can form a surround heat dissipation for the peripheral area of ​​the high-voltage device 110; the second heat dissipation groove structure 108 is located within the area enclosed by the first heat dissipation groove structure 107 and is arranged corresponding to the bottom of the high-voltage device 110, and can directly act on the core heating area of ​​the high-voltage device 110. By making the size of the second heat dissipation groove structure 108 larger than the first heat dissipation groove structure 107, a wider heat dissipation channel can be formed in the core heating area at the bottom of the high-voltage device 110, significantly increasing the heat dissipation contact area and heat conduction cross-section of this area, enhancing the ability to quickly remove heat from the core area, and preventing heat accumulation in the core area.

[0087] Of course, the present application is not limited to the first heat dissipation groove structure 107 and the second heat dissipation groove structure 108 having only the above-mentioned size relationship. The two can also have other size relationships, for example, the size of the first heat dissipation groove structure 107 is consistent with the size of the second heat dissipation groove structure 108, etc. The present application does not limit this.

[0088] In addition, the back side of the substrate 101 may be thinned to control the thickness of the substrate 101 , and an external heat dissipation plate connected to the heat dissipation groove structure may be deposited on the back side of the substrate 101 .

[0089] At this point, the process steps of the BCD device and the manufacturing method thereof according to the embodiments of the present application are completed. It can be understood that the BCD device and the manufacturing method thereof according to the embodiments of the present application not only include the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the method of the embodiments of the present application.

[0090] In summary, according to the BCD device and its manufacturing method of the embodiments of the present application, the buried oxide layer 106 serves as a vertical isolation structure, forming a vertical insulation barrier in the region of the substrate 101 corresponding to the high-voltage device 110, thereby achieving vertical electrical isolation between the high-voltage region and the substrate 101. The lateral carrier suppression layer 105 is located between the first isolation structure 103 and the second isolation structure 104, effectively suppressing the lateral diffusion of carriers, forming a lateral isolation barrier, avoiding crosstalk between the high-voltage region and the low-voltage region, and reducing the risk of lateral leakage. The hybrid isolation mechanism formed by the combination of the two breaks through the limitation of traditional physical isolation (such as DTI or single PN junction isolation) that relies only on isolation in a single direction. It can simultaneously take into account efficient vertical and lateral isolation, blocking potential leakage paths of carriers as much as possible, thereby meeting the insulation requirements in high-voltage scenarios.

[0091] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present application. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0092] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various application aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach of the present application should not be interpreted as reflecting the intention that the claimed application requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the point of the application is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0093] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0094] It should be noted that the above embodiments are illustrative rather than limiting of the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The use of the words first, second, and third, etc., does not denote any order. These words may be interpreted as designations.

Claims

1. A BCD device, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; A first isolation structure and a second isolation structure are spaced apart and arranged in the epitaxial layer; a high-voltage device, disposed in the epitaxial layer surrounded by the first isolation structure; a low-voltage device, disposed in the epitaxial layer surrounded by the second isolation structure; a lateral carrier suppression layer, disposed in the epitaxial layer between the first isolation structure and the second isolation structure; A buried oxide layer is provided in a region of the substrate corresponding to the high-voltage device.

2. The BCD device according to claim 1, wherein: The substrate is also provided with a first heat dissipation groove structure distributed along the edge of the high-voltage device. The first heat dissipation groove structure extends from the side of the substrate away from the epitaxial layer into the substrate and passes through the substrate. The end of the first heat dissipation groove structure close to the epitaxial layer is connected to the high-voltage device, and this end is also respectively connected to the buried oxide layer, the first isolation structure and the lateral carrier suppression layer. The end of the first heat dissipation groove structure away from the epitaxial layer is used to connect to an external heat sink.

3. The BCD device according to claim 2, wherein: The first heat dissipation groove structure includes a metal heat conductor and an insulating layer arranged on the side wall of the metal heat conductor, the end of the metal heat conductor close to the epitaxial layer is connected to the high-voltage device, and the end away from the epitaxial layer is connected to the external heat dissipation plate, and the end of the insulating layer close to the epitaxial layer is connected to the buried oxide layer, the first isolation structure and the lateral carrier suppression layer.

4. The BCD device according to claim 2, wherein: The first heat dissipation groove structure has a size that gradually decreases from an end close to the substrate to an end close to the epitaxial layer.

5. The BCD device according to claim 1, wherein: At least one second heat dissipation groove structure is provided in the substrate below the buried oxide layer. The second heat dissipation groove structure extends from the side of the substrate facing away from the epitaxial layer into the substrate to pass through the buried oxide layer and be connected to the high-voltage device. The end of the second heat dissipation groove structure facing away from the epitaxial layer is used to be connected to an external heat dissipation plate.

6. The BCD device according to claim 1, wherein: The lateral carrier suppression layer is a heavily doped region of the first conductivity type. The lateral carrier suppression layer also penetrates the epitaxial layer and extends into the substrate.

7. The BCD device according to claim 1, wherein: The high-voltage device includes a DMOS device, and the low-voltage device includes a CMOS device and a Bipolar device.

8. A method for manufacturing a BCD device according to any one of claims 1 to 7, characterized in that: include: providing a substrate; forming an epitaxial layer on the substrate; forming a buried oxide layer in the substrate, wherein the buried oxide layer is located in a region of the substrate corresponding to a high-voltage device to be subsequently formed; forming a lateral carrier suppression layer and a first isolation structure and a second isolation structure spaced apart in the epitaxial layer, wherein the lateral carrier suppression layer is located in the epitaxial layer between the first isolation structure and the second isolation structure; A high-voltage device is formed in the epitaxial layer surrounded by the first isolation structure, and a low-voltage device is formed in the epitaxial layer surrounded by the second isolation structure.

9. The manufacturing method according to claim 8, wherein: Also includes: forming a patterned mask layer on the back side of the substrate, wherein the mask layer defines a pattern of trenches to be formed and distributed along the edge of the high-voltage device; Etching is performed based on the mask layer to form a trench distributed along the edge of the high-voltage device, wherein the trench extends from a side of the substrate facing away from the epitaxial layer into the substrate and penetrates the substrate, wherein an end of the trench close to the epitaxial layer exposes the high-voltage device, and the buried oxide layer, the first isolation structure, and the lateral carrier suppression layer are also exposed at the same end; depositing an insulating material on a sidewall of the trench to form an insulating layer; The grooves in the insulating layer are filled with a metal heat conductive material to form a metal heat conductor.

10. The manufacturing method according to claim 8, wherein A lateral carrier suppression layer is formed in the epitaxial layer, comprising: forming the lateral carrier suppression layer by tilted ion implantation, wherein the angle of the tilted implantation is 30° to 60°, and the lateral carrier suppression layer is a heavily doped region of the first conductivity type.

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