Chip testability design method, electronic equipment and computer readable storage medium

Abstract

The invention discloses a chip testability design method, electronic equipment and a computer readable storage medium, and relates to the technical field of integrated circuit design and testing.The chip testability design method comprises the steps that multiple test items of a chip are obtained, the multiple test items at least comprise a first test item and a second test item, and the first test item and the second test item are matched with each other; the first test item is a test item for a first module group of the chip, the second test item is a test item for a second module group of the chip, and the first module group is different from the second module group; test parameters of the first test item are configured through the JTAG port, and a first main body operation stage corresponding to the first test item is entered; and during the running period of the first main body running stage, testing parameters of the second testing item are configured through the JTAG port, and a second main body running stage corresponding to the second testing item is entered. The test time can be shortened, and the test cost can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design and testing, and in particular to a chip testability design method, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of information technology, large-scale integration (LSI) is increasingly used in modern society. These highly integrated circuit systems are characterized not only by their diverse functionality but also by their stringent requirements for performance, reliability, and cost-effectiveness. As an integral part of ensuring chip quality, Design for Testability (DFT) technology has seen significant development and application in recent years.

[0003] DFT technologies primarily include SCAN (scan chain) technology, memory built-in self-test (MBIST), and intellectual property core testing (IPTEST), among other methods. These methods work together to ensure the reliability of LSI products. SCAN technology transforms circuits into scannable shift register chains, enabling controllable and observable internal states and greatly simplifying the testing process. MBIST specifically targets on-chip memories, implementing self-testing through embedded test algorithms, improving test efficiency and reducing reliance on external test equipment. IPTEST is primarily used to verify the functional correctness of each independent intellectual property (IP) core within an integrated circuit, ensuring stable operation of the overall system.

[0004] However, with the continued expansion of chip sizes and increasingly stringent market quality standards, traditional DFT technology faces new challenges. To comprehensively cover all possible fault points within a chip, the testing process requires the generation of a large number of test parameters (SCAN vectors). The number of these vectors increases exponentially with chip size, directly increasing test time and costs, becoming a key bottleneck restricting further improvements in IC test efficiency. Therefore, how to shorten test time and reduce test costs while ensuring chip test quality and coverage has become a pressing technical challenge. Summary of the Invention

[0005] The main purpose of this application is to provide a chip testability design method, electronic device and computer-readable storage medium, aiming to solve the technical problem of how to shorten the test time and reduce the test cost while ensuring the chip test quality and coverage.

[0006] To achieve the above objectives, the present application provides a chip testability design method, comprising: Acquire multiple test items of a chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, the first module group being different from the second module group; Configuring test parameters of the first test item through the JTAG port and entering a first main body operation phase corresponding to the first test item, wherein the first main body operation phase is used to generate first test result information corresponding to the first test item; During the operation of the first main body operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main body operation phase corresponding to the second test item is entered, wherein the second main body operation phase is used to generate second test result information corresponding to the second test item.

[0007] In addition, to achieve the above objectives, the present application also provides a chip testability design method, including: Acquire multiple test items for a chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, the third IP test item is an IP test item for a first module of the chip, the fourth IP test item is an IP test item for a second module of the chip, and the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; By broadcasting signals from the JTAG port, the test parameters of the third IP test item and the test parameters of the fourth IP test item are configured in parallel, and a third main operation phase corresponding to the third IP test item and a fourth main operation phase corresponding to the fourth IP test item are entered; The third main body operation phase is used to generate third test result information corresponding to the third IP test test item, and the fourth main body operation phase is used to generate fourth test result information corresponding to the fourth IP test test item.

[0008] In addition, to achieve the above-mentioned purpose, the present application also provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and runnable on the processor, and when the computer program is executed by the processor, it implements the chip testability design method as described above.

[0009] In addition, to achieve the above-mentioned purpose, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the chip testability design method as described above is implemented.

[0010] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the chip testability design method as described above.

[0011] Given the above background, there is still much room for improvement in chip testability design technology in the related art. It is necessary to develop a method that can not only ensure test quality but also efficiently shorten test time, which is of great significance to promoting the sustainable development of the semiconductor industry. Based on this, the applicant has spent a lot of time and energy on countless experiments. After countless experiments, it was finally discovered through research that it is possible to make full use of the principle that the JTAG port is in an idle state during the main operation phase of the test item (according to statistics, the duration of the main operation phase is much longer than the configuration and observation time) by cleverly taking advantage of the principle that the JTAG port is in an idle state during the main operation phase of the test item (according to statistics, the duration of the main operation phase is much longer than the configuration and observation time). The test parameters of other test items can be configured through the JTAG port, and the test vectors of multiple test items can be tested in parallel. This can reasonably utilize the idle time of the JTAG network, reduce the total time for running all test parameters, and save testing costs on ATE (Automatic Test Equipment) machines.

[0012] In the DFT testing technology, IP test only uses the JTAG port during the configuration and observation process. During the main test time, the chip is operating on its own. At this time, the JTAG port is idle. SCAN only needs to use the JTAG port in the configuration stage. During the main test (i.e., during the main operation stage), the chip's SCAN in and SCAN out paths are used. Based on this, the embodiment of the present application provides a chip testability design method, an electronic device, and a computer-readable storage medium. The technical solution of the embodiment of the present application is to obtain multiple test items of the chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for the first module group of the chip, and the second test item is a test item for the second module group of the chip, and the first module group is different from the second module group; configure the test parameters of the first test item through the JTAG port, and enter the first main operation stage corresponding to the first test item, wherein the first main operation stage is used to generate the first test result information corresponding to the first test item; during the operation of the first main operation stage, configure the test parameters of the second test item through the JTAG port, and enter the second main operation stage corresponding to the second test item, which In the embodiment, the second main operation phase is used to generate second test result information corresponding to the second test item, so that the embodiment of the present application can make full use of the idle time of the JTAG port, reduce the need to test each test item serially, and cause each test item to queue up and wait for processing and idle time wasted. Since most of the wasted test time is mainly the duration of the main operation phase of each test item, this embodiment cleverly utilizes the period when the JTAG port is idle during the main operation phase to configure test parameters for other test items through the JTAG port, thereby realizing parallel testing of test vectors of multiple test items, saving testing costs on ATE machines, improving the utilization rate of ATE machines, and effectively solving the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without any creative work.

[0015] Figure 1A flowchart illustrating the first embodiment of the chip testability design method of the present application; Figure 2 A flowchart illustrating a second embodiment of the chip testability design method of the present application; Figure 3 This is a schematic diagram of the overall circuit structure of the DFT parallel measurement technology in a specific embodiment of the present application; Figure 4 This is a schematic diagram of converting an IPTEST serial test to a parallel test in a specific embodiment of the present application; Figure 5 This is a schematic diagram of converting the same type of IPTEST serial test to broadcast parallel test in a specific embodiment of the present application; Figure 6 This is a schematic diagram of converting the SCAN test and IPTEST serial test into a parallel test in a specific embodiment of the present application; Figure 7 Schematic diagram of the device structure of the hardware operating environment involved in the chip testability design method in the embodiment of the present application.

[0016] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0017] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0018] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0019] In traditional DFT technology, all test items must be executed sequentially in a serial test mode. Each test item must wait for the previous test item to complete its main operation phase before configuration can begin. The JTAG port responsible for configuration is idle during the main operation of different test items and is not effectively utilized, resulting in a long test process and high test costs on ATE.

[0020] To this end, the applicant spent a lot of time and energy conducting countless experiments. After countless experiments, it was finally discovered through research that it is possible to make full use of the principle that the JTAG port is in an idle state during the main operation phase of the test item (statistically, the duration of the main operation phase is much longer than the configuration and observation time) by cleverly utilizing the period when the JTAG port is in an idle state during the main operation phase, configure test parameters for other test items through the JTAG port, and realize parallel testing of test vectors of multiple test items. This can reasonably utilize the idle time of the JTAG network, reduce the total time for running all test parameters, and save testing costs on ATE (Automatic Test Equipment) machines.

[0021] On this basis, an embodiment of the present application provides a solution: obtaining multiple test items of a chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, and the first module group is different from the second module group; configuring the test parameters of the first test item through the JTAG port, and entering the first main body operation phase corresponding to the first test item, wherein the first main body operation phase is used to generate first test result information corresponding to the first test item; during the operation of the first main body operation phase, configuring the test parameters of the second test item through the JTAG port, entering the second main body operation phase corresponding to the second test item, wherein the second main body operation phase is used to generate second test result information corresponding to the second test item.

[0022] The embodiment of the present application can make full use of the idle time of the JTAG port, reduce the need to test each test item serially, and reduce the idle time wasted by each test item having to queue up and wait for processing. Since most of the wasted test time is mainly the duration of the main operation phase of each test item, this embodiment cleverly utilizes the period when the JTAG port is idle during the main operation phase to configure test parameters for other test items through the JTAG port, thereby realizing parallel testing of test vectors of multiple test items, saving testing costs on ATE machines, and improving the utilization rate of ATE machines, thereby effectively solving the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage.

[0023] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0024] This application proposes a chip testability design method according to a first embodiment.

[0025] Please refer to Figure 1 , Figure 1 A flowchart illustrating the first embodiment of the chip testability design method of the present application.

[0026] In this embodiment, the chip testability design method includes steps S100 to S300: Step S100, obtaining multiple test items of a chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, the first module group being different from the second module group; It's important to note that during the design of large-scale integrated circuits (LSIs), chips are typically divided into multiple modules. Each module is a relatively independent logical unit or physical area within the chip. During chip testing, all modules can be flexibly divided into several module groups based on requirements, with each module group containing at least one module.

[0027] In this embodiment, the multiple modules of the chip are divided into at least a first module group and a second module group, and there are no common modules between the first module group and the second module group, ensuring that the first module group is different from the second module group to avoid the situation where the same module executes multiple test items at the same time during parallel testing, resulting in I / O (Input / Output) conflicts.

[0028] Those skilled in the art will appreciate that in DFT technology, a test item refers to a test task for the functional or structural design of a chip's internal modules, and is primarily divided into IP test items and SCAN test items. The IP test item refers to a test task that uses IPTEST technology to perform functional verification of a chip's internal IP core, while the SCAN test item refers to a test task that uses SCAN technology to perform structural testing of a chip's internal circuits. Whether it's an IP test item or a SCAN test item, the test process can be divided into a configuration phase, a main operation phase, and a signal observation phase. The configuration phase refers to the process of configuring test parameters. Test parameters refer to the parameter variables that need to be pre-configured on the module under test during the test process, primarily including test vectors, clock frequencies, voltage thresholds, timing constraints, fault coverage targets, etc. Test vectors include input stimulus signals and corresponding expected output responses. The main operation phase refers to the process of running the test logic and outputting test results. Test logic refers to the internal self-test logic that needs to be executed on the module under test during the test process. Test results refer to the output responses obtained by running the test logic under the configured test parameters during the test process. The signal observation phase refers to the process of observing the test results. By comparing the test results with the expected output response in the test vector, it can be determined whether the module under test has functional defects, performance deviations, or abnormal electrical characteristics.

[0029] Step S200: configuring test parameters of a first test item through a JTAG port, and entering a first main body running phase corresponding to the first test item, wherein the first main body running phase is used to generate first test result information corresponding to the first test item; Step S300, during the operation of the first main operation phase, configure the test parameters of the second test item through the JTAG port, and enter the second main operation phase corresponding to the second test item, wherein the second main operation phase is used to generate second test result information corresponding to the second test item.

[0030] It should be noted that the JTAG (Joint Test Action Group) port is a test access port whose functions at least include configuration of test parameters and reading back (ie, observation) of test results.

[0031] It should also be noted that, in this embodiment, the first main execution phase refers to the main operation phase corresponding to the first test item, the second main execution phase refers to the main operation phase corresponding to the second test item, the first test result information refers to the test result generated by the first module group after executing the first main operation phase, and the second test result information refers to the test result generated by the second module group after executing the second main operation phase.

[0032] Those skilled in the art will know that the IP test item only uses the JTAG port to configure test parameters and read back test results in the configuration stage and signal observation stage. The JTAG port is not required for signal transmission in the main operation stage, and the test logic only relies on the internal circuit of the chip to run independently. The SCAN test item only needs to use the JTAG port in the configuration stage. The chip's SCAN in / SCAN out port is used in the main operation stage. Therefore, in the main operation stage corresponding to each test item, the JTAG port is in an idle state.

[0033] In traditional serial test modes, all test items must be executed sequentially. This means that the JTAG port can only begin configuring the test parameters for the next test item after the previous test item completes the entire process of parameter configuration, main execution, and result observation. Because the main execution phase typically accounts for over 80% of the total test duration (for example, the long computation cycles of functional tests or the large-scale shift operations of SCAN tests), in traditional serial test modes, the JTAG port remains idle most of the time, resulting in lengthy test times, low ATE tool utilization, and high test costs.

[0034] To this end, this embodiment identifies and utilizes the idle time window of the JTAG port in the first main operation phase, embeds the test parameter configuration of the second test item into the main operation phase of the first test item, and realizes time and space decoupling between the test parameter configuration of the second test item and the test logic operation of the first test item, thereby eliminating the waste of idle JTAG ports caused by waiting for the entire process of the previous test item to be completed before the test parameter configuration of the next test item in the traditional serial test mode, and realizes parallel testing of the test vectors loaded by each of the main operation phases of multiple test items, saving the test cost on the ATE machine and improving the utilization rate of the ATE machine, thereby effectively solving the technical problem of how to shorten the test time and reduce the test cost under the premise of ensuring the chip test quality and coverage.

[0035] In this embodiment, before entering the first main body operation phase corresponding to the first test item in step S200, the chip testability design method may further include step A10: Step A10: Isolate other SCAN signals and / or other IP TEST signals through the JTAG network to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item; Among them, other SCAN signals are SCAN signals that are not related to each test item, and other IP TEST signals are IP TEST signals that are not related to each test item.

[0036] It should be noted that the JTAG network refers to the test access path built through the JTAG protocol, which is used to debug and test the internal or external interfaces of the chip, allowing access to the internal status of the chip without interfering with the normal operation of the system, and performing configuration, testing and diagnostic tasks.

[0037] It should be noted that the JTAG port is a specific hardware interface that implements the JTAG function and is used to connect external test equipment (such as ATE machines) with the internal chip, while the JTAG network is an interconnected test environment created using the JTAG port and the JTAG protocol. That is, in testability design, external test equipment sends commands and data through the JTAG port, which are then transmitted to the internal modules of the chip via the JTAG network.

[0038] It should also be noted that SCAN signals refer to signals used during the SCAN test process, including control signals such as SCAN in (scan input), SCAN out (scan output), and SCAN enable (scan enable). IP TEST signals refer to signals used during the IPTEST process, involving test stimuli and responses specific to a particular IP core, used to verify the functional correctness of the IP core.

[0039] This embodiment uses the JTAG network to isolate other SCAN signals and / or other IP TEST signals that are not related to each test item before entering the first main operation phase corresponding to the first test item, ensuring that the ongoing test item is not affected by other non-related signals, thereby improving the accuracy and reliability of the test results.

[0040] It is worth mentioning that the specific isolation means may be to clamp other SCAN signals and / or other IP TEST signals, or to insert a wrapper cell into other SCAN signals and / or other IP TEST signals. Those skilled in the art have conducted in-depth research on this, and this embodiment will not elaborate on this.

[0041] In a feasible implementation manner, the first test item is a first IP test item, the second test item is a second IP test item, and the chip testability design method may further include step S410 or step S420: Step S410, when the first main body operation phase is completed earlier than the second main body operation phase, during the period between the completion of the first main body operation phase and the start of the second main body operation phase, observing the generated first test result information through the JTAG port; Alternatively, in step S420, when the second main body operation phase is completed earlier than the first main body operation phase, the generated second test result information is observed through the JTAG port during the period between the second main body operation phase and the first main body operation phase.

[0042] It should be noted that the first IP test item is an IP test item for the first module group of the chip, and the second IP test item is an IP test item for the second module group of the chip.

[0043] In this embodiment, the first test item and the second test item are both IP test items. Therefore, in the signal observation phases corresponding to the first test item and the second test item, the test results need to be observed through the JTAG port.

[0044] Due to the diversity of IP cores, including but not limited to DDR (Double Data Rate), SerDes (Serializer / Deserializer), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), GEPHY (Gigabit Ethernet PHYsical layer), POR (Power-On Reset), PVT-Sensor (Process, Voltage, and Temperature Sensor), and PLL (Phase-Locked Loop), when performing functional testing on different types of IP cores, the types of IP test items (also known as IP test types) required to be applied are also different, and the main running phase corresponding to each type of IP test item varies in length.

[0045] In view of this, this embodiment dynamically adjusts the order of observing the test results corresponding to each IP test item through the JTAG port according to the end order of the main operation phase corresponding to each IP test item, that is, according to the generation order of the test results corresponding to each IP test item. Therefore, when the main operation phase corresponding to a certain IP test item ends first and generates the corresponding test result, the idle time window of the JTAG port when other test items are still in the main operation phase is utilized to observe the test result corresponding to the first completed IP test through the JTAG port, thereby fully utilizing the idle time period of the JTAG port, and embedding the signal observation phase of the IP test item that ends the main operation phase first into the main operation phase of the IP test item that ends the main operation phase later, greatly reducing the time wasted by the IP test item that ends the main operation phase later due to waiting for the IP test item that ends the main operation phase first to complete the test result observation, achieving the effect of time and space decoupling, reducing the resource conflict on the JTAG port during the signal observation phase of each IP test item, thereby improving the utilization rate of the JTAG port, significantly shortening the overall test time, and reducing the test cost of the ATE machine.

[0046] In another feasible implementation, the first test item is a SCAN test item, the second test item is a second IPtest test item, and the chip testability design method may further include step S430: Step S430 , when the second main body operation phase is completed earlier than the first main body operation phase, during the period between the completion of the second main body operation phase and the execution of the first main body operation phase, the generated second test result information is observed through the JTAG port.

[0047] In this embodiment, the first test item is the SCAN test item, and its corresponding signal observation phase does not require observation of the test results through the JTAG port, while the second test item is the IP test test item, and the test results need to be observed through the JTAG port in the signal observation phase. Therefore, this embodiment combines the characteristics of the SCAN test item and the IP test test item, and cleverly utilizes the differences in the use requirements of different types of test items for the JTAG port at different stages. When the main operation phase corresponding to the IP test test item ends first, the signal observation phase of the IP test test item is embedded in the main operation phase of the SCAN test item, thereby making full use of the idle time period of the JTAG port, completing the signal observation phase of the IP test test item as soon as possible, reducing the idle time of the JTAG port resources, improving the utilization rate of the ATE machine, and making the overall test process more compact and efficient, thereby reducing test costs and improving test efficiency while ensuring test coverage and test quality.

[0048] In another feasible implementation, the first test item is a first IP test item, the second test item is a SCAN test item, and the chip testability design method may further include step S440: Step S440 , when the first main body operation phase is completed earlier than the second main body operation phase, during the period between the completion of the first main body operation phase and the second main body operation phase, the generated first test result information is observed through the JTAG port.

[0049] In one example, when the second main body operation phase is completed before the first main body operation phase, no processing is performed during the period when the second main body operation phase is completed and is in the operation of the first main body operation phase, and when the first main body operation phase is completed, the generated first test result information is observed through the JTAG port.

[0050] In this embodiment, the second test item is the SCAN test item, and its corresponding signal observation phase does not require observation of the test results through the JTAG port, while the first test item is the IP test test item, and the test results need to be observed through the JTAG port in the signal observation phase. Therefore, this embodiment combines the characteristics of the SCAN test item and the IP test test item, and cleverly utilizes the differences in the use requirements of different types of test items for the JTAG port at different stages. When the main operation phase corresponding to the IP test test item ends first, the signal observation phase of the IP test test item is embedded in the main operation phase of the SCAN test item, thereby making full use of the idle time period of the JTAG port, completing the signal observation phase of the IP test test item as soon as possible, reducing the idle time of the JTAG port resources, improving the utilization rate of the ATE machine, and making the overall test process more compact and efficient, thereby reducing test costs and improving test efficiency while ensuring test coverage and test quality.

[0051] It is worth mentioning that when the chip has fewer test items to complete and can complete the test parameter configuration of all test items before the end of the main operation phase corresponding to any test item, after completing the test parameter configuration of all test items, the test results of each test item can be observed in sequence according to the end order of the main operation phase corresponding to each test item. Alternatively, the observation order of the test results of each test item can be determined in advance based on the importance and urgency of each test item, and then in actual application, the test results of each test item can be observed in sequence according to the predetermined observation order.

[0052] For example, when the test items that the chip needs to complete include IP test item a for module group A, IP test item b for module group B, and IP test item c for module group C, the configuration phase corresponding to a requires 1 second, the configuration phase corresponding to b requires 2 seconds, the configuration phase corresponding to c requires 3 seconds, the main operation phase corresponding to a requires 10 seconds, the main operation phase corresponding to b requires 12 seconds, and the main operation phase corresponding to c requires 15 seconds. After taking 6 seconds to complete the configuration phases a, b, and c in sequence, the main operation phase corresponding to each IP test item has not yet ended. That is, the chip needs to complete fewer test items, and the test parameter configuration of all test items can be completed before the main operation phase corresponding to any test item ends. At this time, the test parameters can be configured according to the configuration phases of each IP test item. The main running phases corresponding to the test items of test are ended in order, and the test results of each test item are observed in turn, so that when the main running phase corresponding to a ends at the 11th second and the main running phases corresponding to b and c have not yet ended, the signal observation phase corresponding to a is immediately entered through the JTAG port, so as to end the signal observation phase corresponding to a before the end of the main running phases corresponding to b and c as much as possible. Accordingly, when the signal observation phase corresponding to a ends and the main running phase corresponding to b is in progress, the signal observation phase corresponding to b is immediately entered through the JTAG port, so as to end the signal observation phase corresponding to b before the end of the main running phase corresponding to c as much as possible, thereby making the best use of the idle time of the JTAG port to complete the configuration of test parameters and the observation of test results.

[0053] In addition, when the chip needs to complete a large number of test items, the main operation phase corresponding to a certain IP test item has ended, but some test items have not yet been configured with test parameters, you can choose to complete the test parameter configuration of the remaining test items through the JTAG port first, and then observe the test results of the IP test items whose main operation phase has ended through the JTAG port. You can also choose to observe the test results of the IP test items whose main operation phase has ended through the JTAG port first, and then return to complete the test parameter configuration of the remaining test items through the JTAG port. This application proposes a chip testability design method according to a second embodiment.

[0054] Please refer to Figure 2 , Figure 2 A flowchart illustrating the second embodiment of the chip testability design method of the present application.

[0055] In the second embodiment of the present application, for the same or similar contents as those in the above embodiments, please refer to the above introduction and will not be repeated hereafter.

[0056] In this embodiment, the chip testability design method may include steps S500 to S600: Step S500: Acquire multiple test items of the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, the third IP test item is an IP test item for a first module of the chip, the fourth IP test item is an IP test item for a second module of the chip, and the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; In this embodiment, the first module includes a first IP core, the second module includes a second IP core, the third IP test item is actually an IP test item for the first IP core, the fourth IP test item is actually an IP test item for the second IP core, and the first IP core and the second IP core are different IP cores of the same type. Therefore, the third IP test item and the fourth IP test item have the same IP test type, the required configuration test parameters are also the same, and can be configured in parallel through signal broadcasting.

[0057] It is worth mentioning that, in this embodiment, the first module and the second module can be the same module or different modules.

[0058] Step S600: configuring the test parameters of the third IP test item and the fourth IP test item in parallel through signal broadcasting of the JTAG port, and entering the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item; The third main body operation phase is used to generate third test result information corresponding to the third IP test test item, and the fourth main body operation phase is used to generate fourth test result information corresponding to the fourth IP test test item.

[0059] Those skilled in the art will recognize that signal broadcasting refers to a technique used in testing or communication systems to simultaneously send the same information or instructions to multiple target devices or modules via a common channel (such as a JTAG port). In this mode, information is not transmitted one-on-one to specific targets, but rather broadcasted, allowing all receivers connected to the common channel to receive the same information. This method can significantly improve data transmission efficiency and is particularly effective when the same operation needs to be performed on multiple similar devices or modules.

[0060] In this embodiment, since the first IP core and the second IP core are IP cores of the same type, and the IP test type of the third IP test item and the fourth IP test item is the same, the same test parameters can be used for configuration in the configuration stage of the third IP test item and the fourth IP test item, and then the test parameters of the third IP test item and the fourth IP test item can be configured at the same time through the signal broadcasting method of the JTAG port, so that the configuration stages of multiple test items are executed in parallel, thereby avoiding the configuration of test parameters for each test item in turn, greatly reducing the total time required for the test parameter configuration corresponding to each test item in the entire chip testing process, thereby significantly improving the test efficiency and reducing the test cost.

[0061] It is not difficult to understand that when there are multiple (two or more) IP cores of the same type that need to execute IP test items of the same IP test type, the test parameters of each IP test item can be configured in parallel through the signal broadcast method of the JTAG port, thereby executing the configuration phase of multiple IP test items in parallel.

[0062] In this embodiment, before entering the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item in step S600, the chip testability design method may further include step B10: Step B10: Isolating other SCAN signals and / or other IP TEST signals through the JTAG network to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item; Among them, other SCAN signals are SCAN signals that are not related to each test item, and other IP TEST signals are IP TEST signals that are not related to each test item.

[0063] Before entering the main operation phase corresponding to each test item, this embodiment isolates other SCAN signals and / or other IP TEST signals that are not related to each test item through the JTAG network, thereby ensuring that the ongoing test item is not affected by other non-related signals, thereby improving the accuracy and reliability of the test results.

[0064] In a feasible embodiment, after entering the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item in step S600, the chip testability design method may further include step S710: Step S710 : After the third main body operation phase and the fourth main body operation phase are executed, the generated third test result information and the fourth test result information are observed through the JTAG port.

[0065] In this embodiment, since the IP test type of the first IP test item and the IP test type of the second IP test item are the same, and the same test parameters are configured in parallel through signal broadcasting, this means that the main operation phases corresponding to each test item start almost at the same time and have basically the same duration. Correspondingly, the main operation phases corresponding to each test item also end almost at the same time. Therefore, there will inevitably be resource competition for the JTAG port in the signal observation phase of each test item, and the signal observation phase of this test item cannot be embedded in the main operation phase of another test item.

[0066] In view of this, this embodiment can serially observe the test results of each test item through the JTAG port in sequence through a serial observation method, or can improve the hardware circuit structure so that the JTAG port can observe the test results of each test item in parallel, or can compress the signal to observe the test results of each test item in parallel through the JTAG port. As for the specific hardware circuit structure improvement method and signal compression method, those skilled in the art have already conducted certain research on this, and this embodiment will not elaborate on this.

[0067] It is worth mentioning that, through the above two embodiments of the present application, the present application can realize the parallelism between IP test items and IP test items, the parallelism between IP test items and SCAN test items, and the broadcast parallelism between IP test items and IP test items between different IP cores of the same type, and then combine the schemes of the above two embodiments to obtain a scheme in which different module groups have IP test items and IP test items in parallel, while IP test items are also in parallel with SCAN test items, and even IP test items of the same IP test type in the same module group are broadcast in parallel. For example, the first IP test item of module group A is parallel to the second IP test item of module group B, and the SCAN test item of module group C. At the same time, within module group A, each module synchronously executes the first IP test item by broadcasting in parallel. Within module group B, each module synchronously executes the second IP test item by broadcasting in parallel.

[0068] To facilitate understanding of the technical concept or technical principle of the above-mentioned embodiment of the chip testability design method of the present application, a specific embodiment is listed below: Large-scale integrated circuit chips contain multiple modules, some of which may include IP cores, such as DDR, SerDes, PCIE, USB, GEPHY, POR, PVT-Sensor, and PLL. IPTEST-related signals (i.e., IPTEST signals) are generally controlled uniformly via the JTAG network. The IPTEST process consists of a configuration phase, a main operation phase, and a signal observation phase. The configuration and signal observation phases require the use of the JTAG network, while the main operation phase involves the logical operations within the IP core. This phase requires no configuration and only requires waiting, so the JTAG network is idle.

[0069] As shown in Table 1, in IPTEST, the configuration phase and signal observation phase require the use of the JTAG network, and the two phases account for a very small proportion of the entire IPTEST time. However, the main operation phase does not require the JTAG network, but it takes a long time to wait for the IP core to complete operation. Table 1:

[0070] Each module in a large-scale integrated circuit chip contains SCAN logic. The control signals of the SCAN logic (i.e., SCAN signals), such as mode signals and reset signals, are also controlled by the JTAG network. The entire SCAN test process also includes the configuration phase, the main operation phase, and the signal observation phase. The difference is that the configuration phase of the SCAN test requires the use of the JTAG network, while the main operation phase and the signal observation phase use the SCAN in / SCAN out ports, which do not require the JTAG network.

[0071] As shown in Table 2, in the SCAN test, only the configuration phase requires the use of the JTAG network, and the configuration phase accounts for a very small proportion of the entire SCAN test time. The main operation phase does not require the JTAG network, but it takes a long time to wait for the SCAN logic to complete. Table 2:

[0072] Since the JTAG network is only used for a part of the time in both IPTEST and SCAN tests, and the JTAG network is idle most of the time, testing multiple IPTEST vectors (i.e., test vectors of IP test items) in parallel on the ATE machine, or testing IPTEST vectors and SCAN vectors (i.e., test vectors of SCAN test items) in parallel, can reasonably utilize the idle time of the JTAG network, reduce the total running time of all test vectors, and save testing costs on the ATE machine.

[0073] In this specific embodiment, the specific implementation scheme can be divided into the following items: (1) Parallel testing between IPTEST and IPTEST (i.e., parallel testing of IP test items); (2) Parallel testing of the same type of IP test items through broadcasting (i.e., IP test items of the same IP test type are tested in parallel through signal broadcasting); (3) Parallel testing between IPTEST and SCAN tests (i.e., parallel testing of IP test items and SCAN test items).

[0074] like Figure 3 As shown in the figure, in a medium-sized chip, there are multiple modules inside the chip, which may contain IP cores. The IPTEST signals include: clock signal, reset signal, IPTEST mode signal, JTAG interface signal and other control signals (i.e. other IPTEST signals). In IPTEST, in addition to the clock signal generated by the PLL, the reset signal, IPTEST mode signal, and JTAG interface signal are all controlled by the JTAG network. Other control signals from the module interface also need to be isolated in the IPTEST mode through the JTAG network (that is, other IP TEST signals are isolated through the JTAG network to prevent other IP TEST signals from affecting the test results corresponding to each test item). Specific isolation methods include clamping other control signals or inserting wrapper cells for other control signals.

[0075] Each module also contains SCAN logic. Figure 1 The SCAN test shown uses multiple SCAN chains. SCAN signals include the SCAN in / SCAN out signals, the SCAN mode signal, the reset signal, the clock signal, and other control signals (i.e., other SCAN signals). Similarly, in SCAN testing, the clock signal is generated by a PLL, and the reset and SCAN mode signals are controlled by the JTAG network. Other control signals from the module interface also need to be isolated through the JTAG network in SCAN mode (that is, other SCAN signals are isolated through the JTAG network to prevent other SCAN signals from affecting the test results of each test item). Specific isolation methods include clamping other control signals or inserting wrapper cells for other control signals. Unlike the JTAG interface signals in the IP core, the SCAN in / SCAN out signals in the SCAN logic are not controlled by the JTAG network.

[0076] In the parallel test of IPTEST and IPTEST, such as Figure 4As shown, the original different IPTESTs were all serial tests. This specific implementation modifies them into serial configuration phases of different IPTESTs, parallel main operation waiting phases (i.e. main operation phases), and serial signal observation phases. Thus, when the previous IPTEST is in the main operation waiting phase, the configuration phase of the next IPTEST is embedded, and when the main operation phase of the previous IPTEST ends and the next IPTEST is still in the main operation waiting phase, the signal observation phase of the previous IPTEST is embedded, thereby making full use of the time when JTAG is in an idle state in the main operation waiting phase, and realizing the parallel main operation waiting phases of each IPTEST.

[0077] That is to say, the test parameters of the first IP test item are configured through the JTAG port, and the first main body operation phase corresponding to the first IP test item is entered; during the operation of the first main body operation phase, the test parameters of the second IP test item are configured through the JTAG port, and the second main body operation phase corresponding to the second IP test item is entered; when the first main body operation phase is completed earlier than the second main body operation phase, during the operation of the first main body operation phase after the execution of the first main body operation phase is completed and in the second main body operation phase, the first test result information corresponding to the generated first IP test item is observed through the JTAG port; or, when the second main body operation phase is completed earlier than the first main body operation phase, during the operation of the second main body operation phase after the execution of the second main body operation phase is in the first main body operation phase, the second test result information corresponding to the generated second IP test item is observed through the JTAG port.

[0078] In the same IPTEST broadcast parallel test, such as Figure 5 As shown, if the same type of IP is instantiated multiple times and the design complexity is acceptable, this specific embodiment can use the JTAG broadcast method to perform broadcast parallel testing of the same type of IP Test. Specifically, in the configuration phase, the test parameters are broadcast to all IP cores of the same type at the same time through the JTAG broadcast method, so that the configuration phase of the same type of IP Test is parallel, and all IP cores of the same type are prompted to synchronously enter the main operation waiting phase, so that the main operation waiting phase of the same type of IP Test is parallel. Finally, by compressing the test results of each IP Test, the signal observation phase of the same type of IP Test is parallel, or serial observation is maintained.

[0079] That is to say, through the signal broadcasting method of the JTAG port, the test parameters of the third IP test item and the test parameters of the fourth IP test item are configured in parallel, and the third main operation phase corresponding to the third IP test item and the fourth main operation phase corresponding to the fourth IP test item are entered; after the third main operation phase and the fourth main operation phase are executed, the generated third test result information and the fourth test result information are observed through the JTAG port.

[0080] In the parallel test of IPTEST and SCAN test, such as Figure 6 As shown, the original SCAN test and IPTEST are serial tests. This specific implementation modifies them into the following test process: first, the JTAG port is used to complete the configuration phase of the SCAN test, and then the SCAN test enters the main test phase. At this time, the JTAG port can be used to perform the configuration phase of IPTEST. It is not difficult to understand that in the above-mentioned parallel test of IPTEST and SCAN test, the serial order of the configuration phase of IPTEST and SCAN test can be swapped. In addition, when there are multiple different IPTESTs, you can refer to the parallel test of IPTEST and SCAN test. Figure 4 The shown scheme is embedded in IPTEST and tested in parallel with IPTEST.

[0081] That is to say, the test parameters of the IP test item are configured through the JTAG port, and the first main operation phase corresponding to the IP test item is entered; during the operation of the first main operation phase, the test parameters of the SCAN test item are configured through the JTAG port, and the second main operation phase corresponding to the SCAN test item is entered; when the first main operation phase is completed earlier than the second main operation phase, during the operation of the first main operation phase and in the second main operation phase, the test result information corresponding to the generated IP test item is observed through the JTAG port.

[0082] Alternatively, the test parameters of the SCAN test item are configured through the JTAG port, and the first main operation phase corresponding to the SCAN test item is entered; during the operation of the first main operation phase, the test parameters of the IP test test item are configured through the JTAG port, and the second main operation phase corresponding to the IP test test item is entered; when the second main operation phase is completed earlier than the first main operation phase, during the operation of the second main operation phase and in the first main operation phase, the test result information corresponding to the generated IP test test item is observed through the JTAG port.

[0083] It should be noted that the above examples are only used to assist in understanding the present application and do not constitute a limitation on the chip testability design method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0084] In addition, please refer to Figure 7 , Figure 7 Schematic diagram of the device structure of the hardware operating environment involved in the chip testability design method in the embodiment of the present application.

[0085] The present application also provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the steps of the chip testability design method in the above-mentioned embodiment.

[0086] Reference below Figure 7 , which shows a structural schematic diagram of an electronic device suitable for implementing the embodiments of the present application. Figure 7 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0087] like Figure 7 As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory 1002 or programs loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the electronic device. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems may be connected to the input / output interface 1006: an input device 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 1003 including, for example, a magnetic tape or hard disk; and a communication device 1009. The communication device 1009 may allow the electronic device to communicate with other devices wirelessly or wired to exchange data. Although the figures show electronic devices with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0088] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are performed.

[0089] The electronic device provided in this application, which employs the chip testability design method of the above-described embodiment, can solve the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the chip testability design method provided in the above-described embodiment, and the other technical features of the electronic device are the same as those disclosed in the above-described embodiment method, which will not be described in detail here.

[0090] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0091] The above are merely specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the above claims.

[0092] In addition, the present application also provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, and the computer-readable program instructions are used to execute the steps of the chip testability design method in the above-mentioned embodiment.

[0093] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0094] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0095] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by an electronic device, the electronic device: obtains multiple test items of the chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for the first module group of the chip, and the second test item is a test item for the second module group of the chip, and the first module group is different from the second module group; configures the test parameters of the first test item through the JTAG port, and enters the first main body operation phase corresponding to the first test item, wherein the first main body operation phase is used to generate first test result information corresponding to the first test item; during the operation of the first main body operation phase, configures the test parameters of the second test item through the JTAG port, and enters the second main body operation phase corresponding to the second test item, wherein the second main body operation phase is used to generate second test result information corresponding to the second test item.

[0096] Alternatively, the electronic device: obtains multiple test items of the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, the third IP test item is an IP test item for the first module of the chip, the fourth IP test item is an IP test item for the second module of the chip, and the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; configures the test parameters of the third IP test item and the fourth IP test item in parallel through the signal broadcasting method of the JTAG port, and enters a third main body operation phase corresponding to the third IP test item and a fourth main body operation phase corresponding to the fourth IP test item; wherein the third main body operation phase is used to generate third test result information corresponding to the third IP test item, and the fourth main body operation phase is used to generate fourth test result information corresponding to the fourth IP test item.

[0097] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0098] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0099] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0100] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for executing the steps of the chip design for testability method described above. This solves the technical problem of shortening test time and reducing test costs while ensuring chip test quality and coverage. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the chip design for testability method provided in the above-described embodiments, and are not further elaborated here.

[0101] In addition, an embodiment of the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the chip testability design method in the above embodiment.

[0102] The computer program product provided in this application solves the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage. Compared with the prior art, the beneficial effects of the computer program product provided in the embodiments of this application are the same as those of the chip testability design method provided in the above embodiments, and will not be elaborated here.

[0103] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A chip testability design method, comprising: Acquire multiple test items of a chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, the first module group being different from the second module group; configuring test parameters of the first test item through a JTAG port, and entering a first main body operation phase corresponding to the first test item, wherein the first main body operation phase is used to generate first test result information corresponding to the first test item; During the operation of the first main body operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main body operation phase corresponding to the second test item is entered, wherein the second main body operation phase is used to generate second test result information corresponding to the second test item.

2. The chip testability design method according to claim 1, wherein: The first test item is a first IPtest test item, the second test item is a second IPtest test item, and the method further includes: In a case where the first main body operation phase is completed earlier than the second main body operation phase, the first test result information generated is observed through the JTAG port during the period between the completion of the first main body operation phase and the execution of the second main body operation phase; or When the second main body operation phase is completed earlier than the first main body operation phase, the second test result information generated is observed through the JTAG port during the period from the completion of the second main body operation phase to the execution of the first main body operation phase.

3. The chip testability design method according to claim 1, wherein: The first test item is a SCAN test item, the second test item is a second IP test item, and the method further includes: When the second main body operation phase is completed earlier than the first main body operation phase, the second test result information generated is observed through the JTAG port during the period from the completion of the second main body operation phase to the execution of the first main body operation phase.

4. The chip testability design method according to claim 1, wherein: The first test item is a first IPtest test item, the second test item is a SCAN test item, and the method further includes: When the first main body operation phase is completed earlier than the second main body operation phase, the first test result information generated is observed through the JTAG port during the period between the completion of the first main body operation phase and the second main body operation phase.

5. The chip testability design method according to any one of claims 1 to 4, characterized in that: Before entering the first main body operation phase corresponding to the first test item, the method further includes: Isolate other SCAN signals and / or other IP TEST signals through the JTAG network, whereby the isolation is used to prevent the other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to the test items; The other SCAN signals are SCAN signals that are not related to the test items, and the other IP TEST signals are IP TEST signals that are not related to the test items.

6. A chip testability design method comprising: Acquire multiple test items for a chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, the third IP test item is an IP test item for a first module of the chip, the fourth IP test item is an IP test item for a second module of the chip, and the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; By broadcasting signals from the JTAG port, the test parameters of the third IP test item and the test parameters of the fourth IP test item are configured in parallel, and a third main operation phase corresponding to the third IP test item and a fourth main operation phase corresponding to the fourth IP test item are entered; The third main body operation phase is used to generate third test result information corresponding to the third IP test test item, and the fourth main body operation phase is used to generate fourth test result information corresponding to the fourth IP test test item.

7. The chip testability design method according to claim 6, wherein: After entering the third main body operation phase corresponding to the third IP test test item and the fourth main body operation phase corresponding to the fourth IP test test item, the method further includes: After the third main body operation phase and the fourth main body operation phase are executed, the generated third test result information and the generated fourth test result information are observed through a JTAG port.

8. The chip testability design method according to claim 6 or 7, wherein: Before entering the third main body operation phase corresponding to the third IP test test item and the fourth main body operation phase corresponding to the fourth IP test test item, the method further includes: Isolate other SCAN signals and / or other IP TEST signals through the JTAG network, whereby the isolation is used to prevent the other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to the test items; The other SCAN signals are SCAN signals that are not related to the test items, and the other IP TEST signals are IP TEST signals that are not related to the test items.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the chip testability design method according to any one of claims 1 to 5, or 6 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the chip testability design method according to any one of claims 1 to 5, or 6 to 8.

11. A computer program product, characterized in that The computer program product includes a computer program, and when the computer program is executed by a processor, the chip testability design method according to any one of claims 1 to 5, or 6 to 8 is implemented.

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