Hierarchical circuit scan chain insertion method based on Bottom-up mode

Abstract

According to the Hierachical circuit scan chain insertion method based on the Bottom-up mode, a Bottom-up chain insertion scheme in a theoretical level is converted into a chain insertion method capable of being practically applied, efficient scan chain insertion is achieved in a bottom-up and parallel chain insertion mode, compared with a traditional Top-down method, the processing efficiency of a large-scale complex circuit is remarkably improved, and the processing efficiency of the large-scale complex circuit is improved. In addition, due to the unique internal scanning chain and external scanning chain construction strategy, the testability of the design is greatly improved, the debugging process is simplified, it is ensured that the test coverage rate is remarkably increased, the bottleneck of the traditional technology is successfully broken through, and the application prospect is wide. A solution with innovativeness and practicability is provided for the design of a super-large-scale integrated circuit, and the technical blank of a Bottom-up chain insertion scheme from theory to practice is filled.

Description

Technical Field

[0001] The present invention relates to the field of chip testability design, in particular to a scan chain insertion method for a large-scale integrated circuit, and more particularly to a hierarchical circuit scan chain insertion method based on a bottom-up mode. Background Art

[0002] As chip sizes continue to expand, Electronic Design Automation (EDA) tools have become essential technologies in the chip design field. As modern integrated circuit processes continue to advance in sophistication, chip manufacturing accuracy continues to improve, leading to a significant increase in the risk of manufacturing defects. To achieve efficient and accurate fault detection during production, the application of scan chain testing technology is becoming increasingly critical. Insertion chain technology, as the core component of scan chain testing, directly impacts the efficiency and accuracy of chip testing.

[0003] Existing insertion chaining technology primarily utilizes a top-down insertion chaining scheme, which works its way down through the circuit hierarchy, gradually inserting scan chains layer by layer by sequentially searching for the input and output interfaces of each scan unit. This scheme typically unfolds along the circuit hierarchy, ultimately completing all scan chain connections at the bottom layer. However, with the rapid growth in scale and complexity of modern chips, particularly large-scale integrated circuits (LSIs) and system-on-chips (SoCs), the chip hierarchy is becoming increasingly complex, and the time required for top-down insertion chaining is increasing exponentially. Furthermore, because top-down insertion chaining operates globally, problems at any level during debugging can impact the integrity of the entire scan chain, making it difficult to locate the issue and increasing debugging costs. Furthermore, because top-down insertion chaining relies on a global view of the entire design, the insertion progress of each module is closely tied to the overall circuit structure. Problems in a higher level or module can hinder insertion progress at lower levels.

[0004] In recent years, researchers in this field have proposed a bottom-up insertion chaining approach. This approach adopts a bottom-up approach, dividing the circuit into multiple independent blocks or modules. Two types of scan chains are then inserted into each block: a wrapper chain (external scan chain) and a core chain (internal scan chain). Compared to the top-down insertion chaining approach, the bottom-up insertion chaining approach offers the following advantages: The bottom-up approach divides large-scale circuits into multiple smaller modules. By inserting independent scan chains into each module, the complexity of layer-by-layer scanning is avoided. This modular design significantly improves processing speed and is particularly suitable for complex, large-scale circuits. Parallel operations shorten processing time: Because each module can be processed independently, the bottom-up approach supports parallel insertion chaining, enabling operations to be performed simultaneously on multiple modules. This parallel processing significantly reduces the overall insertion chaining time. In the bottom-up insertion chaining approach, scan chain insertion for each block is relatively independent, allowing debugging to quickly locate the module with the problem, reducing global dependencies. This localized debugging approach is more efficient and shortens debugging time. The bottom-up plug-in chaining solution is more scalable. Since each module can independently complete the plug-in chaining, as the chip scale increases, only more modules need to be added for processing, without having to redesign the entire plug-in chaining process. The bottom-up solution breaks down complex circuit designs into multiple independent components, reducing global dependencies. The bottom-up solution groups scan triggers within each clock domain into independent scan chains. Scan chains between different clock domains operate independently, avoiding direct cross-domain data transfer. Although the bottom-up plug-in chaining solution, with its technical advantages such as modular design and parallel processing, has theoretically demonstrated excellent adaptability to modern VLSI design, it is still in the conceptualization and theoretical demonstration stage and has not yet completed the transition from academic conception to engineering practice. There are no actual chip plug-in chaining cases based on this solution in the market, and practical challenges such as technical verification and tool development remain before industrial application.

[0005] In summary, the existing top-down plug-in chain scheme is not applicable to large-scale circuits with complex structures. Although the bottom-up plug-in chain scheme has shown excellent adaptability to modern ultra-large-scale integrated circuit design at the theoretical level due to its technical advantages such as modular design and parallel processing, it is currently still in the conceptual conception and theoretical demonstration stage. Therefore, there is an urgent need for an applicable and implementable scan chain insertion method for integrated circuits based on the bottom-up plug-in chain scheme.

[0006] It should be noted that this background information is provided solely to introduce relevant information of the present invention to facilitate understanding of the technical solution of the present invention. It does not necessarily constitute prior art. In the absence of evidence demonstrating that the relevant information was disclosed prior to the filing date of the present invention, the relevant information should not be considered prior art. Summary of the Invention

[0007] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide a hierarchical circuit scan chain insertion method based on the bottom-up mode.

[0008] The purpose of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, a method for inserting a scan chain of a hierarchical circuit based on a bottom-up mode is proposed, wherein the scan chain is used to test whether a target hierarchical circuit has a fault, and the target hierarchical circuit includes multiple circuit modules, each circuit module includes multiple scan units, and the method includes performing the following steps for each circuit module: step S1, obtaining scan chain construction information of the current circuit module, wherein the scan chain construction information includes the number of scan units inside the current circuit module, the number of internal scan chains to be inserted, a test input port, a test output port, a port to be inserted into a packaging unit, a signal selection module, a clock control signal port, and an SE control port; step S2, Insert encapsulation units before all ports of the encapsulation units and connect each encapsulation unit to the clock signal control port and the SE control port respectively, and connect all inserted encapsulation units in series, and connect them in series in the order of test input port, signal selection module, all encapsulation units after series connection, and test output port to form an external scan chain of the current circuit module; step S3, determine the number of scan units connected to each internal scan chain according to the number of scan units of the circuit module and the number of internal scan chains to be inserted, connect each scan unit to the clock signal control port and the SE control port respectively, connect the corresponding scan units on each internal scan chain in series, and connect them in series in the order of test input interface, scan unit after series connection, and test output interface to form an internal scan chain of the circuit module.

[0010] Preferably, in step S1, the scan chain construction information of the current circuit module is obtained in the following manner: by parsing a configuration file preset by the user to obtain the scan chain construction information of the current circuit module, wherein the configuration file preset by the user contains the scan chain construction information of all circuit modules in the target hierarchical circuit.

[0011] Preferably, in step S3, the number of scan units connected to each internal scan chain in the circuit module is calculated in the following manner: the number of scan units of the current circuit module is divided by the number of internal scan chains of the current circuit module to obtain the number of scan units on each internal scan chain in the current circuit module.

[0012] Preferably, in step S3, the corresponding scanning unit on each internal scan chain is obtained in the following manner: all scanning units in the current circuit module are traversed, and whenever the number of traversed scanning units reaches the number of scanning units connected on an internal scan chain, the traversed scanning units are used as scanning units connected in series on a scan chain.

[0013] Preferably, in step S3, when traversing the scanning units in the circuit module, the scanning units in the circuit module are traversed in the order from the highest circuit level to the lowest circuit level in the circuit module.

[0014] Preferably, in step S3, when the corresponding scanning units on each internal scan chain are connected in series, if two adjacent scanning units of the same internal scan chain are located at the same level in the circuit module, the output ports and input ports of the two adjacent scanning units are directly connected in series; if two adjacent scanning units of the same internal scan chain are located at different levels in the circuit module, the two adjacent scanning units are connected in series in a preset manner.

[0015] Preferably, the preset method is: the output port of the scanning unit in the front position and the input port of the scanning unit in the back position are penetrated to the common highest circuit level to which the two adjacent scanning units belong, and the output port of the scanning unit in the front position is connected to the input port of the scanning unit in the back position in the highest circuit level to connect the two adjacent scanning units in series.

[0016] According to a second aspect of the present invention, a testing method for a hierarchical circuit is proposed for performing a fault test on a target hierarchical circuit. The method comprises: inserting an internal scan chain and an external scan chain into the target hierarchical circuit using any of the methods described in the first aspect of the present invention to construct a test circuit for the target hierarchical circuit; and performing a scan chain test on the constructed test circuit to detect whether there is a fault in the hierarchical circuit.

[0017] According to a third aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. The computer program can be executed by a processor to implement the steps of the method according to any one of the first aspect or the second aspect of the present invention.

[0018] According to the fourth aspect of the present invention, an electronic device is proposed, comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in any one of the first aspect of the present invention or the second aspect of the present invention by executing the executable instructions.

[0019] Compared with the prior art, the advantages of the present invention are:

[0020] This paper implements the theoretical bottom-up insertion chain scheme and proposes a hierarchical circuit scan chain insertion method based on the bottom-up mode. Leveraging the modular design and parallel processing technical advantages of the bottom-up insertion chain scheme, this method successfully breaks through the technical bottleneck of the traditional top-down method and demonstrates excellent adaptability to modern ultra-large-scale integrated circuit design. At the same time, it fills the gap in the transition from theory to practice of the bottom-up insertion chain scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of a bottom-up mode-based hierarchical circuit scan chain insertion method according to an embodiment of the present invention;

[0023] Figure 2 Insert a schematic diagram of a packaging unit according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of an external scan chain according to an embodiment of the present invention;

[0025] Figure 4 Schematic diagram of an internal scan chain according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] As mentioned in the background technology section, the existing top-down plug-in chain solution is not suitable for large-scale circuits with complex structures. Although the bottom-up plug-in chain solution has demonstrated excellent adaptability to modern ultra-large-scale integrated circuit design at the theoretical level due to its technical advantages such as modular design and parallel processing, the current bottom-up plug-in chain solution is still in the conceptual conception and theoretical demonstration stage. Therefore, there is an urgent need for a practical integrated circuit plug-in chain method based on the bottom-up plug-in chain solution.

[0028] To overcome the technical bottlenecks of low efficiency and difficult debugging faced by traditional insertion chain solutions in very large-scale integrated circuits, this paper proposes a bottom-up model-based hierarchical circuit scan chain insertion scheme. This scheme realizes the engineering implementation of the bottom-up insertion chain theory. Based on the modular and layered design of hierarchical circuits, this scheme breaks down large-scale circuits into independently operable units. Using parallel processing technology, it simultaneously inserts external and internal scan chains into multiple modules, constructing a multi-level, three-dimensional scan test architecture. Compared with traditional insertion chain solutions, this scheme not only significantly shortens the overall insertion chain time, but also significantly improves the scan chain coverage of complex circuit structures.

[0029] Before specifically introducing the embodiments of the invention, a brief description of the bottom-up plug-in chain solution is given first:

[0030] In the bottom-up insertion chain approach, scan chains within a block (circuit module) are divided into two types: wrapper chain (external scan chain) and core chain (internal scan chain). Two modes are available: Internal Mode and External Mode. Internal Mode provides a view from the wrapper unit into the wrapper core, while External Mode provides a view between the wrapper core and the wrapper unit. During research, it was discovered that both top-down and bottom-up insertion chain approaches share some common characteristics when processing scan units. Both methods connect scan units end-to-end in a specific order to ensure scan chain integrity.

[0031] The bottom-up insertion chaining solution adopts a modular processing strategy, dividing the scan chains within each block into two categories: wrapper chain and core chain. Within this architecture, two insertion chaining modes are available: internal mode and external mode. The internal mode focuses on scan chain connections between wrapper units and core logic, handling the internal structural view from the wrapper unit into the core logic. The external mode handles the interface connection view between the package core and the wrapper units, ensuring the correct connection between the package hierarchy and the peripheral interface. These two modes are particularly well-suited for bottom-up design methodologies, flexibly addressing complex intra-module and inter-module connectivity requirements. By separating the wrapper chain and core chain, handling internal and external connectivity relationships separately, they effectively improve insertion chaining efficiency and controllability. Furthermore, the bottom-up mode, through modular design, significantly enhances the flexibility and debugging efficiency of the insertion chaining process in large-scale circuits, while ensuring circuit testability at different levels.

[0032] The present invention is described in detail below with reference to the accompanying drawings and embodiments. According to one embodiment of the present invention, a method for inserting a Hierarchical circuit scan chain based on a Bottom-up mode is proposed. Figure 1 In summary, the method of the present invention includes steps S1 to S3, wherein step S1 obtains scan chain construction information of the current circuit module, wherein the scan chain construction information includes the number of scan units in the current circuit module, the number of internal scan chains to be inserted, a test input port, a test output port, a port to be inserted with a package unit, a signal selection module, a clock control signal port, and an SE control port; step S2 inserts a package unit before all ports to be inserted with the package unit and connects each package unit to the clock signal control port and the SE control port, and connects all the inserted package units in series in the order of the test input port, the signal selection module, all the package units after series connection, and the test output port to form an external scan chain of the current circuit module; step S3 determines the number of scan units connected to each internal scan chain according to the number of scan units in the circuit module and the number of internal scan chains to be inserted, connects each scan unit to the clock signal control port and the SE control port, connects the corresponding scan units on each internal scan chain in series in the order of the test input interface, the scan unit after series connection, and the test output interface to form an internal scan chain of the circuit module.

[0033] In order to better understand the present invention, each step will be described in detail below in conjunction with specific embodiments.

[0034] According to one embodiment of the present invention, in step S1 of the present invention, the scan chain construction information of the current circuit module is parsed based on a configuration file preset by the user. The preset configuration file contains important parameter information about the scan chain, such as the number of scan chains of each circuit module, the input port set and output port set of the scan chain, etc. The parsed data will be stored in a corresponding data structure for use in the subsequent chain insertion process.

[0035] According to one embodiment of the present invention, in step S2 of the present invention, see Figure 2 The figure shows the structure after the packaging unit is inserted into the circuit module. The present invention builds a double isolation barrier of physical and logical by inserting the packaging unit in front of the input port and the output port, thereby effectively separating the complex logic inside the circuit module from the external signal environment. Secondly, the inserted external scan chain can directly build a global test path across the circuit module, which is more compatible with external test equipment, realizes multi-module parallel testing to improve efficiency, effectively isolates external interference, and enhances circuit test stability and system robustness.

[0036] According to one embodiment of the present invention, in the present invention, all ports that need to be inserted into the encapsulation unit are input ports and output ports in the circuit module except for control signals, wherein the control signals include but are not limited to clk control signals, set control signals, reset control signals, test mode control signals, and scan enable control signals.

[0037] In order to more clearly describe the insertion process of the external scan chain, the following is a detailed description with reference to the accompanying drawings. Figure 3 , the figure shows the structure after the circuit module is inserted into the external scan chain. First, the present invention connects all the inserted packaging units in series. When connecting the packaging units in series, the packaging units are connected in series according to the order of the ports connected to the packaging units in the circuit module, which can effectively reduce the length of the series path to reduce the complexity of the external scan chain. Secondly, the external scan chain of the current circuit module is formed in series in the order of the test input port, the signal selection module, all the packaging units after series connection, and the test output port. In the present invention, the signal selection module is used to select different test signals to input the external scan chain. Preferably, the present invention selects the MUX module as the signal selection module. It should be understood that the MUX module is a well-known technology for researchers in this field and will not be described in detail here. In addition, the signal selection module can be other modules that can achieve the same function as the MUX module.

[0038] According to one embodiment of the present invention, in step S3 of the present invention, the number of scan units connected to each internal scan chain in the circuit module is calculated as follows: the number of scan units in the current circuit module is divided by the number of internal scan chains in the current circuit module to obtain the number of scan units connected to each internal scan chain in the circuit module. For example, if the number of scan units in the circuit module is 1000 and the number of scan chains to be inserted into the circuit module is 10, then 100 scan units need to be connected in series in each scan chain.

[0039] According to one embodiment of the present invention, in step S3 of the present invention, the scan cells corresponding to each internal scan chain are obtained in the following manner: all scan cells in the current circuit module are traversed, and whenever the number of traversed scan cells reaches the number of scan cells connected to an internal scan chain, the traversed scan cells are used as the scan cells connected in series on the scan chain. For example, assuming that there are 1000 scan cells (Scan1, Scan2, Scan3, ... Scan1000) in the circuit module, and 100 scan cells are connected in series on each scan chain, the traversal starts from Scan1 and reaches 100 scan cells, that is, Scan100, and Scan1-Scan100 are used as the scan cells connected in series on the first internal scan chain. The traversal then starts from Scan101 and reaches 100 scan cells, that is, Scan200, and Scan101-Scan200 are used as the scan cells connected in series on the second internal scan chain. The same process is repeated to obtain the scan cells connected in series on each internal scan chain.

[0040] It should be noted that, in a hierarchical circuit, the internal scan chain connecting the scan units in different circuit layers in series may cause problems such as the scan chain being too long, signal delay, noise interference, and clock domain crossing, thereby affecting the testability and reliability of the circuit. Therefore, in order to avoid the internal scan chain connecting the scan units in different circuit layers in series, according to an embodiment of the present invention, in step S3 of the present invention, when traversing the scan units in the circuit module, the scan units in the circuit module are traversed in the order from the highest circuit level to the lowest circuit layer in the circuit module. Specifically, each circuit module may contain multiple circuit layers. When traversing scan cells, the system starts at the highest layer and, after traversing all scan cells in the current layer, moves on to the next layer. For example, assuming a circuit module consists of three circuit layers (first, second, and third), with the first layer containing scan cells Scan1-Scan100, the second layer containing scan cells Scan101-Scan200, and the third layer containing scan cells Scan201-Scan300, the scan cell traversal order is: (Scan1-Scan100) -> (Scan101-Scan200) -> (Scan201-Scan300). By systematically traversing scan cells according to the circuit hierarchy, the system ensures that the scan cells within each internal scan chain are highly concentrated at the same circuit level. This approach effectively avoids issues such as signal transmission delays and timing mismatches caused by cross-layer layouts, significantly improving the overall performance and test reliability of the scan chain.

[0041] According to one embodiment of the present invention, in step S3 of the present invention, when connecting the corresponding scan cells on each internal scan chain in series, if two adjacent scan cells in the same internal scan chain are located at the same level in the circuit module, the output ports and input ports of the two adjacent scan cells are directly connected in series. If two adjacent scan cells in the same internal scan chain are located at different levels in the circuit module, the path connecting the two adjacent scan cells is hierarchically flattened and penetrated in a predetermined manner to connect the two adjacent scan cells in series. Specifically, the output port of the preceding scan cell and the input port of the succeeding scan cell are penetrated to the common highest circuit level to which the two adjacent scan cells belong, and the output port of the preceding scan cell is connected to the input port of the succeeding scan cell in the highest circuit level to connect the two adjacent scan cells in series. For example, assuming that two scan cells Instance_i and Instance_j are located at different levels, their hierarchical relationships are I1 / I2 / Instance_i and J1 / J2 / J3 / Instance_j, respectively (" / " represents a level). When connected in series, first connect the virtual input port of I1 to the virtual input port of J1, and then penetrate each layer in turn until all levels of scanning units are connected.

[0042] To facilitate understanding of the internal scan chain insertion process of the present invention, a detailed description will be given below with reference to the accompanying drawings.

[0043] See attached Figure 4 The chain of blue lines in the figure represents the internal scan chain, where each scan unit is connected to the clock signal control port and the SE control port of the circuit module. The corresponding scan units in each internal scan chain are then connected in series, following the order of the test input interface, the series-connected scan units, and the test output interface, to form the internal scan chain of the circuit module. Scan units Scan_i and Scan_j, as well as Scan_x and Scan_y, are two pairs of adjacent scan units located on different circuit layers. Connecting these two pairs of scan units requires hierarchical flattening and penetration of the connection paths.

[0044] According to another embodiment of the present invention, a hierarchical circuit testing method is proposed for performing fault testing on a target hierarchical circuit. The method includes: using the above-mentioned bottom-up mode hierarchical circuit scan chain insertion method to insert an internal scan chain and an external scan chain into the target hierarchical circuit to construct a hierarchical circuit test circuit; and performing a scan chain test on the constructed hierarchical circuit test circuit to detect whether there is a fault in the hierarchical circuit.

[0045] This paper implements the theoretical bottom-up insertion chain approach and proposes a bottom-up scan chain insertion method for hierarchical circuits. This method achieves efficient bottom-up, layer-by-layer scan chain insertion, significantly improving the processing efficiency of large-scale, complex circuits. It reduces global dependencies, and its modular packaging unit design enhances flexibility and scalability, making it particularly suitable for modern large-scale hierarchical circuits. It improves the testability and debugging convenience of the design while ensuring test coverage. This method successfully overcomes the technical bottlenecks of traditional top-down methods, demonstrating excellent adaptability to modern ultra-large-scale integrated circuit design. It also fills the gap in the theoretical and practical application of bottom-up insertion chain solutions.

[0046] It should be noted that although the above describes the various steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0047] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0048] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove having instructions stored thereon, and any suitable combination thereof.

[0049] While various embodiments of the present invention have been described above, the above descriptions are intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for inserting a scan chain into a hierarchical circuit based on a bottom-up mode, wherein the scan chain is used to test whether a target hierarchical circuit has a fault. The target hierarchical circuit includes multiple circuit modules, each of which includes multiple scan units. The method comprises performing the following steps for each circuit module: Step S1: Obtain scan chain construction information of the current circuit module, wherein the scan chain construction information includes the number of scan units inside the current circuit module, the number of internal scan chains to be inserted, test input ports, test output ports, ports to be inserted into the encapsulation unit, signal selection modules, clock control signal ports, and SE control ports; Step S2: inserting a package unit before all ports where the package unit needs to be inserted and connecting each package unit to the clock signal control port and the SE control port, respectively, and connecting all the inserted package units in series in the order of the test input port, the signal selection module, all the package units after the series connection, and the test output port to form an external scan chain of the current circuit module; Step S3: Determine the number of scan units connected to each internal scan chain according to the number of scan units in the circuit module and the number of internal scan chains to be inserted, connect each scan unit to the clock signal control port and the SE control port respectively, connect the corresponding scan units on each internal scan chain in series, and connect them in series in the order of test input interface, series-connected scan units, and test output interface to form the internal scan chain of the circuit module.

2. The method according to claim 1, characterized in that In step S1, the scan chain construction information of the current circuit module is obtained in the following manner: The scan chain construction information of the current circuit module is obtained by parsing the configuration file preset by the user, wherein the configuration file preset by the user includes the scan chain construction information of all circuit modules in the target hierarchical circuit.

3. The method according to claim 1, characterized in that In step S3, the number of scan units connected to each internal scan chain in the circuit module is calculated as follows: The number of scan units in the current circuit module is divided by the number of internal scan chains in the current circuit module to obtain the number of scan units in each internal scan chain in the current circuit module.

4. The method according to claim 3, characterized in that In step S3, the corresponding scanning unit on each internal scan chain is obtained in the following manner: All scan cells in the current circuit module are traversed. Whenever the number of traversed scan cells reaches the number of scan cells connected on an internal scan chain, the traversed scan cells are used as scan cells connected in series on a scan chain.

5. The method according to claim 4, characterized in that In step S3, when traversing the scanning units in the circuit module, the scanning units in the circuit module are traversed in the order from the highest circuit level to the lowest circuit level in the circuit module.

6. The method according to claim 1, characterized in that In step S3, when the corresponding scanning units on each internal scan chain are connected in series, if two adjacent scanning units of the same internal scan chain are located at the same level in the circuit module, the output ports and input ports of the two adjacent scanning units are directly connected in series; if two adjacent scanning units of the same internal scan chain are located at different levels in the circuit module, the two adjacent scanning units are connected in series in a preset manner.

7. The method according to claim 6, characterized in that The preset method is: The output port of the scanning unit in the front position and the input port of the scanning unit in the back position are penetrated to the common highest circuit level to which the two adjacent scanning units belong, and the output port of the scanning unit in the front position and the input port of the scanning unit in the back position are connected in the said highest circuit level to connect the two adjacent scanning units in series.

8. A testing method for a hierarchical circuit, for performing a fault test on a target hierarchical circuit, characterized in that: The method comprises: Inserting an internal scan chain and an external scan chain into a target hierarchical circuit using the method according to any one of claims 1 to 7 to construct a test circuit for the target hierarchical circuit; Perform scan chain testing on the constructed test circuit to detect whether there are faults in the hierarchical circuit.

9. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: one or more processors; as well as a memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1 to 8 by executing the executable instructions.

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