Exception handling method and device, processor and medium
By binding the processor core with the watchdog function and using inter-core interrupts for exception handling, the problem of watchdog function failure when the processor core soft locks abnormally is solved, and the reliability and robustness of processor core exception detection are achieved.
Patent Information
- Application Number
- CN202510795669.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2025-09-16
AI Technical Summary
When a core soft lock exception occurs in a processor core, a watchdog function running on the processor core becomes invalid, resulting in the inability to identify the invalid watchdog function and the processor core that cannot be detected.
By binding the processor core with the watchdog function, the watchdog function of the first processor core is used to detect whether the second processor core is abnormal, and an inter-core interrupt is sent when an abnormality is detected, so that the second processor core can perform abnormal processing on its own, thereby realizing polling and mutual inspection of multiple processor cores.
This solves the problem of being unable to determine the failed watchdog function when a core soft lock exception occurs in the processor core, and improves the reliability and robustness of processor core exception detection.
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Figure CN120653479A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to an exception handling method, device, processor, and medium. Background Art
[0002] As the world advances, processors are increasingly multi-core, with each core independently operating in either user mode or kernel context. When a core experiences a kernel soft lockup, effective detection methods are needed to locate and resolve the issue.
[0003] To solve this problem, a software watchdog is currently used to detect and recover from system failures. Specifically, a watchdog function is created for each processor core, and the watchdog function is run to detect whether the time from the last time the corresponding processor core called the watchdog function to the current time exceeds a predetermined time; if it exceeds the predetermined time, a kernel soft lock exception occurs in the corresponding processor core, and the error of the corresponding processor core is reported.
[0004] The watchdog function corresponding to a processor core can be assigned to any processor core within the processor. When a core softlock exception occurs in a processor core, the watchdog function assigned to that core becomes inoperable, rendering the processor core corresponding to the inoperable watchdog function undetectable. However, the allocation of watchdog functions is uncertain, meaning the watchdog function running on each processor core is uncertain. Consequently, after a core softlock exception occurs, it's impossible to determine which watchdog function is running on that core. Consequently, it's impossible to determine which watchdog function is inoperable, and therefore, which processor core cannot be detected. Summary of the Invention
[0005] The purpose of the embodiments of the present application is to provide an exception handling method, apparatus, processor, and medium to address the problem that a core softlock exception occurs in a processor core, causing the watchdog function running on the processor core to fail, resulting in the inability to identify the failed watchdog function and the undetected processor cores. The specific technical solution is as follows:
[0006] In a first aspect, an embodiment of the present application provides an exception handling method, which is applied to a first processor core included in a processor, wherein the first processor core is bound to a first watchdog function, and the processor further includes a second processor core. The method includes:
[0007] Running the first watchdog function to detect whether the second processor core is abnormal;
[0008] When an exception is detected in the second processor core, a first inter-core interrupt is sent to the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
[0009] In some embodiments, the processor further includes a third processor core, the second processor core is bound to a second watchdog function, and the second watchdog function is used to detect whether the third processor core is abnormal; when the second processor core is detected to be abnormal, the method further includes:
[0010] Running the first watchdog function to detect whether the third processor core is abnormal;
[0011] When an exception is detected in the third processor core, a second inter-core interrupt is sent to the third processor core, so that the third processor core performs exception processing according to the second inter-core interrupt.
[0012] In some embodiments, executing the first watchdog function to detect whether the second processor core is abnormal includes:
[0013] detecting whether the second processor core is abnormal by using a first detection variable included in the first watchdog function, the first detection variable indicating that the first watchdog function corresponds to the second processor core;
[0014] The running of the first watchdog function to detect whether the third processor core is abnormal includes:
[0015] updating, in a polling mutual check order, the first detection variable included in the first watchdog function to a second detection variable, where the second detection variable indicates that the first watchdog function corresponds to the third processor core;
[0016] The second detection variable included in the first watchdog function is used to detect whether the third processor core is abnormal.
[0017] In some embodiments, the method further comprises:
[0018] When the second processor core returns to normal, the second detection variable included in the first watchdog function is updated to the first detection variable in a polling mutual detection order.
[0019] In some embodiments, the method further comprises:
[0020] Receive the third inter-core interrupt;
[0021] generating a non-maskable interrupt according to the third inter-core interrupt;
[0022] Exception handling is performed in the non-maskable interrupt.
[0023] In a second aspect, an embodiment of the present application provides an exception handling device, which is applied to a first processor core included in a processor, wherein the first processor core is bound to a first watchdog function, and the processor further includes a second processor core. The device includes:
[0024] a detection module, configured to run the first watchdog function to detect whether the second processor core is abnormal;
[0025] The sending module is configured to send a first inter-core interrupt to the second processor core when an exception is detected in the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
[0026] In some embodiments, the processor also includes a third processor core, the second processor core is bound to a second watchdog function, and the second watchdog function is used to detect whether the third processor core is abnormal; the detection module is also used to run the first watchdog function when the second processor core is detected to be abnormal, so as to detect whether the third processor core is abnormal; the sending module is also used to send a second inter-core interrupt to the third processor core when the third processor core is detected to be abnormal, so that the third processor core performs exception processing according to the second inter-core interrupt.
[0027] In some embodiments, the detection module is specifically configured to detect whether the second processor core is abnormal using a first detection variable included in the first watchdog function, the first detection variable indicating that the first watchdog function corresponds to the second processor core;
[0028] The detection module is specifically used to update the first detection variable included in the first watchdog function to a second detection variable in accordance with the polling mutual inspection order, wherein the second detection variable indicates that the first watchdog function corresponds to the third processor core; and use the second detection variable included in the first watchdog function to detect whether the third processor core is abnormal.
[0029] In some embodiments, the detection module is further configured to update the second detection variable included in the first watchdog function to the first detection variable in a polling mutual check order when the second processor core returns to normal.
[0030] In some embodiments, the apparatus further includes: a receiving module configured to receive a third inter-core interrupt; generate a non-maskable interrupt according to the third inter-core interrupt; and perform exception processing in the non-maskable interrupt.
[0031] In a third aspect, an embodiment of the present application provides a processor comprising a plurality of processor cores, each processor core being bound to a watchdog function; each processor core determines the corresponding processor core in accordance with a polling mutual check order; the bound watchdog function is run to detect the corresponding processor core; and when an abnormality is detected in the corresponding processor core, an inter-core interrupt is sent to the corresponding processor core so that the corresponding processor core performs exception handling according to the inter-core interrupt.
[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor core included in a processor, any one of the methods provided in the first aspect is implemented.
[0033] Beneficial effects of the embodiments of the present application:
[0034] In the technical solution provided by the embodiment of the present application, the processor core is bound to the watchdog function, that is, each watchdog function runs on a specific processor core. The first processor core runs the bound first watchdog function to perform an exception detection on the second processor core. After detecting the exception of the second processor core, an inter-core interrupt is sent to the second processor core, and the second processor core performs the exception processing on its own according to the first inter-core interrupt. Since each processor core is bound to the watchdog function, after any processor core is abnormal, it can be determined that the watchdog function bound to the abnormal processor core is invalid, and then it can be determined that the processor core corresponding to the invalid watchdog function cannot be detected, which solves the problem that the kernel soft lock exception occurs in the processor core, the watchdog function running on the processor core is invalid, resulting in the invalid watchdog function and the part of the processor core that cannot be detected being unable to be determined.
[0035] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.
[0037] Figure 1 A schematic diagram of a software watchdog;
[0038] Figure 2 A schematic diagram of a first flow chart of the exception handling method provided in an embodiment of the present application;
[0039] Figure 3A second flow chart of the exception handling method provided in an embodiment of the present application;
[0040] Figure 4 A schematic diagram of a software watchdog provided in an embodiment of the present application;
[0041] Figure 5 A schematic diagram of a polling mutual check among multiple processor cores provided in an embodiment of the present application;
[0042] Figure 6 A schematic diagram of the structure of the exception handling device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0043] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.
[0044] To facilitate understanding, the terms appearing in the embodiments of this application are explained below.
[0045] Linux operating system: An open-source, Unix-like operating system that runs on a processor (such as a central processing unit (CPU)). It is known for its stability, high security, and flexibility and is widely used on various platforms, including servers, desktop computers, embedded systems, and mobile devices.
[0046] Soft lockup: A kernel soft lockup exception in a processor core. This exception occurs when a kernel-mode program running on the processor core has hard or soft interrupts disabled for an extended period of time. Common scenarios include: 1) the processor core disables soft or hard interrupts for an extended period of time while running the kernel portion of a user-mode process or kernel thread; 2) the processor core runs a soft interrupt handler for an extended period of time while running a soft interrupt; 3) the processor core runs a hard interrupt handler for an extended period of time while running a hard interrupt.
[0047] High-Resolution Timer (Hrtimer): A high-resolution timer mechanism provided by the Linux operating system kernel. Compared with traditional timers (such as timer_list), it provides nanosecond accuracy.
[0048] Watchdog: Also known as the kernel watchdog, a hardware or software timer, is a built-in kernel monitoring program in the Linux operating system used to detect and recover from system failures. Hardware watchdogs are implemented using a physical hardware timer and require regular feeding; otherwise, a system reset will be triggered. Software watchdogs are implemented purely in software and monitor system status through kernel threads.
[0049] Per-CPU (PERCPU) variables: An important data sharing mechanism in the Linux kernel that maintains an independent copy of variables for each CPU core, avoiding lock contention problems in a multi-core environment.
[0050] Process: In Linux, a process is a fundamental concept in the operating system, representing a running program instance. Each process has its own independent address space, resources (such as file descriptors and memory), and execution state. A process is the fundamental unit of resource allocation and scheduling in the operating system.
[0051] Thread: In Linux, a thread is an execution unit within a process and the basic unit of scheduling for the operating system. Threads are similar to processes, but they share the process's address space and resources (such as memory and file descriptors), making communication and data sharing between threads more efficient. A process can consist of one or more threads.
[0052] As the world advances, processors are increasingly multi-core. Each processor core independently operates in either user mode or kernel context. Kernel context includes the kernel portion of a process, kernel threads, soft interrupts, and interrupts. When a kernel softlock exception occurs on a processor core, effective detection methods are needed to locate and resolve the issue.
[0053] To solve this problem, a software watchdog is currently used to detect and recover from system failures. Specifically, a watchdog function is created for each processor core, including a high-resolution timer and a watchdog thread; each processor core runs the watchdog function, that is, the high-resolution timer is used to periodically wake up the watchdog thread, and the watchdog thread is woken up to detect whether the time from the last time the corresponding processor core called the watchdog function to the current time exceeds the preset time; if it exceeds the preset time, the corresponding processor core will have a kernel soft lock exception, and then the error of the corresponding processor core will be reported.
[0054] like Figure 1The software watchdog shown in the figure includes N processor cores (e.g., processor core 1 through processor core N). Each processor core creates and starts a corresponding high-resolution timer and watchdog thread. For example, processor core 1 creates high-resolution timer 1 and watchdog thread 1; processor core 2 creates high-resolution timer 2 and watchdog thread 2. The N processor cores create N high-resolution timers (e.g., high-resolution timer 1 through high-resolution timer N) and N watchdog threads (e.g., watchdog thread 1 through watchdog thread N).
[0055] Each processor core can call the watchdog function (such as touch_softlockup_watchdog) in the following situations: when the scheduler switches processes, when soft interrupts and hard interrupts enter / exit, when soft interrupts and hard interrupts are enabled, and in other display scenarios (such as read-copy-update (RCU) read-side critical section, console output, and manual watchdog feeding before long operations), etc., and write the PERCPU variable data of this core, that is, record the time when this core last called the watchdog function (i.e., watchdog feeding time).
[0056] After the watchdog thread corresponding to each processor core is started, it goes into sleep mode. A high-resolution timer periodically triggers and wakes up the watchdog thread. The high-resolution timer's timeout can be set, such as 10 seconds. After waking up, the watchdog thread checks the system status and the corresponding processor core's watchdog timer. If a timeout is detected (i.e., the barking occurs, and the duration from the watchdog timer to the current moment exceeds the preset duration), the watchdog thread reports an error or kernel panic to the core.
[0057] The watchdog function (i.e., high-resolution timer and watchdog thread) corresponding to a processor core can be assigned to any processor core in the processor. If a core softlock exception occurs in a processor core, the high-resolution timer and watchdog thread assigned to that processor core will become inoperative, causing the watchdog function assigned to that processor core to become inoperative, making the processor core corresponding to the inoperative watchdog function undetectable.
[0058] In order to solve the above problem, the embodiment of the present application provides an exception handling method, which is applied to a first processor core included in a processor, the first processor core is bound to a first watchdog function, and the processor also includes a second processor core, see Figure 2 , Figure 2 This is a first flow chart of an exception handling method provided in an embodiment of the present application, and the exception handling method includes the following steps.
[0059] Step S21 : running the first watchdog function to detect whether the second processor core is abnormal.
[0060] Step S22 : When an exception is detected in the second processor core, a first inter-core interrupt is sent to the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
[0061] In the technical solution provided by the embodiment of the present application, the processor core is bound to the watchdog function, that is, each watchdog function runs on a specific processor core. The first processor core runs the bound first watchdog function to perform an exception detection on the second processor core. After detecting the exception of the second processor core, an inter-core interrupt is sent to the second processor core, and the second processor core performs the exception processing on its own according to the first inter-core interrupt. Since each processor core is bound to the watchdog function, after any processor core is abnormal, it can be determined that the watchdog function bound to the abnormal processor core is invalid, and then it can be determined that the processor core corresponding to the invalid watchdog function cannot be detected, which solves the problem that the kernel soft lock exception occurs in the processor core, the watchdog function running on the processor core is invalid, resulting in the invalid watchdog function and the part of the processor core that cannot be detected being unable to be determined.
[0062] In the embodiment of the present application, the processor is a multi-core processor including multiple processor cores, the number of which is not limited herein. The processor runs a Linux operating system, and each processor core is associated with a watchdog function, each of which may include a high-resolution timer and a watchdog thread.
[0063] The watchdog function bound to each processor core runs on the processor core to detect whether the corresponding processor core is abnormal. The processor core corresponding to each processor core can be determined according to a pre-set polling mutual inspection order. For example, the processor may include three processor cores, namely processor core 1 to processor core 3, which are respectively bound to watchdog functions 1 to watchdog functions 3; the polling mutual inspection order can be processor core 1-processor core 2-processor core 3-processor core 1, that is, the watchdog function 1 running on processor core 1 is used to detect whether processor core 2 is abnormal, the watchdog function 1 and processor core 1 correspond to processor core 2, the watchdog function 1 running on processor core 2 is used to detect whether processor core 3 is abnormal, the watchdog function 2 and processor core 2 correspond to processor core 3, the watchdog function 3 running on processor core 2 is used to detect whether processor core 1 is abnormal, and the watchdog function 3 and processor core 3 correspond to processor core 1. Multiple processor cores realize polling mutual inspection of these multiple processor cores through the bound watchdog function.
[0064] In the embodiment of the present application, the first processor core can be any processor core among the multiple processor cores. For ease of description, the following description will take the first processor core as an example to illustrate the exception handling method provided in the embodiment of the present application, which does not serve as a limitation. The watchdog function bound to the first processor core is the first watchdog function. The high-resolution timer and watchdog thread included in the first watchdog function are respectively referred to as the first high-resolution timer and the first watchdog thread. The second processor core is the processor core corresponding to the first processor core among the multiple processor cores, and the first watchdog function is used to detect whether the second processor core is abnormal.
[0065] In step S21, the first processor core runs the first watchdog function. That is, the first processor core can periodically trigger the first high-resolution timer according to the timeout period of the first high-resolution timer, wake up the first watchdog thread from the sleep state, and perform abnormal detection on the second processor core through the first watchdog thread. The timeout period can be 10 seconds, 20 seconds, etc., and there is no limit on this.
[0066] In the embodiment of the present application, the first processor core can obtain the PERCPU variable data of the second processor core through the first watchdog thread, obtain the time when the second processor core last called the dog feeding function (i.e., the dog feeding time), and determine whether the time from the dog feeding time of the second processor core to the current time exceeds a predetermined time (i.e., whether the dog is barking), thereby realizing abnormality detection of the second processor core. The predetermined time can be 1 minute, 2 minutes, etc., and is not limited to this.
[0067] If the duration of the dog feeding time of the second processor core to the current moment does not exceed the preset duration, it means that the second processor core is not abnormal, then the first watchdog thread re-enters the sleep state, the first high-resolution timer is cleared, and the timing is restarted until the timing reaches the timeout time, and the first high-resolution timer is triggered again to wake up the first watchdog thread.
[0068] If the duration from the dog feeding time of the second processor core to the current moment exceeds the predetermined duration, it indicates that the second processor core is abnormal, and step S22 is executed.
[0069] In an embodiment of the present application, before the first processor core detects the watchdog time of the second processor core through the first watchdog thread, it can first detect whether the processor system status is normal through the first watchdog thread. If it is determined that the processor system status is normal, the first processor core then obtains the PERCPU variable data of the second processor core and determines whether the duration from the watchdog time of the second processor core to the current moment exceeds a predetermined duration; otherwise, the first processor core determines that the processor system status is abnormal and restarts the processor system.
[0070] In step S22, the first inter-core interrupt is an inter-core interrupt sent by the first processor core to the second processor core after the first processor core determines that the second processor core is abnormal. The first inter-core interrupt may be an inter-processor interrupt (IPI), which is used to implement communication and coordination between multiple cores and is a non-maskable interrupt.
[0071] After the first processor core sends the first inter-core interrupt to the second processor core, the second processor core receives the first inter-core interrupt, collects current exception information of the second processor core based on the non-maskable first inter-core interrupt, and performs exception processing according to the exception information.
[0072] In an embodiment of the present application, after receiving a first inter-core interrupt, the second processor core can generate a non-maskable interrupt based on the first inter-core interrupt. This non-maskable interrupt cannot be disabled by the processor's interrupt mask flag and is a high-priority interrupt. The second processor core can collect exception information from the generated non-maskable interrupt and, based on a pre-set correspondence between the exception information and the processing method, determine the processing method corresponding to the collected exception information. Exception handling is then performed on the second processor core according to the determined processing method, thereby conserving processing resources of the first processor core and reducing the load.
[0073] In this embodiment of the present application, the handling method may include generating a panic, restarting the current core, or restarting the system. If the handling method determined is generating a panic or restarting the system, the processor system may be restarted; if the handling method determined is restarting the current core, the second processor core may be restarted. The specific handling method corresponding to each exception information can be set according to actual circumstances and is not limited to this.
[0074] In an embodiment of the present application, each processor core included in the processor can determine the corresponding processor core in a polling mutual inspection order and run the bound watchdog function to detect the corresponding processor core; when each processor core detects that the corresponding processor core is abnormal, it can send an inter-core interrupt to the corresponding processor core, and the corresponding processor core performs exception processing according to the inter-core interrupt.
[0075] In some embodiments, the processor may further include other processor cores, such as a third processor core. Before the second processor core becomes abnormal, according to the polling mutual inspection order, the processor core corresponding to the second processor core is the third processor core, and the watchdog function bound to the second processor core (i.e., the second watchdog function) is used to detect whether the third processor core is abnormal. In this case, see Figure 3 , Figure 3The second flowchart of the exception handling method provided in the embodiment of the present application may include the following steps: the second processor core is a processor core corresponding to the first processor core among the multiple processor cores, and the first watchdog function is used to detect whether the second processor core is abnormal.
[0076] Step S31: Run the first watchdog function to detect whether the second processor core is abnormal, which is the same as the above step S21.
[0077] Step S32 , when an exception is detected in the second processor core, sends a first inter-core interrupt to the second processor core so that the second processor core performs exception processing according to the first inter-core interrupt. This is the same as the above step S22 .
[0078] Step S33: running the first watchdog function to detect whether the third processor core is abnormal.
[0079] Step S34 : When an exception is detected in the third processor core, a second inter-core interrupt is sent to the third processor core, so that the third processor core performs exception processing according to the second inter-core interrupt.
[0080] In the technical solution provided by the embodiments of the present application, after the second processor core experiences an abnormality, the second watchdog function becomes ineffective, and the third processor core corresponding to the second watchdog function cannot be detected. The first processor core can use the first watchdog function to detect abnormalities in the third processor core. This allows the implementation of the following: if any processor core experiences an abnormality and the watchdog function bound to that processor core fails, other processor cores can run their own bound watchdog functions to detect the undetectable processor core, thus resolving the problem of being unable to detect undetectable processor cores.
[0081] In the embodiment of the present application, after the first processor core detects that the second processor core is abnormal, the first processor core may first execute step S32 to send a first inter-core interrupt to the second processor core, and then execute step S33.
[0082] In step S33, the first processor core has determined that the second processor core is abnormal. The first processor core can update the processor core being tested by the first watchdog function to the third processor core corresponding to the second processor core. The first processor core can also periodically trigger the first high-resolution timer based on the timeout period of the first high-resolution timer to wake the first watchdog thread from a sleep state, and perform abnormality detection on the third processor core through the first watchdog thread. This is similar to the process of performing abnormality detection on the second processor core in step S21. For details, please refer to the relevant description of step S21.
[0083] In the above step S34, the second inter-core interrupt is an inter-core interrupt sent by the first processor core to the third processor core after determining that the third processor core is abnormal. The second inter-core interrupt and the first inter-core interrupt may be of the same type of interrupt, ie, IPI.
[0084] After the first processor core sends the second inter-core interrupt to the third processor core, the third processor core receives the second inter-core interrupt, collects the third processor core's current exception information based on the non-maskable second inter-core interrupt, and performs exception handling based on the exception information. This is similar to the exception handling process for the second processor core in step S22 above. For details, see the relevant description of step S22 above.
[0085] In some embodiments, the watchdog function may include a detection variable, and the detection variable indicates the processor core corresponding to the watchdog function. The detection variable can be represented by the identification of the processor core, etc., and this is not limited. The detection variable included in the first watchdog function is the first detection variable, and the first detection variable indicates that the first watchdog function corresponds to the second processor core, that is, the processor core corresponding to the first processor core is the second processor core. The above step S31 (or step S21) can be implemented by the following steps: using the first detection variable included in the first watchdog function to detect whether the second processor core is abnormal. The first processor core can run the first watchdog function, determine that the processor core indicated by the first detection variable included in the first watchdog function is the second processor core, and perform abnormality detection on the second processor core. For details, please refer to the relevant description of the above step S21.
[0086] In an embodiment of the present application, after the first processor core detects that the second processor core is abnormal, the first processor core can detect whether the third processor core is abnormal through the following steps: according to the polling mutual inspection order, the first detection variable included in the first watchdog function is updated to the second detection variable, and the second detection variable included in the first watchdog function is used to detect whether the third processor core is abnormal.
[0087] In an embodiment of the present application, the second detection variable indicates that the first watchdog function corresponds to the third processor core, that is, indicates that the processor core corresponding to the first processor core is the third processor core. After detecting that the second processor core is abnormal, the first processor core can determine that the processor core to be detected is the third processor core in accordance with the polling mutual inspection order, and update the detection variable included in the first watchdog function from the first detection variable to the second detection variable. The first processor core can run the first watchdog function and determine that the processor core indicated by the second detection variable included in the first watchdog function is the third processor core, and perform an abnormality detection on the second processor core. For details, please refer to the relevant description of the above step S21.
[0088] For example, if processor core 1 detects that processor core 2 is abnormal, processor core 1 sends an inter-core interrupt to processor core 2, and according to the polling mutual inspection order of processor core 1-processor core 2-processor core 3-processor core 1, determines that the processor core to be detected is processor core 3, and updates the detection variable included in watchdog function 1 to the identifier corresponding to processor core 3. At this time, processor core 1 runs watchdog function 1 to detect processor core 3, processor core 3 runs watchdog function 3 to detect processor core 1, and processor core 2 is abnormal and does not participate in the polling mutual inspection. By updating the detection variable, the first processor core can continue to detect the third processor core through the first watchdog function after the second processor core is abnormal, thereby realizing the polling mutual inspection of multiple processor cores.
[0089] In some embodiments, when the second processor core returns to normal, the above exception handling method may further include the following step: updating the second detection variable included in the first watchdog function to the first detection variable according to a polling mutual check sequence.
[0090] In an embodiment of the present application, when performing exception handling on the second processor core, if the processing method of restarting the current core is adopted, the second processor core can rejoin the polling mutual inspection of multiple processor cores after restarting and returning to normal. The first processor core can determine that the processor core to be detected is the second processor core according to the polling mutual inspection order, and update the detection variable included in the first watchdog function from the second detection variable to the first detection variable. After that, the first watchdog function is run to continue to perform exception detection on the second processor core.
[0091] In an embodiment of the present application, the detection variable may be included in the watchdog thread. Before detecting an abnormality in the second processor core, the first processor core may wake up the first watchdog thread. The first watchdog thread may obtain the PERCPU variable data of the second processor core based on the second processor core indicated by the first detection variable included in the first watchdog thread, obtain the watchdog time of the second processor core, and determine whether the duration from the watchdog time of the second processor core to the current moment exceeds a predetermined duration, thereby detecting an abnormality in the second processor core.
[0092] After detecting that the second processor core is abnormal, the first processor core can also determine that the processor core to be detected is the third processor core in accordance with the polling mutual inspection order, and update the detection variable included in the first watchdog thread from the first detection variable to the second detection variable. After waking up the first watchdog thread, the first processor core can obtain the PERCPU variable data of the third processor core through the first watchdog thread based on the third processor core indicated by the second detection variable included in the first watchdog thread, obtain the dog feeding time of the third processor core, and determine whether the duration from the dog feeding time of the third processor core to the current moment exceeds the predetermined duration, so as to perform abnormality detection on the third processor core. Similarly, the first processor core can also adopt a similar method to update the detection variable included in the first watchdog thread from the second detection variable to the first detection variable, and perform abnormality detection on the second processor core through the first watchdog thread. For details, please refer to the relevant description of the above step S22.
[0093] In some embodiments, the watchdog function running on the fourth processor core can detect the first processor core. The fourth processor core can be the second processor core or the third processor core, or it can be other processor cores included in the processor, without limitation. When the fourth processor core detects that the first processor core is abnormal, the first processor core can also receive an inter-core interrupt (such as a third inter-core interrupt) sent by the fourth processor core, and generate a non-maskable interrupt based on the third inter-core interrupt, and perform exception handling in the non-maskable interrupt. Similar to the process of the second processor core receiving the first inter-core interrupt for exception handling, please refer to the relevant description of the above step S22 for details.
[0094] The following combination Figure 4 and Figure 5 The exception handling method provided in the embodiment of the present application is described in detail.
[0095] like Figure 4 As shown, the processor includes multiple processor cores (i.e., processor cores 1 through N). Each processor core is bound to a high-resolution timer and a watchdog thread. For example, processor core 1 is bound to high-resolution timer 1 and watchdog thread 1, processor core 2 is bound to high-resolution timer 2 and watchdog thread 2, and processor core N is bound to high-resolution timer N and watchdog thread N. The value of N is not limited. Each processor core can call the watchdog feeding function and write data to the PERCPU variable of this core to record the watchdog feeding time of this core.
[0096] For each processor core, the watchdog thread bound to that processor core starts and goes into sleep mode. The high-resolution timer bound to that processor core triggers periodically according to the set timeout period (e.g., 10 seconds) to wake up the bound watchdog thread. For example, high-resolution timer 1 wakes up watchdog thread 1 every 10 seconds, and high-resolution timer 2 wakes up watchdog thread 2 every 10 seconds.
[0097] For each processor core, after the watchdog thread bound to the processor core is awakened, it detects the system status and, through polling and mutual inspection, detects whether the time from the watchdog feeding time of other cores to the current moment exceeds the preset time (i.e., detects whether other cores are barking). Figure 5 As shown, watchdog thread 1 running on processor core 1 detects whether processor core 2 is barking, watchdog thread 2 running on processor core 2 detects whether processor core 3 is barking, and watchdog thread N running on processor core N detects whether processor core 1 is barking, thereby realizing polling mutual inspection.
[0098] If the watchdog thread running on any processor core (called a patrol core) detects that another processor core (called a barking core) is barking, it determines that the processor core is abnormal and sends an IPI (inter-core interrupt) to the corresponding barking core. After receiving the IPI, the barking core generates an NMI, which collects and reports information about the softlock anomaly and determines the response: panic, restart the core, or restart the system.
[0099] At the same time, the processor cores adjust the polling mutual detection method, that is, after removing the barking core, they continue to perform new polling mutual detection on other processor cores. For example, if processor core 2 barks, processor core 1 will detect processor core 3 and no longer detect processor core 2.
[0100] The technical solution provided by the embodiment of the present application improves the robustness and reliability of the software watchdog by binding the watchdog thread and high-resolution timer to the processor core, and adopting a method of processor core polling mutual checking and IPI inter-core interrupt notification of the barking core to report errors, compared to the software watchdog solution that comes with the Linux system. This solves the problem of software watchdog failure that may occur when the processor core has a long-term kernel soft lock exception. At the same time, by removing the barking core and adjusting the polling mutual checking method, the problem of a processor core running the watchdog function corresponding to the core (or other core) and the core having a kernel soft lock exception, which causes the watchdog function running on the core to be unable to run, and thus causes the core (or other core) to be unable to be detected, is solved.
[0101] Corresponding to the above-mentioned exception handling method, the embodiment of the present application also provides an exception handling device, such as Figure 6As shown, the device is applied to a first processor core included in a processor, the first processor core is bound to a first watchdog function, and the processor also includes a second processor core. The device includes:
[0102] A detection module 61 is configured to run a first watchdog function to detect whether the second processor core is abnormal;
[0103] The sending module 62 is configured to send a first inter-core interrupt to the second processor core when an exception is detected in the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
[0104] In the technical solution provided by the embodiment of the present application, the processor core is bound to the watchdog function, that is, each watchdog function runs on a specific processor core. The first processor core runs the bound first watchdog function to perform an exception detection on the second processor core. After detecting the exception of the second processor core, an inter-core interrupt is sent to the second processor core, and the second processor core performs the exception processing on its own according to the first inter-core interrupt. Since each processor core is bound to the watchdog function, after any processor core is abnormal, it can be determined that the watchdog function bound to the abnormal processor core is invalid, and then it can be determined that the processor core corresponding to the invalid watchdog function cannot be detected, which solves the problem that the kernel soft lock exception occurs in the processor core, the watchdog function running on the processor core is invalid, resulting in the invalid watchdog function and the part of the processor core that cannot be detected being unable to be determined.
[0105] In some embodiments, the processor may also include a third processor core, the second processor core may be bound to a second watchdog function, and the second watchdog function may be used to detect whether the third processor core is abnormal; the detection module may also be used to run the first watchdog function when the second processor core is detected to be abnormal, so as to detect whether the third processor core is abnormal; the sending module may also be used to send a second inter-core interrupt to the third processor core when the third processor core is detected to be abnormal, so that the third processor core performs exception handling according to the second inter-core interrupt.
[0106] In some embodiments, the detection module may be specifically configured to detect whether the second processor core is abnormal using a first detection variable included in the first watchdog function, the first detection variable indicating that the first watchdog function corresponds to the second processor core;
[0107] The detection module can be specifically used to update the first detection variable included in the first watchdog function to the second detection variable in accordance with the polling mutual inspection order, and the second detection variable indicates that the first watchdog function corresponds to the third processor core; and use the second detection variable included in the first watchdog function to detect whether the third processor core is abnormal.
[0108] In some embodiments, the detection module may be further configured to update the second detection variable included in the first watchdog function to the first detection variable according to a polling mutual detection sequence when the second processor core returns to normal.
[0109] In some embodiments, the apparatus may further include: a receiving module configured to receive a third inter-core interrupt; generate a non-maskable interrupt according to the third inter-core interrupt; and perform exception processing in the non-maskable interrupt.
[0110] An embodiment of the present application also provides a processor, which includes multiple processor cores, each processor core is bound to a watchdog function; each processor core determines the corresponding processor core according to a polling mutual inspection order; runs the bound watchdog function to detect the corresponding processor core; when the corresponding processor core is detected to be abnormal, sends an inter-core interrupt to the corresponding processor core, so that the corresponding processor core performs exception processing according to the inter-core interrupt.
[0111] In another embodiment provided by the present application, a computer-readable storage medium is further provided, in which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned exception handling methods is implemented.
[0112] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).
[0113] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.
[0114] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. In particular, the device, processor, and storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, refer to the descriptions of the method embodiments.
[0115] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.
Claims
1. An exception handling method, characterized in that: Applied to a processor including a first processor core, the first processor core being bound to a first watchdog function, and the processor also including a second processor core, the method comprising: Running the first watchdog function to detect whether the second processor core is abnormal; When an exception is detected in the second processor core, a first inter-core interrupt is sent to the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
2. The method according to claim 1, characterized in that The processor further includes a third processor core, the second processor core is bound to a second watchdog function, and the second watchdog function is used to detect whether the third processor core is abnormal; When an abnormality is detected in the second processor core, the method further includes: Running the first watchdog function to detect whether the third processor core is abnormal; When an exception is detected in the third processor core, a second inter-core interrupt is sent to the third processor core, so that the third processor core performs exception processing according to the second inter-core interrupt.
3. The method according to claim 2, characterized in that The running of the first watchdog function to detect whether the second processor core is abnormal includes: detecting whether the second processor core is abnormal by using a first detection variable included in the first watchdog function, the first detection variable indicating that the first watchdog function corresponds to the second processor core; The running of the first watchdog function to detect whether the third processor core is abnormal includes: updating, in a polling mutual check order, the first detection variable included in the first watchdog function to a second detection variable, where the second detection variable indicates that the first watchdog function corresponds to the third processor core; The second detection variable included in the first watchdog function is used to detect whether the third processor core is abnormal.
4. The method according to claim 3, characterized in that The method further comprises: When the second processor core returns to normal, the second detection variable included in the first watchdog function is updated to the first detection variable in a polling mutual detection order.
5. The method according to claim 1, wherein The method further comprises: Receive the third inter-core interrupt; generating a non-maskable interrupt according to the third inter-core interrupt; Exception handling is performed in the non-maskable interrupt.
6. An exception handling device, characterized in that: The device is applied to a first processor core included in a processor, the first processor core being bound to a first watchdog function, and the processor further including a second processor core, the device comprising: a detection module, configured to run the first watchdog function to detect whether the second processor core is abnormal; The sending module is configured to send a first inter-core interrupt to the second processor core when an exception is detected in the second processor core, so that the second processor core performs exception processing according to the first inter-core interrupt.
7. The device according to claim 6, characterized in that The processor also includes a third processor core, the second processor core is bound to a second watchdog function, and the second watchdog function is used to detect whether the third processor core is abnormal; the detection module is also used to run the first watchdog function to detect whether the third processor core is abnormal when the second processor core is detected to be abnormal; the sending module is also used to send a second inter-core interrupt to the third processor core when the third processor core is detected to be abnormal, so that the third processor core performs exception processing according to the second inter-core interrupt.
8. The device according to claim 7, characterized in that The detection module is specifically configured to detect whether the second processor core is abnormal by using a first detection variable included in the first watchdog function, wherein the first detection variable indicates that the first watchdog function corresponds to the second processor core; The detection module is specifically used to update the first detection variable included in the first watchdog function to a second detection variable in accordance with the polling mutual inspection order, wherein the second detection variable indicates that the first watchdog function corresponds to the third processor core; and use the second detection variable included in the first watchdog function to detect whether the third processor core is abnormal.
9. The device according to claim 8, characterized in that The detection module is further configured to update the second detection variable included in the first watchdog function to the first detection variable according to a polling mutual detection sequence when the second processor core returns to normal.
10. The device according to claim 6, characterized in that The device further includes: a receiving module configured to receive a third inter-core interrupt; generate a non-maskable interrupt according to the third inter-core interrupt; and perform exception processing in the non-maskable interrupt.
11. A processor, characterized in that: The processor includes multiple processor cores, each processor core is respectively bound to a watchdog function; Each processor core determines the corresponding processor core in a polling mutual inspection order; runs the bound watchdog function to detect the corresponding processor core; and when the corresponding processor core is detected to be abnormal, sends an inter-core interrupt to the corresponding processor core so that the corresponding processor core performs exception processing according to the inter-core interrupt.
12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor core included in the processor, the method steps described in any one of claims 1 to 5 are implemented.