Circuit for simulating human brain sleep stage transition and design method

Abstract

The invention relates to the field of memristor neural networks, provides two memristor-based neural networks for simulating a sleep cycle, and realizes and verifies corresponding circuits in PSPICE. The neural network based on the memristor provided by the invention simulates GABAergic neurons (RMTg) in a capped nucleus on the inner side of a brain beak and part of neurons in a capped region (LDT) on the outer side of the brain and a hypothalamic region (LH) on the outer side of the brain. It is proved that activation of GABAergic neurons in RMTg and its subsequent inhibitory effect on LDT and LH regions result in different state transitions between fast eye movement sleep, non-fast eye movement sleep and wakefulness. The designed circuit is very close to a real biological neural network structure, and indirect, direct and variable influences among neurons are considered. The PSPICE simulation result shows that the provided memristor neural network circuit can realize the conversion between different sleep states and wakefulness.

Description

Technical Field

[0001] The present invention relates to a memristive neural network, and in particular to a technology for transitioning between different sleep stages based on a memristive neural network. Background Art

[0002] A memristor is an electronic component with nonlinear resistance properties. It was first proposed by Professor Shao-Tang Tsai in 1971 and successfully fabricated by HP Labs in 2008. Unlike traditional resistors, capacitors, and inductors, memristors can store charge and maintain their resistance value even when powered off. This gives memristors a memory capability similar to that of neurons in the brain. A memristor neural network is an artificial neural network model built on memristors. While traditional artificial neural networks are primarily based on linear models, memristor neural networks leverage the nonlinear properties of memristors to better mimic the behavior of brain neurons. Memristor neural networks update weights and store information by adjusting the resistance of memristors, thereby enabling learning and memory. Memristors and memristor neural networks have broad application prospects in the field of artificial intelligence. They can be used to build efficient pattern recognition systems, embedded smart devices, and intelligent sensor networks. Furthermore, due to the advantages of memristors such as low power consumption, high integration density, and reconfigurability, memristor neural networks also possess strong computing power and storage capacity, making them considered a candidate technology for next-generation artificial intelligence hardware.

[0003] Sleep is a vital physiological process in the human body. During sleep, periods of rapid eye movement (REM) sleep and non-rapid eye movement (NREM) sleep alternate, and periods of wakefulness may occur. Sleep disorders can negatively impact health and well-being. Sleep stage transition technology based on memristive neural networks can simulate and regulate the transitions between different sleep stages, contributing to in-depth research on sleep mechanisms and the occurrence and treatment of related diseases. Individuals may have different sleep needs and stage transitions. Sleep stage transition technology based on memristive neural networks can be tailored to individual sleep patterns and needs, providing personalized sleep treatment plans that help improve sleep quality and regulate the circadian rhythm. Memristors, as a new type of electronic component, have broad application prospects in the fields of artificial intelligence and neural networks. Sleep stage transition technology based on memristive neural networks can further expand the application of memristor technology and promote its research and application in other fields, such as smart healthcare and brain-computer interfaces. Summary of the Invention

[0004] The structure of the memristor neural network is attached. Figure 1The output states of the two sleep-expression neurons, Sleep-expression_1 and Sleep-expression_2, are influenced by synaptic weights W2 and W3. The transitions between different sleep stages and wakefulness are determined by the output states of the two sleep-expression neurons. The output states of sleep-expression neurons and their corresponding sleep states are shown in Appendix 1. '1' indicates that the neuron is in an active state with continuous output, while '0' indicates that the neuron is in an inactive state with no peak output.

[0005]

[0006] Table 1

[0007] Attachment Figure 1 The blue arrows between neurons in the figure represent inhibitory connections, while the red arrows represent facilitatory connections. GABA In -LH, when the LH and Sleep neurons are in an activated state and the RGABA neurons are in an inactivated state, the two sleep-expressing neurons on the right are in an activated state. At this time, the states of the two sleep-expressing neurons are (1, 1), indicating a REM sleep state. When the RGABA neurons are activated, the LH neurons are inhibited by the RGABA neurons, and the synaptic weight W1 gradually decreases. When the LH neuron output is completely inhibited, the prominent weight W2 between the Sleep neuron and the Sleep-expression_1 neuron also gradually decreases. When W2 is less than the weight threshold, the Sleep-expression_1 neuron is in an inactivated state. At this time, the states of the two sleep-expressing neurons change from (1, 1) to (0, 1), indicating that the sleep state changes from REM sleep to NREM sleep.

[0008] In the neural network RMTg GABA -In the LDT, RGABA_1, RGABA_2, and RGABA_3 neurons represent RMTg GABANeurons inhibit connections between different neurons in the LDT. The LDT contains cholinergic neurons (Cho Neuron), glutamatergic neurons (GluNeuron) and GABAergic neurons (LGABANeuron). When Cho neurons, LGABA neurons and Glu neurons are activated, the states of the two sleep-expressing neurons are (1, 1), indicating a REM sleep state. When the RGABA_2 neuron is activated, the weight W4 decreases and the output of the neuron LGABA is inhibited. When W4 is less than the synaptic threshold, the output of the LGABA neuron is completely blocked. The output expression of the Glu neuron inhibited by the LGABA neuron returns to normal, so the synaptic weight W3 between the Sleep neuron and the Sleep-expression_2 neuron gradually decreases. When W3 is less than the weight threshold, the Sleep-expression_2 neuron is in an inactive state and has no output. At this time, the states of the two sleep-expressing neurons change from (1, 1) to (1, 0), indicating a transition from the REM sleep stage to Wakefulness. When RGABA_1 and RGABA_2 neurons are activated simultaneously, the expression of Cho neurons is inhibited, and the prominent weight W2 between the Sleep neuron and the Sleep-expression_1 neuron gradually decreases. When W2 is less than the weight threshold, the Sleep-expression_1 neuron is in an inactive state and has no output. The activation of the RGABA_3 neuron inhibits the output expression of the Glu neuron, so the synaptic weight W3 between the Sleep neuron and the Sleep-expression_2 neuron gradually increases. When W3 is greater than the weight threshold, the Sleep-expression_2 neuron is in an active state. At this time, the states of the two sleep expression neurons change from (1, 0) to (0, 1), indicating a transition from the wakefulness stage to the NREM sleep stage. Memristive neural network RMTg GABA -LH and RMTg GABA -The complete circuit of LDT is attached Figure 2 , Attachment Figure 3 .

[0009] A circuit implementation of different sleep stage transition technology based on memristive neural network is as follows:

[0010] 1. Voltage Control Module

[0011] The voltage control module has two different structures, see Figure 4 (a) and Figure 4(b) In Figure (a), when Input1 and Input2 or Input2 and Input3 are input simultaneously, OR gate D3 opens. At this time, the voltage output by subtractor DIFF1 is lower than the threshold of the signal control switch S1, S1 is closed, and S2 is open. The voltage control module outputs -V2. When only Input2 is input, OR gate D3 closes. At this time, S1 is open and S2 is closed. The voltage control module outputs V1. V Output1 Expressed as:

[0012]

[0013] exist Figure 4 In (b), when Input4 and Input5 are both high, the voltage control switch S3 is open and S4 is closed. The voltage control module outputs V3. When only Input5 is input, S3 is closed and S4 is open. The voltage control module outputs -V4. V Output2 Expressed as:

[0014]

[0015] 2. Synaptic Module

[0016] The synaptic module is the core of the circuit design. The voltage control module applies positive or negative voltage to the memristor, thereby affecting the change in the memristor resistance. The synaptic weight W0 is a fixed value, and there is no synaptic module in the circuit. The synaptic module structure is shown in Figure 5 The output voltage of this module is expressed as:

[0017]

[0018] M1 is a memristor. Input V Input The voltage can be positive or negative. When a negative voltage is input, its absolute value is greater than the positive voltage. To ensure the memristor threshold remains consistent across different inputs, the synaptic module incorporates a voltage-controlled switch. When the input voltage is negative, the signal controls switch S5 to close, V5 = 0V. When the input voltage is positive, S5 opens. When the memristor's resistance falls below the memristor threshold, S6 opens, and the synaptic module generates an output.

[0019] 3. Output Module

[0020] Output module see Figure 6 ABS2 is a mathematical calculation module, and its input and output relationships are described as follows: |V in |=|V out |. V in Indicates the input of ABS2, V outIndicates the output of ABS2. When the output voltage of ABS2 is greater than V7, the output module generates a voltage of 5V. When the voltage output of ABS2 is less than V7, the output module outputs a low level.

[0021] 4. Complete Circuit Design

[0022] Memristor-based neural network RMTg GABA -LH and RMTg GABA -LDT's complete circuits are as follows Figure 2 and Figure 3 As shown. Out1 is the Sleep expression_1 neuron. Out2 is the Sleep expression_1 neuron. N1 is the output signal of the Sleep neuron. Figure 2 In the figure, N2 is the output signal of LH neurons. N3 is the output signal of RGABA neurons. Figure 3 In the figure, N4 is the output signal of RGABA_1 neuron. N5 is the output signal of Cho neuron. N6 is the output signal of RGABA_3 neuron. N7 is the output signal of Glu neuron. N8 is the output signal of RGABA_2 neuron. N9 is the output signal of LGABA neuron. Different sleep stages are determined by V Out1 and V Out2 The output states and corresponding sleep stages are shown in Table 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a structural diagram of the memristive neural network of the present invention;

[0024] Figure 2 This is the circuit structure diagram of the memristive neural network RMTg-LH;

[0025] Figure 3 This is the circuit structure diagram of the memristive neural network RMTg-LDT;

[0026] Figure 4 It is the structure diagram of voltage control module;

[0027] Figure 5 It is a diagram of the synaptic module structure;

[0028] Figure 6 It is the output module structure diagram;

[0029] Figure 7 It is RMTg GABA - Simulation results of the transition from REM sleep to NREM sleep in LH

[0030] Figure 8 It is RMTg GABA-Diagram of simulation results of the transition from REM sleep to wakefulness in LDT.

[0031] Figure 9 It is RMTg GABA -Diagram of simulation results of the transition from wakefulness to NREM sleep in LDT.

[0032] Specific implementation

[0033] 1)RMTg GABA - Transition from REM sleep to NREM sleep during LH

[0034] PSPICE simulation results are shown in Figure 7 In the REM phase, only input signals N1 and N2 output high level. Between 0 and 80 seconds, N3 outputs low level. V SUM1 and V SUM3 The outputs of are V2 and V6 respectively, so the memristors M1 and M2 keep low resistance. Between 80 seconds and 180 seconds, N3 outputs high level. AND gate D1 is open, V SUM1 =-V1. A negative voltage is applied across the memristor M1, causing the resistance of M1 to increase and S3 to close. V SUM2 =(R5 / M1)*V1. OP5 is a comparator. ABS2 When M1 is greater than the threshold value of 0.75kΩ, S4 is closed and V ABS2 =0V. OP5 has no output. AND gate D2 and switch S5 are closed, and switch S6 is open. V SUM3 The output voltage of S7 is -V7. A negative voltage is applied to the memristor M2, the resistance of M2 continues to increase, and S7 is closed. SUM4 =(R 16 / M2)*V7, when the resistance of M2 is greater than 0.5kΩ, V SUM4 is less than the trigger condition of switch S8. S8 is closed, V Out1 is low level. Memristor M3 maintains low resistance state, V Out2 Output high level. V Out1 and V Out2 The output state of N3 changes from (+, +) to (-, +), indicating that the sleep stage changes from REM to NREM. Between 137 seconds and 256 seconds, the sleep state remains in NREM. Between 256 seconds and 400 seconds, N3 outputs a low level. AND gate D1 is closed, switch S1 is closed, and S2 is open. V SUM1 The output voltage is V2. A positive voltage is applied to the memristor M1, V SUM2 =V3+(R5 / M1)*V2. The memristor value of M1 decreases continuously. When the resistance of M1 is lower than 0.75kΩ, S4 opens and V OP5Output high level. AND gates D2 and S5 are open, while S6 is closed. V SUM3 The output voltage of V6 is V6, and a positive voltage is applied to the memristor M2, and its memristance decreases. SUM4 The output voltage is (R 16 / M2)*V6+V8. When the resistance of M2 decreases to 0.5kΩ, S8 opens. V Out2 Output high level. V Out1 and V Out2 The output state changes from (0, 1) to (1, 1), indicating that the sleep stage changes from NREM to REM. The changes in the main parameters of the circuit are shown in Table 2.

[0035] stage <![CDATA[N1]]> <![CDATA[N2]]> <![CDATA[N3]]> <![CDATA[M1]]> <![CDATA[M2]]> <![CDATA[M3]]> <![CDATA[Out1]]> <![CDATA[Out2]]> REM 1 1 0 \ \ \ 1 1 NREM 1 1 1 ↑1 ↑1 \ 0 1 REM 1 1 0 ↓0.4 ↓0.4 \ 1 1

[0036] Table 2

[0037] 2)RMTg GABA -Transition from REM sleep to wakefulness during LDT

[0038] PSPICE simulation results are shown in Figure 8 In the REM phase (0-176 seconds), N1, N5, N7, and N9 output high levels, while N4, N6, and N8 output low levels. SUM1 =V2, so the resistance of memristor M1 remains in a low resistance state. OP5 Output high level, AND gate D2 is open. SUM3 The output of V6 is V6, and the resistance of memristor M2 always remains in the resistance state. Out1 Output high level. AND gate D7 and S 17 Close, S 18 Open. Therefore V SUM9 The output is V 22 The memristor M5 maintains a low resistance state. V OP25 Output high level. AND gate D6, OR gate D5 and S 14 Open, V SUM7 =-V 17 The memristor M4 remains in a high resistance state. Therefore, V OP20 Output low level. AND gate D3 and S 10 Closed, while S9 is open. V SUM5 =V 11 The memristor M3 remains in a low resistance state. V Out2 Output high level. Starting from the 50th second, N8 outputs high level. AND gate D7 and switch S 17 In open state, V SUM9 =-V 21 , a negative voltage is applied to the memristor M5, and the memristor value of M5 gradually increases. SUM10The output is (R 49 / M5)*V 21 When the resistance of M5 is greater than 0.65kΩ, V SUM10 Less than switch S 20 At this time, V OP25 Output low level. AND gate D6, OR gate D5 and switch S 14 Close, S 13 Open. V SUM7 The output is V 16 When a positive voltage is applied to the memristor M4, the resistance of M4 gradually decreases. SUM8 The output is (R 39 / M4)*V 16 +V 18 .When the memory state is less than 0.5kΩ, V SUM8 Greater than switch S 16 At this time, V OP20 The output of the AND gate D3 is high. The voltage control switch S 10 Open, S9 closed. V SUM5 =-V 12 , a negative voltage is applied to the memristor M3, and the resistance of M3 gradually increases. SUM6 The output is (R 27 / M3)*V 12 When the resistance of M3 is greater than 0.5kΩ, V SUM16 Less than switch S 12 At this time, V OP15 Output low level. V Out2 Output low level. V Out1 and V Out2 The output state changes from (1, 1) to (1, 0). This indicates a transition from NREM sleep to wakefulness. The wakefulness phase lasts from 176 to 335 seconds. Indirect influences between neurons are common in biological neural networks. The continuous changes in memristors M5, M4, and M3 reflect the indirect influence relationships between real biological neurons.

[0039] 3)RMTg GABA - Transition from wakefulness to NREM sleep during LDT

[0040] Both REM-Wakefulness transition and Wakefulness-NREM transition are completed in one simulation. The PSPICE simulation results of Wakefulness-NREM transition are shown in Figure 9 N4 and N6 output high level after 250 seconds. AND gate D1 and switch S1 are open, and S2 is closed. V SUM1The output value of is -V1, and a negative voltage is applied to the memristor M1, causing the resistance of M1 to gradually increase. SUM2 The output of (R5 / M1)*V1. When the resistance of M1 is greater than 0.8kΩ, V SUM2 Less than the trigger condition of switch S4. V OP5 The output of is low. Therefore, AND gate D2 and switch S5 are closed, and S6 is open. SUM5 The output value is V SUM5 =-V7, a negative voltage is applied to the memristor M2. Therefore, the resistance of M2 gradually increases, V SUM4 The output is (R 16 / M2)*V7. When the resistance of M2 is greater than 0.8kΩ, V SUM4 Less than the trigger condition of switch S8. V Output1 Output low level. When N6 is high level, AND gate D4, OR gate D6 and switch 14 are open, S 13 Close. V SUM7 Output is -V 17 , a negative voltage is applied to the memristor M4, and the resistance of M4 gradually increases. SUM8 The output is (R 39 / M4)*V 17 When the resistance of M4 is greater than 0.5kΩ, V SUM8 Less than switch S 16 The trigger condition. OP20 The output of D3 and S 10 Close, S9 open. V SUM5 The output is V 11 When a positive voltage is applied to the memristor M3, the resistance of M3 gradually decreases. SUM6 The output is (R 27 / M3)V 11 +V 13 When the resistance of M3 is less than 0.5kΩ, V SUM6 Greater than the trigger condition of switch S12. V Output1 Output high level. At this time, V Out1 and V Out2 The output state of N8 changes from (1, 0) to (0, 1), indicating the transition of the sleep stage from the Wakefulness stage to the NREM stage. 335-512s is the NREM stage. When N8 outputs a high level, the resistance of the memristor M4 decreases. When the resistance is lower than the threshold, V OP20 Output high level. When N6 outputs high level, the resistance of memristor M4 increases. When the resistance exceeds the threshold, V OP20 Output low level. This reflects the RMTg GABAThe inhibitory and disinhibitory effects of neurons on Glu neurons reflect the variable influence between neurons. The changes in the main parameters of the circuit are shown in Table 3.

[0041] stage <![CDATA[N4]]> <![CDATA[N6]]> <![CDATA[N8]]> <![CDATA[M4]]> <![CDATA[M5]]> <![CDATA[M6]]> <![CDATA[M7]]> <![CDATA[M8]]> <![CDATA[Out3]]> <![CDATA[Out4]]> REM 0 0 0 \ \ \ \ \ 1 1 Wakefulness 0 0 1 \ \ ↑1 ↑0.17 ↑1 1 0 NREM 1 1 1 ↑1 ↓1 ↓0.33 ↑1 \ 0 1

[0042] Table 3

Claims

1. A circuit and design method for simulating human brain sleep stage transitions, characterized in that: The following procedures are included: Two new memristive neural networks and circuit implementations are proposed, which refer to the real biological neural network structure and simulate the γ-aminobutyric acid (GABAergic) neurons in the rostromedial tegmental nucleus (RMTg) of the brain, as well as some neurons in the lateral dorsal tegmentum (LDT) and lateral hypothalamus (LH) regions.

2. The memristive neural network according to claim 1, wherein: Increase Sleep neurons and two sleep expression neurons to replace the sleep control neural network in the brain and explore the GABAergic (RMTg GABA ) neurons on the LDT and LH region neurons, as well as the underlying mechanisms of the transitions between REM sleep, NREM sleep, and wakefulness.

3. The memristive neural network according to claims 1 and 2, characterized in that: The output states of two sleep-expression neurons: Sleep-expression_1 neuron and Sleep-expression_2 neuron are affected by synaptic weights W2 and W3; the transition between different sleep stages and wakefulness is determined by the output states of the two sleep-expression neurons. In Figure 1, the blue arrows between neurons indicate inhibitory connections, while the red arrows indicate facilitative connections. In the memristive neural network RMTg GABA -In LH, RGABA represents RMTg GABA Neurons, when the LH and Sleep neurons are in an activated state and the RGABA neuron is in an inactivated state, the states of the two sleep-expressing neurons are (1, 1), indicating a REM sleep state; when the RGABA neuron is activated, the LH neuron is inhibited by the RGABA neuron, and the synaptic weight W1 gradually decreases. When the LH neuron output is completely inhibited, the protruding weight W2 between the Sleep neuron and the Sleep-expression_1 neuron gradually decreases; when W2 is less than the weight threshold, the Sleep-expression_1 neuron is in an inactivated state, and the states of the two sleep-expressing neurons change from (1, 0) to (0, 1), indicating that the sleep state changes from REM sleep to NREM sleep.

4. The memristive neural network according to claims 1 and 2, characterized in that: In the neural network RMTg GABA -LDT, RGABA_1, RGABA_2 and RGABA_3 neurons represent GABAergic neurons in RMTg; LDT contains cholinergic neurons (Cho Neuron), glutamatergic neurons (Glu Neuron) and GABAergic neurons (LGABA Neuron); when Cho neurons, LGABA neurons and Glu neurons are activated, the states of the two sleep expression neurons are (1, 1), indicating REM sleep state; when RGABA_2 neurons are activated, the weight W4 decreases, and the output of neuron LGABA is inhibited. When W4 is less than the synaptic threshold, the output of LGABA neurons is completely blocked; the output expression of Glu neurons inhibited by LGABA neurons returns to normal, so the synaptic weight W3 between Sleep neurons and Sleep-expression_2 neurons gradually decreases. When W3 is less than the weight threshold, Sleep-expression_2 neurons are in an inactive state and have no output. At this time, the states of the two sleep expression neurons change from (1, 1) to (1, 0), indicating a transition from REM sleep stage to Wakeful sleep stage. ss; when RGABA_1 and RGABA_2 neurons are activated at the same time, the expression of Cho neurons is inhibited, and the prominent weight W2 between the Sleep neuron and the Sleep-expression_1 neuron gradually decreases. When W2 is less than the weight threshold, the Sleep-expression_1 neuron is in an inactive state and has no output; the activation of the RGABA_3 neuron inhibits the output expression of the Glu neuron, so the synaptic weight W3 between the Sleep neuron and the Sleep-expression_2 neuron gradually increases. When W3 is greater than the weight threshold, the Sleep-expression_2 neuron is in an active state. At this time, the states of the two sleep expression neurons change from (1, 0) to (0, 1), indicating a transition from the Wakefulness stage to the NREM sleep stage.

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