3D stacked packaging structure and manufacturing method thereof
By setting a passivation layer on the wafer surface and avoiding the circuit under the pad, and adopting the method of electrically connecting the metal layer in the hole with the metal layer extended from the pad, the cost and applicability problems of the existing 3D packaging technology are solved, and low-cost and high-efficiency chip interconnection is achieved.
Patent Information
- Application Number
- CN202510848507.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-09-16
AI Technical Summary
Existing 3D packaging technology is difficult to achieve low cost, high production efficiency and high versatility at the same time, especially when there are circuits or functional areas under the pads. The process has strong limitations and limited scope of application.
A passivation layer is set on the first surface of the wafer to be processed, and a cutting hole is formed through the first patterning and opening, avoiding the functional circuit under the pad, a metal layer is set in the hole, and the pad is electrically connected to the extended metal layer through the communication metal layer to achieve vertical interconnection of the chips.
It improves the versatility of 3D stacked packaging, reduces production costs, and reduces processing and bonding difficulties, expanding chip design space.
Smart Images
Figure CN120656948A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip packaging, and in particular to a 3D stacking packaging structure and a manufacturing method thereof. Background Art
[0002] With technological advancements, the functionality of electronic devices is becoming increasingly complex, placing new demands on chip packaging technology. This increasing functionality means increasingly complex chip packaging integration. Among the various existing chip packaging technologies, 3D chip packaging is an advanced packaging technology that vertically stacks multiple chips or functional modules and utilizes technologies such as through-silicon vias (TSVs) and microbumps to achieve vertical interconnection. Its core goal is to overcome the physical limitations of traditional two-dimensional planar packaging and improve integration, performance, and energy efficiency.
[0003] Current 3D packaging technologies all use a technique called drilling holes at the pad (PAD) position from the back of the chip to achieve vertical penetration of the chip and complete interconnection. However, there are often circuits or functional areas under the chip pads. Direct vertical penetration at the pad position may be obstructed by the circuits or functional areas. Therefore, the process has strong limitations and a limited scope of application. Other types of 3D packaging are too expensive and the complex process leads to low production efficiency.
[0004] In summary, how to broaden the scope of application of chip 3D packaging while ensuring low production costs and high production efficiency is an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide a 3D stacked packaging structure and a manufacturing method thereof to solve the problem in the prior art that chip 3D packaging technology is difficult to achieve low cost, high production efficiency and high versatility.
[0006] To solve the above technical problems, the present invention provides a method for manufacturing a 3D stacked package structure, comprising:
[0007] Step 1: providing a passivation layer on a first surface of the wafer to be processed; the first surface is the surface of the wafer to be processed where the pad is provided;
[0008] Step 2: patterning the passivation layer for the first time, and providing a first channel on the passivation layer; the bottom surface of the first channel exposes the cutting path of the wafer to be processed;
[0009] Step 3: drilling the cutting path through the first hole to obtain a cutting path hole; the depth of the cutting path hole in the thickness direction of the wafer to be processed is greater than the depth of the functional circuit of the wafer to be processed in the thickness direction;
[0010] Step 4: providing an inner metal layer in the cutting hole;
[0011] Step 5: patterning the passivation layer for a second time, and providing a second through hole on the passivation layer; the bottom surface of the second through hole exposes the pad;
[0012] Step six, providing a pad extension metal layer in the second through hole;
[0013] Step seven, providing a communication metal layer on the surface of the passivation layer, wherein the communication metal layer electrically connects the pad extension metal layer and the metal layer in the hole, thereby obtaining a first wafer to be bonded;
[0014] Step eight, bonding the first surface of the first wafer to be bonded to the second wafer to be bonded to obtain a stacked wafer;
[0015] Step nine: grinding the second surface of the first wafer to be bonded in the stacked wafers until the metal layer in the hole is exposed, thereby obtaining a stacked package wafer; the second surface is opposite to the first surface.
[0016] Optionally, in the method for manufacturing the 3D stacked package structure, the first patterning of the passivation layer includes:
[0017] Disposing a patterned first photoresist layer on the surface of the passivation layer, wherein the first photoresist layer includes a cutting path through hole;
[0018] The passivation layer is etched using the first photoresist layer as a mask to obtain a first channel.
[0019] Optionally, in the manufacturing method of the 3D stacked package structure, drilling the cutting lanes through the first holes to obtain cutting lane holes includes:
[0020] The first photoresist layer and the passivation layer are used as masks to perform wet etching or dry etching or laser drilling on the wafer to be processed to obtain cutting holes.
[0021] Optionally, in the method for manufacturing the 3D stacked package structure, providing an in-hole metal layer in the cutting hole includes:
[0022] Disposing a first adhesive layer in the cutting hole;
[0023] An in-hole metal layer is grown in the cutting hole through an electroplating process.
[0024] Optionally, in the manufacturing method of the 3D stacked package structure, the first adhesion layer is a metal titanium layer;
[0025] The thickness of the metal titanium layer ranges from 0.1 micrometers to 0.3 micrometers, inclusive.
[0026] Optionally, in the manufacturing method of the 3D stacked package structure, after providing the in-hole metal layer in the cutting hole, the method further includes:
[0027] The first surface is ground by a CMP process so that the surface of the metal layer in the hole is flush with the surface of the passivation layer.
[0028] Optionally, in the method for manufacturing the 3D stacked package structure, patterning the passivation layer a second time and providing a second through hole on the passivation layer includes:
[0029] Disposing a patterned second photoresist layer on the surface of the passivation layer, wherein the second photoresist layer includes a pad through hole;
[0030] Using the second photoresist layer as a mask, etching the passivation layer to obtain a second through hole;
[0031] Accordingly, a pad extension metal layer is provided in the second through hole, comprising:
[0032] disposing a second adhesive layer in the second through hole;
[0033] growing a pad extension metal layer in the second through hole by an electroplating process;
[0034] Correspondingly, after providing the pad extension metal layer in the second through hole, the method further includes:
[0035] The first surface is ground by a CMP process to make the surface of the metal layer in the hole, the surface of the passivation layer and the surface of the pad extension metal layer flush.
[0036] Optionally, in the manufacturing method of the 3D stacked package structure, providing a communication metal layer on the surface of the passivation layer includes:
[0037] A patterned third photoresist layer is provided on the surface of the passivation layer, wherein the third photoresist layer includes a communication through hole; the bottom surface of the communication through hole exposes the surface of the pad extension metal layer, the surface of the metal layer in the hole, and the surface of the passivation layer between the pad extension metal layer and the metal layer in the hole;
[0038] A communication metal layer is grown in the communication through-hole through a coating process.
[0039] A 3D stacked packaging structure is a packaging structure obtained by any of the above-mentioned manufacturing methods of the 3D stacked packaging structure.
[0040] Optionally, in the 3D stacked packaging structure, the second wafer to be bonded in the 3D stacked packaging structure is also a wafer obtained through steps one to seven.
[0041] The manufacturing method of the 3D stacked packaging structure provided by the present invention comprises the following steps: first, setting a passivation layer on the first surface of the wafer to be processed; the first surface is the surface of the wafer to be processed on which the pad is set; second, patterning the passivation layer for the first time, setting a first channel on the passivation layer; the bottom surface of the first channel exposes the cutting path of the wafer to be processed; third, drilling the cutting path through the first channel to obtain a cutting path hole; the depth of the cutting path hole in the thickness direction of the wafer to be processed is greater than the depth of the functional circuit of the wafer to be processed in the thickness direction; fourth, setting an in-hole metal layer in the cutting path hole; fifth, The passivation layer is patterned for the second time, and a second through hole is set on the passivation layer; the bottom surface of the second through hole exposes the pad; step six, a pad extension metal layer is set in the second through hole; step seven, a communication metal layer is set on the surface of the passivation layer, and the communication metal layer electrically connects the pad extension metal layer with the metal layer in the hole to obtain a first wafer to be bonded; step eight, the first surface of the first wafer to be bonded is bonded to the second wafer to be bonded to obtain a stacked wafer; step nine, the second surface of the first wafer to be bonded of the stacked wafer is ground until the metal layer in the hole is exposed to obtain a stacked package wafer; the second surface is opposite to the first surface. The present invention moves the metal conductive structure that runs through the wafer to be processed to the dicing area of the wafer, drills a hole at this location, and sets a metal layer inside the hole. This avoids the functional circuitry below the pad, freeing the process constraints of 3D stacked packaging, providing greater design space for chip design on the wafer to be processed, and greatly improving the versatility of 3D stacked packaging. In addition, the present invention electrically connects the metal layer inside the hole to the pad through a communication metal layer on the surface of the wafer to be processed. This greatly reduces the processing difficulty of the wafer to be processed without increasing the bonding difficulty of the wafer to be processed, thereby reducing production costs. The present invention also provides a 3D stacked packaging structure with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0043] Figure 1 A schematic flow chart of a specific embodiment of a method for manufacturing a 3D stacked packaging structure provided by the present invention;
[0044] Figures 2 to 15 This is a schematic diagram of the process structure corresponding to each process of a specific embodiment of the method for manufacturing the 3D stacked packaging structure provided by the present invention.
[0045] Reference numerals:
[0046] 10 - Wafer to be processed; 11 - Bonding pad; 12 - Functional circuit; 13 - Cutting channel hole; 14 - Metal layer in hole; 20 - Passivation layer; 21 - First channel; 22 - Second through hole; 23 - Bonding pad extension metal layer; 30 - First photoresist layer; 31 - Cutting channel through hole; 40 - Second photoresist layer; 41 - Bonding pad through hole; 50 - Third photoresist layer; 51 - Communication through hole; 52 - Communication metal layer; DETAILED DESCRIPTION
[0047] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0048] The core of the present invention is to provide a method for manufacturing a 3D stacked packaging structure, a flow chart of a specific embodiment of the invention is shown in FIG. Figure 1 As shown, it is called specific implementation method one, including:
[0049] S101: Step 1, providing a passivation layer on a first surface of a wafer to be processed; the first surface is a surface of the wafer to be processed where a pad is provided.
[0050] Typically, the pad 11 is only provided on one surface of the wafer 10 to be processed. Figure 2 , Figure 2 Schematic diagram of the structure of the wafer 10 to be processed with the passivation layer 20 disposed entirely on the first surface. The thickness of the passivation layer 20 is preferably not less than 3 microns, and of course, it can be adjusted according to actual conditions.
[0051] S102: Step 2, patterning the passivation layer for the first time, and providing a first channel on the passivation layer; the bottom surface of the first channel exposes the cutting path of the wafer to be processed.
[0052] The cutting path of the wafer 10 to be processed is usually located away from the functional circuits 12 of each chip on the wafer 10 to be processed, so as to avoid accidental damage to the functional circuit 12 structure during the subsequent punching process. Figure 3 .
[0053] The diameter of the first channel 21 is preferably in the range of 5 μm to 17 μm, including endpoint values, such as any one of 5.0 μm, 10.2 μm or 17.0 μm. Of course, it can also be adjusted according to actual conditions.
[0054] As a preferred embodiment, this step includes:
[0055] A1: A patterned first photoresist layer 30 is provided on the surface of the passivation layer 20 , wherein the first photoresist layer 30 includes a cutting path through hole 31 .
[0056] The cutting path through hole 31 passes through the first photoresist layer 30. The structural diagram corresponding to this step is shown in FIG. Figure 4 shown.
[0057] A2: Using the first photoresist layer 30 as a mask, the passivation layer 20 is etched to obtain a first channel 21 .
[0058] The structural diagram corresponding to this step is as follows Figure 5 As shown, in this specific embodiment, the first photoresist layer 30 is used to pattern the passivation layer 20. This method can achieve high-precision patterning at a lower cost. Of course, the passivation layer 20 can also be patterned by other methods, which are not limited in the present invention.
[0059] S103: Step three, drilling the cutting lane through the first hole to obtain a cutting lane hole; the depth of the cutting lane hole in the thickness direction of the wafer to be processed is greater than the depth of the functional circuit of the wafer to be processed in the thickness direction.
[0060] Since the cutting hole 13 needs to be filled with metal to obtain the metal layer 14 in the hole, and the role of the metal layer 14 in the hole is to penetrate the final chip, the depth of the functional circuit 12 on the wafer 10 to be processed should not exceed the depth of the metal layer 14 in the hole, that is, it should not exceed the depth of the cutting hole 13, otherwise the functional circuit 12 will be exposed outside the chip, which is unreasonable. The structural diagram of the wafer 10 to be processed with the cutting hole 13 is shown in FIG. Figure 6 shown.
[0061] As a specific implementation method, this step includes:
[0062] The first photoresist layer 30 and the passivation layer 20 are used as masks to perform wet etching, dry etching or laser drilling on the wafer 10 to obtain cutting holes 13 .
[0063] In this specific embodiment, three process methods for obtaining the cutting hole 13 are provided, namely, wet etching, dry etching and laser drilling. The above three process methods are simple and low-cost methods. Of course, other process methods can also be selected according to actual conditions, and the present invention is not limited here.
[0064] S104: Step 4, providing an inner hole metal layer in the cutting hole.
[0065] The metal layer 14 in the hole can be provided by any one of a deposition process or an electroplating process. Of course, it can also be provided by other processes, which are not limited in the present invention. The corresponding structural diagram is shown in FIG. Figure 7 shown.
[0066] As another specific embodiment, providing the inner hole metal layer 14 in the cutting hole 13 includes:
[0067] B1: a first adhesive layer is provided in the cutting hole 13 .
[0068] The first adhesion layer can serve as a growth substrate for the in-hole metal layer 14 to improve the quality of the in-hole metal layer 14 grown by electroplating.
[0069] Furthermore, the first adhesion layer is a metal titanium layer;
[0070] The thickness of the metal titanium layer ranges from 0.1 micrometer to 0.3 micrometer, including endpoint values, such as any one of 0.10 micrometer, 0.22 micrometer or 0.30 micrometer.
[0071] In current chip packaging processes, the majority of conductive structures on a chip are copper structures. Using a titanium layer as the first adhesion layer in the electroplating process can significantly enhance the connection stability between the electroplated copper structure (hereinafter referred to as the in-hole metal layer 14) and the semiconductor structure (hereinafter referred to as the wafer 10 to be processed). Accordingly, the aforementioned thickness range represents the optimal range obtained through extensive theoretical calculations and practical testing. Within this range, the titanium layer can secure the electroplated in-hole metal layer 14 to the semiconductor without significantly increasing costs. Of course, other materials and thicknesses can also be used as the first adhesion layer, and this is not a limitation of the present invention.
[0072] B2: growing an inner metal layer 14 in the cutting hole 13 by electroplating process.
[0073] In this specific embodiment, the first adhesion layer and the electroplating process are used to achieve rapid growth of the metal layer 14 in the hole, which greatly reduces the process difficulty while reducing the cost.
[0074] In addition, after the inner metal layer 14 is provided in the cutting hole 13, the method further includes:
[0075] The first surface is polished by a CMP process so that the surface of the metal layer 14 in the hole is flush with the surface of the passivation layer 20 .
[0076] In this preferred embodiment, the first surface is processed by CMP (chemical mechanical polishing) to make the surface of the metal layer 14 in the hole flush with the surface of the passivation layer 20, which facilitates the subsequent arrangement of the second through hole 22 and the communication metal layer 52 and improves the quality of the above structure.
[0077] S105 : Step five, patterning the passivation layer for a second time, and providing a second through hole on the passivation layer; the bottom surface of the second through hole exposes the pad 11 .
[0078] The structural diagram corresponding to this step is as follows Figure 8 shown.
[0079] S106: Step six, providing a pad extension metal layer in the second through hole.
[0080] The structural diagram corresponding to this step is as follows Figure 9 As shown, the pad extension metal layer 23 fills up the second through hole 22 .
[0081] S107: Step seven, providing a communication metal layer on the surface of the passivation layer, wherein the communication metal layer electrically connects the pad extension metal layer with the metal layer in the hole, thereby obtaining a first wafer to be bonded.
[0082] The communication metal layer 52 should be a thinner layer on the surface of the passivation layer 20 so as not to hinder the subsequent inter-wafer bonding. Similarly, in order not to hinder the subsequent inter-wafer bonding, the surface of the in-hole metal layer 14 should not protrude from the passivation layer 20, and the surface of the pad extension metal layer 23 should not protrude from the passivation layer 20.
[0083] Furthermore, this step includes:
[0084] C1: A patterned third photoresist layer 50 is provided on the surface of the passivation layer 20, and the third photoresist layer 50 includes a communication through hole 51; the bottom surface of the communication through hole 51 exposes the surface of the pad extension metal layer 23, the surface of the in-hole metal layer 14, and the surface of the passivation layer 20 between the pad extension metal layer 23 and the in-hole metal layer 14.
[0085] The structural diagram corresponding to this step is as follows Figure 10 shown.
[0086] C2: growing a communication metal layer 52 in the communication hole 51 through a coating process.
[0087] The structural diagram corresponding to this step is as follows Figure 11 As shown, in this specific embodiment, the patterned communication metal layer 52 is realized by the third photoresist layer 50, which is a process method that ensures low production cost and high graphic accuracy. Of course, other process methods can also be selected according to actual conditions, and the present invention is not limited here.
[0088] S108: Step eight, bonding the first surface of the first wafer to be bonded to the second wafer to be bonded to obtain a stacked wafer.
[0089] The first wafer to be bonded may have the same structure as or different from the second wafer to be bonded. The second wafer to be bonded may not have a metal conductive structure that runs through it in the thickness direction (that is, although the second wafer to be bonded can be bonded to a third wafer on the surface away from the first wafer to be bonded, the third wafer cannot be electrically connected to the second wafer to be bonded through the bonding process). It may also be a wafer that has also undergone steps one to seven.
[0090] The structural diagram corresponding to this step is as follows Figure 12 shown.
[0091] S109: Step nine, grinding the second surface of the first wafer to be bonded in the stacked wafers until the metal layer in the hole is exposed, thereby obtaining a stacked package wafer; the second surface is opposite to the first surface.
[0092] The structural diagram corresponding to this step is as follows Figure 13 After the bonding process is completed, the first wafer to be bonded is thinned to expose the metal layer 14 in the hole at the end away from the first surface (i.e., the second surface), so that the first wafer to be bonded can be electrically connected to an external circuit through the second surface.
[0093] As a preferred embodiment, the passivation layer 20 is patterned for the second time, and a second through hole 22 is provided on the passivation layer 20, including:
[0094] D1: a patterned second photoresist layer 40 is provided on the surface of the passivation layer 20 , wherein the second photoresist layer 40 includes a pad through hole 41 .
[0095] The structural diagram corresponding to this step is as follows Figure 14 shown.
[0096] D2: using the second photoresist layer 40 as a mask, etching the passivation layer 20 to obtain a second through hole 22 .
[0097] The structural diagram corresponding to this step is as follows Figure 15 shown.
[0098] Accordingly, a pad extension metal layer 23 is provided in the second through hole 22, including:
[0099] D3: Disposing a second adhesive layer in the second through hole 22 .
[0100] D4: growing a pad extension metal layer 23 in the second through hole 22 by an electroplating process.
[0101] The material and thickness of the second adhesion layer can refer to the first adhesion layer mentioned above, and the electroplating process of the pad extension metal layer 23 can also refer to the electroplating process of the in-hole metal layer 14 mentioned above, which will not be repeated here.
[0102] Correspondingly, after the pad extension metal layer 23 is provided in the second through hole 22, the method further includes:
[0103] D5: grinding the first surface by a CMP process to make the surface of the in-hole metal layer 14 , the surface of the passivation layer 20 and the surface of the pad extension metal layer 23 flush.
[0104] In other words, after the CMP process in this step, the surfaces of all structures on the first surface are in a flush state, which reduces the difficulty of setting the subsequent communication metal layer 52 and also reduces the difficulty of wafer bonding in subsequent steps, thereby improving the wafer bonding quality.
[0105] The manufacturing method of the 3D stacked packaging structure provided by the present invention comprises the following steps: first, setting a passivation layer 20 on the first surface of the wafer to be processed 10; the first surface is the surface of the wafer to be processed 10 on which the pad 11 is set; second, performing a first patterning on the passivation layer 20, and setting a first channel 21 on the passivation layer 20; the bottom surface of the first channel 21 exposes the cutting path of the wafer to be processed 10; third, opening the cutting path through the first channel 21 to obtain a cutting path hole 13; the depth of the cutting path hole 13 in the thickness direction of the wafer to be processed 10 is greater than the depth of the functional circuit 12 of the wafer to be processed 10 in the thickness direction; fourth, setting an in-hole metal layer 14 in the cutting path hole 13; and fifth, , the passivation layer 20 is patterned for the second time, and a second through hole 22 is set on the passivation layer 20; the bottom surface of the second through hole 22 exposes the pad 11; step six, a pad extension metal layer 23 is set in the second through hole 22; step seven, a communication metal layer 52 is set on the surface of the passivation layer 20, and the communication metal layer 52 electrically connects the pad extension metal layer 23 with the metal layer 14 in the hole to obtain a first wafer to be bonded; step eight, the first surface of the first wafer to be bonded is bonded to the second wafer to be bonded to obtain a stacked wafer; step nine, the second surface of the first wafer to be bonded of the stacked wafer is ground until the metal layer 14 in the hole is exposed to obtain a stacked package wafer; the second surface is opposite to the first surface. In the present invention, the metal conductive structure that passes through the wafer to be processed 10 is moved to the cutting path area of the wafer, and a hole is drilled at this position and a metal layer 14 is set in the hole. This can avoid the functional circuit 12 under the pad 11, freeing the process constraints of the 3D stacked package, providing a larger design space for the chip design on the wafer to be processed 10, and greatly improving the versatility of the 3D stacked package. In addition, in the present invention, the metal layer 14 in the hole is electrically connected to the pad 11 through the communication metal layer 52 on the surface of the wafer to be processed 10, without increasing the bonding difficulty of the wafer to be processed 10, thereby greatly reducing the processing difficulty of the wafer to be processed 10 and reducing production costs.
[0106] The present invention also provides a 3D stacked packaging structure, a structural diagram of a specific embodiment of which is shown as follows: Figure 13 As shown, it is referred to as the second specific embodiment, and the 3D stacked packaging structure is a packaging structure obtained by any of the manufacturing methods of the 3D stacked packaging structure described above.
[0107] The 3D stacked packaging structure provided in this specific embodiment corresponds to the manufacturing method of the 3D stacked packaging structure mentioned above. The specific technical details can be referred to above, and the present invention will not be repeated here.
[0108] As a preferred embodiment, the second wafer to be bonded in the 3D stacked package structure is also the wafer obtained through steps one to seven (eg Figure 13 shown).
[0109] That is, in this preferred embodiment, the two bonded wafers both have the metal layer 14 in the hole connecting the corresponding first surface and second surface, and the second surfaces of the two wafers can be further bonded to other wafers or connected to other external circuits, thereby enhancing the structural design freedom of the 3D stacked packaging structure and reducing the design limitations of the packaging structure.
[0110] The 3D stacked packaging structure provided by the present invention is a packaging structure obtained by any of the above-mentioned manufacturing methods of the 3D stacked packaging structure. In the present invention, the metal conductive structure that passes through the wafer 10 to be processed is moved to the cutting path area of the wafer, and a hole is drilled at this position and a metal layer 14 is provided in the hole. This can avoid the functional circuit 12 under the pad 11, freeing the process constraints of the 3D stacked packaging, providing a larger design space for the chip design on the wafer 10 to be processed, and greatly improving the versatility of the 3D stacked packaging. In addition, in the present invention, the metal layer 14 in the hole is electrically connected to the pad 11 through the communication metal layer 52 on the surface of the wafer 10 to be processed. While not increasing the bonding difficulty of the wafer 10 to be processed, it greatly reduces the processing difficulty of the wafer 10 to be processed and reduces production costs.
[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.
[0112] It should be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.
[0113] The above is a detailed introduction to the 3D stacked packaging structure and its manufacturing method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core ideas of the present invention. It should be noted that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.
Claims
1. A method for manufacturing a 3D stacked package structure, characterized in that: include: Step 1: providing a passivation layer on the first surface of the wafer to be processed; The first surface is a surface on which the bonding pad of the wafer to be processed is provided; Step 2: patterning the passivation layer for the first time, and providing a first channel on the passivation layer; The bottom surface of the first hole exposes the dicing street of the wafer to be processed; Step 3, drilling the cutting path through the first hole to obtain a cutting path hole; The depth of the cutting path hole in the thickness direction of the wafer to be processed is greater than the depth of the functional circuit of the wafer to be processed in the thickness direction; Step 4: providing an inner metal layer in the cutting hole; Step 5: patterning the passivation layer for a second time, and providing a second through hole on the passivation layer; the bottom surface of the second through hole exposes the pad; Step six, providing a pad extension metal layer in the second through hole; Step seven, providing a communication metal layer on the surface of the passivation layer, wherein the communication metal layer electrically connects the pad extension metal layer and the metal layer in the hole, thereby obtaining a first wafer to be bonded; Step eight, bonding the first surface of the first wafer to be bonded to the second wafer to be bonded to obtain a stacked wafer; Step nine, grinding the second surface of the first wafer to be bonded in the stacked wafers until the metal layer in the hole is exposed, thereby obtaining a stacked package wafer; The second surface is opposite to the first surface.
2. The method for manufacturing a 3D stacked package structure according to claim 1, wherein: The first patterning of the passivation layer includes: Disposing a patterned first photoresist layer on the surface of the passivation layer, wherein the first photoresist layer includes a cutting path through hole; The passivation layer is etched using the first photoresist layer as a mask to obtain a first channel.
3. The method for manufacturing a 3D stacked package structure according to claim 2, wherein: The cutting path is opened through the first hole to obtain a cutting path hole, comprising: The first photoresist layer and the passivation layer are used as masks to perform wet etching or dry etching or laser drilling on the wafer to be processed to obtain cutting holes.
4. The method for manufacturing a 3D stacked package structure according to claim 2, wherein: Providing an inner metal layer in the cutting hole includes: Disposing a first adhesive layer in the cutting hole; An in-hole metal layer is grown in the cutting hole through an electroplating process.
5. The method for manufacturing a 3D stacked package structure according to claim 4, wherein: The first adhesion layer is a metal titanium layer; The thickness of the metal titanium layer ranges from 0.1 micrometers to 0.3 micrometers, inclusive.
6. The method for manufacturing a 3D stacked package structure according to claim 2, wherein: After the metal layer is provided in the cutting hole, the method further comprises: The first surface is ground by a CMP process so that the surface of the metal layer in the hole is flush with the surface of the passivation layer.
7. The method for manufacturing a 3D stacked package structure according to claim 1, wherein: Patterning the passivation layer for a second time and providing a second through hole on the passivation layer includes: Disposing a patterned second photoresist layer on the surface of the passivation layer, wherein the second photoresist layer includes a pad through hole; Using the second photoresist layer as a mask, etching the passivation layer to obtain a second through hole; Accordingly, a pad extension metal layer is provided in the second through hole, comprising: disposing a second adhesive layer in the second through hole; growing a pad extension metal layer in the second through hole by an electroplating process; Correspondingly, after providing the pad extension metal layer in the second through hole, the method further includes: The first surface is ground by a CMP process to make the surface of the metal layer in the hole, the surface of the passivation layer and the surface of the pad extension metal layer flush.
8. The method for manufacturing a 3D stacked package structure according to claim 1, wherein: A communication metal layer is provided on the surface of the passivation layer, comprising: A patterned third photoresist layer is provided on the surface of the passivation layer, wherein the third photoresist layer includes a communication through hole; the bottom surface of the communication through hole exposes the surface of the pad extension metal layer, the surface of the metal layer in the hole, and the surface of the passivation layer between the pad extension metal layer and the metal layer in the hole; A communication metal layer is grown in the communication through-hole through a coating process.
9. A 3D stacked packaging structure, characterized in that: The 3D stacked package structure is a package structure obtained by the manufacturing method of the 3D stacked package structure according to any one of claims 1 to 8.
10. The 3D stacked package structure according to claim 9, wherein: The second wafer to be bonded in the 3D stacked packaging structure is also the wafer obtained through steps one to seven.