Wafer bearing device
By using a solid partition in the wafer carrier to separate the first wafer and the second wafer, the problem of diffusion of contaminants is solved, the electrical quality and yield of the product are improved, and space utilization and film forming effects are optimized.
Patent Information
- Application Number
- CN202410369376.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-13
- Filing Date
- 2024-03-28
- Publication Date
- 2025-09-16
AI Technical Summary
During the semiconductor manufacturing process, contaminants on non-product wafers cannot be completely removed, causing them to diffuse to the surface of product wafers during the next manufacturing process, affecting the electrical quality and yield of the products.
A wafer carrying device is designed, which includes a top, a bottom, a support and a solid partition. The partition is used to separate a first wafer and a second wafer to prevent the spread of contaminants.
It effectively blocks contaminants from the second wafer from diffusing into the first wafer, improving the electrical quality and yield of the product, increasing space utilization, and improving film formation performance.
Smart Images
Figure CN120656979A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a carrier device, and in particular to a wafer carrier device. Background Art
[0002] In the semiconductor manufacturing process, a wafer carrier, such as a wafer boat, can accommodate product wafers and can be further arranged in a furnace tube to heat the product wafers to the required reaction temperature. Non-product wafers, such as monitor wafers for monitoring the film formation status, can be further placed in the wafer carrier. Generally, the film (such as silicon dioxide and silicon nitride) generated on the surface of the non-product wafer can be removed through a cleaning process to recycle the non-product wafer for reuse. However, the cleaning process cannot completely remove the contaminants on the non-product wafers. In the next manufacturing process, these contaminants will diffuse to the surface of the product wafer after being heated, resulting in poor electrical quality and yield of the product. Summary of the Invention
[0003] The invention provides a wafer carrying device, which can effectively prevent the wafer from being contaminated.
[0004] The wafer carrier of the present invention is suitable for accommodating a first wafer and a second wafer, and includes a top, a bottom, a plurality of support members, and a plurality of solid partitions. The bottom is opposite the top. The plurality of support members connect the top and bottom near the edges. The plurality of solid partitions are located between the top and bottom, separated from each other, and fixed to the plurality of support members, defining a plurality of slots between the top and bottom. The first wafer and the second wafer are suitable for being disposed adjacent to each other in the plurality of slots, and are separated by one of the plurality of solid partitions.
[0005] In one embodiment of the present invention, a plurality of solid partitions are disposed between the top and the bottom at equal intervals along the central axis of the top.
[0006] In one embodiment of the present invention, the top, bottom, and multiple support members form a storage space. The storage space includes an upper space adjacent to the top, a middle space, and a lower space adjacent to the bottom. The middle space is located between the upper and lower spaces. Multiple solid partitions are disposed along the central axis of the top only in the upper space, the lower space, or both.
[0007] In one embodiment of the present invention, the middle space is a through space, is larger than the upper space, and is also larger than the lower space.
[0008] In one embodiment of the present invention, each of the plurality of support members includes a plurality of supporting portions stacked from top to bottom, each of the plurality of supporting portions includes a supporting surface, and the first wafer or the second wafer is adapted to be supported by the supporting surface.
[0009] In one embodiment of the present invention, the plurality of solid partitions and the plurality of supporting portions are arranged alternately from top to bottom.
[0010] In one embodiment of the present invention, each of the plurality of solid partitions is located between two adjacent ones of the plurality of supporting portions.
[0011] In one embodiment of the present invention, each of the plurality of support members includes a main body and a plurality of supporting portions. The main body connects the top and bottom portions. The plurality of supporting portions are spaced apart from the main body and extend horizontally toward the central axis of the top portion. Each of the plurality of supporting portions includes a supporting surface. The first wafer or the second wafer is adapted to be supported by the supporting surface.
[0012] In one embodiment of the present invention, each of the plurality of solid partitions is located between two adjacent ones of the plurality of supporting portions.
[0013] In one embodiment of the present invention, the projection of each of the plurality of solid partitions onto the plane where the top is located coincides with the top, and / or the projection of each of the plurality of solid partitions onto the plane where the bottom is located coincides with the bottom.
[0014] Based on the above, in the wafer carrier of the present invention, multiple solid partitions are separated from each other, thereby defining multiple slots between the top and bottom. A first wafer and a second wafer are suitably positioned adjacent to each other in the multiple slots, separated by one of the multiple solid partitions. As a result, contaminants from the second wafer are effectively blocked by the solid partitions and cannot diffuse into the first wafer, thereby improving the electrical quality and yield of products manufactured from the first wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic diagram of a wafer carrying device according to an embodiment of the present invention;
[0016] Figure 2 yes Figure 1 A partial front view of a wafer carrying device carrying a first wafer and a second wafer;
[0017] Figure 3 yes Figure 2 A partial schematic diagram from another perspective;
[0018] Figure 4 is a schematic diagram of a wafer carrying device according to another embodiment of the present invention;
[0019] Figure 5 is a schematic diagram of a wafer carrying device according to another embodiment of the present invention;
[0020] Figure 6 yes Figure 5 A partial front view of a wafer carrying device carrying a first wafer and a second wafer.
[0021] Explanation of symbols
[0022] AX: Central axis
[0023] C: Accommodation space
[0024] C1: Upper Space
[0025] C2: Lower Space
[0026] C3: Middle Space
[0027] D: Direction
[0028] P: slot
[0029] W1: First wafer
[0030] W2: Second wafer
[0031] 10, 10a, 10b: Wafer carrier
[0032] 110: Top
[0033] 120: bottom
[0034] 130, 130a: support member
[0035] 131: bearing part
[0036] 132: Depression
[0037] 133: bearing surface
[0038] 134: Main body
[0039] 140:Solid partition DETAILED DESCRIPTION
[0040] Figure 1 FIG. 1 is a schematic diagram of a wafer carrier according to an embodiment of the present invention. Figure 2 yes Figure 1 A partial front view of a wafer carrying device carrying a first wafer and a second wafer. Figure 3 yes Figure 2 In order to clearly show the support member, Figure 3 The top of the wafer carrier is hidden, and the first wafer is shown in dotted lines.
[0041] Please refer to Figures 1 to 3 In this embodiment, the wafer carrier 10 is, for example, a boat, adapted to accommodate the first wafer W1 ( Figure 2 ) to perform semiconductor manufacturing process (such as a manufacturing process using furnace heating) on the first wafer W1 of the same batch. The wafer carrier 10 can also accommodate the second wafer W2 ( Figure 2The second wafer W2 is, for example, a monitor wafer, which can be used to monitor the film forming status of the first wafer W1 and can be recycled and reused through a cleaning process after the semiconductor manufacturing process is completed. However, the type of the second wafer W2 is not limited thereto.
[0042] In this embodiment, the wafer carrier 10 includes a top portion 110, a bottom portion 120 opposite to the top portion 110, a plurality of supports 130, and a plurality of solid partitions 140. The top portion 110 and the bottom portion 120 are parallel to each other. The plurality of supports 130 connect the top portion 110 and the bottom portion 120 near their edges. The plurality of solid partitions 140 are located between the top portion 110 and the bottom portion 120, spaced apart from each other and fixed to the supports 130, thereby defining a plurality of slots P between the top portion 110 and the bottom portion 120.
[0043] In detail, Figure 2 and Figure 3 As shown, each of the plurality of support members 130 includes a plurality of support members 130 extending from a top portion 110 to a bottom portion 120 ( Figure 1 ) direction D. Each of the plurality of supporting portions 131 includes a recess 132 located inside to form a supporting surface 133. The recess 132 and the supporting surface 133 are parallel to the top 110.
[0044] In this embodiment, the first wafer W1 and the second wafer W2 are suitable for being arranged adjacent to each other in a plurality of slots P, and are separated by one of a plurality of solid partitions 140. Specifically, the first wafer W1 and the second wafer W2 are suitable for being inserted into the recess 132 and supported by the supporting surface 133. That is to say, the first wafer W1 or the second wafer W2 can be inserted into the recess 132 at the same height of each support member 130, and supported by the supporting portion 131 at the same height. In another embodiment, the plurality of supporting portions 131 do not include the structure of the recess 132, and the first wafer W1 or the second wafer W2 is supported by the plane formed by the supporting surface 133, so as to achieve the effect of well accommodating the first wafer W1 or the second wafer W2.
[0045] For example, the plurality of support members 130 in this embodiment includes three support members 130. Therefore, the first wafer W1 or the second wafer W2 can be inserted into three recesses 132 at the same height and simultaneously supported by three support portions 131 at the same height. Of course, the present invention does not limit the number of support members 130.
[0046] like Figure 1 As shown, the plurality of solid partitions 140 of this embodiment are arranged at equal intervals along the central axis AX of the top 110 between the top 110 and the bottom 120 ( Figure 1In addition, the plurality of solid partitions 140 and the plurality of supporting portions 131 are staggered along the direction D. In other words, each of the plurality of solid partitions 140 is located between two adjacent ones of the plurality of supporting portions 131.
[0047] In the general manufacturing process using furnace tubes, non-product wafers in the wafer carrier can be recycled and reused. However, since the subsequent cleaning process cannot completely remove the contaminants on the non-product wafers, these contaminants can easily diffuse to the surface of the product wafer due to heat in the next manufacturing process, resulting in poor electrical quality and yield of the product.
[0048] In comparison, in this embodiment, when the first wafer W1 and the second wafer W2 are set in the slot P, the wafer carrier 10 separates the adjacent first wafer W1 and second wafer W2 through the solid partition 140, reducing the possibility of contaminants in the second wafer W2 diffusing to the first wafer W1 and causing contamination thereof, thereby improving the electrical quality and yield of the product.
[0049] It is noteworthy that the area enclosed by the edges of the solid partition 140 in this embodiment is equal to the area of the solid partition 140 itself. In other words, the solid partition 140 lacks hollow areas, holes, or other recessed structures, resulting in a superior barrier effect. When contaminants from the second wafer W2 diffuse within the furnace tube due to heat, they are unable to pass through the solid partition 140 in direction D and reach the adjacent first wafer W1, thereby further preventing contamination of the first wafer W1.
[0050] It should be noted that, in this embodiment Figure 2 and Figure 3 The first wafer W1 and / or the second wafer W2 are schematically illustrated, but are not intended to limit the size, thickness, position and arrangement of the first wafer W1 and the second wafer W2 .
[0051] Figure 4 FIG. 4 is a schematic diagram of a wafer carrying device according to another embodiment of the present invention. Figure 4 The embodiment shown is Figure 1 The main difference between the embodiments shown is that Figure 4 The solid partition 140 is only located in a portion of the wafer carrier 10a. Specifically, the top 110, bottom 120, and multiple support members 130 form a storage space C. Storage space C includes an upper space C1 adjacent to the top 110, a middle space C3, and a lower space C2 adjacent to the bottom 120. The middle space C3 is located between the upper space C1 and the lower space C2.
[0052] The middle space C3 of this embodiment is a continuous space. The middle space C3 is larger than the upper space C1, and the middle space C3 is larger than the lower space C2. The solid partition 140 is disposed in the upper space C1 and the lower space C2. In another embodiment, the solid partition 140 is only disposed in the upper space C1. In another embodiment, the solid partition 140 is only disposed in the lower space C2. The first wafer W1 ( Figure 2 ) is only placed in the middle space C3.
[0053] Because middle space C3 is not occupied by solid partitions 140 and is larger than both upper space C1 and lower space C2, it can be designed to accommodate more first wafers W1, further improving space utilization. Furthermore, compared to upper space C1 and lower space C2, middle space C3 offers better airflow uniformity and thermal stability. Therefore, concentrating first wafers W1 in middle space C3 results in excellent film formation performance.
[0054] In addition, in this embodiment, the second wafer W2 ( Figure 2 ) is only set in the upper space C1, the lower space C2, or the upper space C1 and the lower space C2. Similar to Figure 2 In the aforementioned embodiment, the first wafer W1 and the second wafer W2 are separated by the solid partition 140 , thereby preventing contaminants in the second wafer W2 from diffusing into the first wafer W1 and contaminating the first wafer W1 , thereby improving the electrical quality and yield of the product.
[0055] Figure 5 FIG. 4 is a schematic diagram of a wafer carrying device according to another embodiment of the present invention. Figure 6 yes Figure 5 A partial front view of a wafer carrying device carrying a first wafer and a second wafer. Figure 5 and Figure 6 The embodiment shown is Figure 1 The main difference between the embodiments shown is that Figure 5 and Figure 6 Each of the plurality of supporting members 130a of the wafer carrier 10b includes a main body 134 and a plurality of carrying portions 131a ( Figure 6 ).
[0056] Specifically, the main body 134 connects the top 110 and the bottom 120, and the plurality of supporting portions 131a are disposed at intervals on the main body 134 and extend horizontally toward the central axis AX of the top 110. In other words, the main body 134 of this embodiment is an integrated structure, rather than a Figure 1 The wafer carrying device 10 is formed by stacking a plurality of carrying portions 131 to form a support member 130 .
[0057] like Figure 6As shown, each of the multiple supporting parts 131a includes a recess 132 located on the inner side to form a supporting surface 133. The first wafer W1 or the second wafer W2 is suitable for being inserted into the recess 132 and supported by the supporting surface 133. Each of the multiple solid partitions 140 is located between two adjacent ones of the multiple supporting parts 131a. In another embodiment, the multiple supporting parts 131a do not include the structure of the recess 132, and the first wafer W1 or the second wafer W2 is supported by the plane formed by the supporting surface 133, thereby achieving the effect of well accommodating the first wafer W1 or the second wafer W2. The remaining structure of the wafer supporting device 10b is the same or similar to that of the wafer supporting device 10a, and will not be repeated here.
[0058] It should also be noted that Figure 6 The first wafer W1 and the second wafer W2 are schematically illustrated, but are not intended to limit the size, thickness, position and arrangement of the first wafer W1 and the second wafer W2 .
[0059] In summary, in the wafer carrier of the present invention, multiple solid partitions separate one another, thereby defining multiple slots between the top and bottom portions. A first wafer and a second wafer are suitably positioned adjacent to each other in the multiple slots, separated by one of the multiple solid partitions. Consequently, contaminants from the second wafer are effectively blocked by the solid partitions and prevented from diffusing to the first wafer, thereby improving the electrical quality and yield of products manufactured from the first wafer.
[0060] In addition, the solid partition can be set to be located only in the upper and lower spaces of the accommodating space without occupying the middle space. Therefore, the middle space can be designed to place more first wafers, further improving the space utilization rate of the wafer carrying device.
Claims
1. A wafer carrier, adapted to accommodate a first wafer and a second wafer, comprising: top; a bottom portion, relative to said top portion; a plurality of support members connecting the top and the bottom near the edge; as well as A plurality of solid partitions are located between the top and the bottom, separated from each other, and fixed to the plurality of supports, and define a plurality of slots between the top and the bottom, wherein The first wafer and the second wafer are suitable for being disposed adjacent to each other in the plurality of slots and separated by one of the plurality of solid partitions. 2 . The wafer carrier device as claimed in claim 1 , wherein the plurality of solid partitions are arranged between the top and the bottom at equal intervals along the central axis of the top.
3. The wafer carrier device as described in claim 1, wherein the top, the bottom and the multiple support members form a accommodating space, the accommodating space includes an upper space adjacent to the top, a middle space and a lower space adjacent to the bottom, the middle space is located between the upper space and the lower space, and the multiple solid partitions are only arranged in the upper space, the lower space, or the upper space and the lower space along the central axis of the top. 4 . The wafer carrier device as claimed in claim 3 , wherein the middle space is a through space, the middle space is larger than the upper space, and the middle space is larger than the lower space.
5. The wafer carrier device as described in claim 1, wherein each of the multiple supporting members includes a plurality of carrying parts stacked from the top to the bottom, each of the multiple carrying parts includes a carrying surface, and the first wafer or the second wafer is suitable for being supported by the carrying surface. 6 . The wafer carrier as claimed in claim 5 , wherein the plurality of solid partitions and the plurality of carrier portions are arranged alternately in a direction from the top to the bottom. 7 . The wafer carrier as claimed in claim 5 , wherein each of the plurality of solid partitions is located between two adjacent ones of the plurality of carrier portions.
8. A wafer carrying device as described in claim 1, wherein each of the multiple supporting members includes a main body and multiple carrying parts, the main body connects the top and the bottom, the multiple carrying parts are arranged at intervals on the main body and extend horizontally toward the central axis of the top, each of the multiple carrying parts includes a carrying surface, and the first wafer or the second wafer is suitable for being supported by the carrying surface. 9 . The wafer carrier as claimed in claim 8 , wherein each of the plurality of solid partitions is located between two adjacent ones of the plurality of carrier portions. 10 . The wafer carrier of claim 1 , wherein an area enclosed by an edge of each of the plurality of solid partitions is equal to an area of each of the plurality of solid partitions.