TSV back surface exposing method and wafer

Abstract

The invention relates to the field of integrated circuit manufacturing, in particular to a TSV back exposure method and a wafer. The back surface of the wafer to be processed is thinned, so that the distance between the thinned back surface and the bottom of the TSV metal column does not exceed a first threshold value; arranging an ion barrier layer with a planarized surface on the back surface; performing ion implantation on the back surface, and forming a highly doped region on one side, close to the ion barrier layer, of the silicon substrate; the ion barrier layer is removed; and performing wet etching on the wafer to be processed by using a doping concentration sensitive liquid medicine, removing the highly doped region, and exposing the TSV metal columns on the back surface. According to the invention, the highly-doped region with high surface flatness is formed in the silicon substrate, so that the back surface with high surface flatness can be obtained after the highly-doped region is etched, that is, it can be ensured that all TSVs are exposed at the same time, the subsequent process difficulty is reduced, and the yield of finished products is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a TSV backside exposure method and a wafer. Background Art

[0002] With the development of semiconductor ultra-large-scale integrated circuits, existing technologies and processes are reaching their physical limits. Driven by the pursuit of further miniaturization and multifunctionality in electronic products, new technologies, materials, and techniques are being explored. Three-dimensional stacking technology is one such approach. 3D stacking stacks silicon wafers using bonding techniques to create three-dimensional metal interconnects. This reduces interconnect distances, increases transmission speeds, reduces device size, and opens the possibility of heterogeneous integration.

[0003] One of the key processes in existing 3D stacking technology is the TSV (Through Silicon Via) process. Conventional TSV dimensions, such as those with a depth greater than 50µm, are typically fabricated using a front-side TSV process. This process involves two steps: front-side TSV etching and back-side TSV exposure. This involves etching the front side of the wafer to form a through-layer via and embedding a metal pillar. The back side of the wafer is then thinned until the metal pillar is exposed, forming the TSV structure.

[0004] Among them, the backside TSV exposure process is a relatively difficult process, because the so-called backside TSV exposure requires processes such as silicon substrate grinding, silicon wet etching, silicon dry etching, and silicon planarization (CMP) to expose the TSVs buried in the silicon substrate. However, the precision of the grinding step is difficult to control, and usually causes a total thickness deviation (TTV) of >1um on the wafer surface. This height difference is difficult to remove in subsequent fine processes such as wet, dry, and CMP processes. When the subsequent TSV exposure process is carried out with this TTV, it is easy to cause TSVs in different positions to not be exposed at the same time because the TSV itself will also have depth errors. Even if the TSV can be exposed, the significant difference in the height of the TSV high silicon substrate will greatly increase the difficulty of subsequent processes, such as dielectric layer filling, and reduce the yield of the final product.

[0005] Therefore, how to reduce the total thickness deviation of the ground surface during the backside TSV exposure process, improve the flatness of the ground surface, and thereby ensure that all TSVs are exposed simultaneously, reduce the difficulty of subsequent processes, and improve the yield of finished products, is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a TSV backside exposure method and wafer to solve the problem in the prior art that when the TSV etched on the front side is exposed, the backside grinding accuracy is very poor, resulting in excessive total thickness deviation, which easily leads to the phenomenon that some TSVs cannot be exposed at the same time, resulting in a decrease in yield.

[0007] To solve the above technical problems, the present invention provides a TSV backside exposure method, comprising:

[0008] Obtaining a wafer to be processed; the wafer to be processed is a wafer that has completed a front-side TSV process, including a silicon substrate and a TSV metal column extending in a thickness direction of the silicon substrate;

[0009] Thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal column does not exceed a first threshold;

[0010] An ion barrier layer with a flat surface is provided on the back surface; the difference between the ion permeability of the ion barrier layer and the ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold value;

[0011] Performing ion implantation on the back surface to form a highly doped region on a side of the silicon substrate close to the ion barrier layer;

[0012] removing the ion barrier layer;

[0013] The wafer to be processed is wet-etched using a doping concentration sensitive solution to remove the highly doped area and expose the TSV metal column on the back surface.

[0014] Optionally, in the TSV backside exposure method, the first threshold value ranges from 2 micrometers to 3 micrometers, including endpoint values.

[0015] Optionally, in the TSV backside exposure method, providing a surface planarized ion barrier layer on the backside surface includes:

[0016] providing a fluid layer on the back surface by FCVD and / or spin coating;

[0017] The fluid layer is baked and / or annealed to obtain the ion barrier layer.

[0018] Optionally, in the TSV backside exposure method, the ion barrier layer includes at least one of a photoresist layer, a silicon oxide layer, a polyimide layer, and a benzocyclobutene layer.

[0019] Optionally, in the TSV backside exposure method, the second threshold value ranges from 8% to 13%, inclusive.

[0020] Optionally, in the TSV backside exposure method, the thickness of the highly doped region ranges from 3 microns to 4 microns, including end points.

[0021] Optionally, in the TSV backside exposure method, the etching selectivity ratio of the doping concentration sensitive solution is greater than 100:1.

[0022] Optionally, in the TSV backside exposure method, the doping concentration sensitive solution is an HNA solution.

[0023] Optionally, in the TSV back surface exposure method, the ion implantation on the back surface includes:

[0024] Ion boron or ion phosphorus is implanted into the back surface.

[0025] A wafer is obtained by any one of the above-mentioned TSV backside exposure methods.

[0026] The TSV back side exposure method provided by the present invention comprises the following steps: obtaining a wafer to be processed; the wafer to be processed is a wafer on which a front-side TSV process has been completed, comprising a silicon substrate and a TSV metal column extending in the thickness direction of the silicon substrate; thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal column does not exceed a first threshold; providing a surface-flattened ion barrier layer on the back surface; the difference between the ion permeability of the ion barrier layer and the ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold; performing ion implantation on the back surface to form a highly doped region on the side of the silicon substrate close to the ion barrier layer; removing the ion barrier layer; and wet-etching the wafer to be processed using a doping concentration-sensitive solution to remove the highly doped region and expose the TSV metal column on the back surface.

[0027] The present invention sets a sufficiently flat ion barrier layer on the surface that is not flat enough, and forms a highly doped region inside the silicon substrate through an ion implantation process. Since the ion penetration rate of the ion barrier layer and the silicon substrate is similar, the boundary between the highly doped region and the non-highly doped region corresponds to the surface of the ion barrier layer away from the silicon substrate. Since the surface flatness of the ion barrier layer is much higher than the flatness of the back surface of the wafer to be processed, a highly flat back surface can be obtained after etching away the highly doped region, which can ensure that all TSVs are exposed at the same time, reduce the difficulty of subsequent processes, and improve the yield rate of finished products. The present invention also provides a wafer with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic flow chart of a specific embodiment of the TSV backside exposure method provided by the present invention;

[0030] Figures 2 to 5 A process structure diagram corresponding to each step of a specific embodiment of the TSV backside exposure method provided by the present invention;

[0031] Figure 6 This is a flow chart of another specific embodiment of the TSV backside exposure method provided by the present invention.

[0032] Reference numerals:

[0033] 101 - silicon substrate; 102 - TSV metal pillar; 103 - ion barrier layer. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0035] The core of the present invention is to provide a TSV backside exposure method, a flow chart of a specific embodiment of the method is shown as follows: Figure 1 As shown, it is called specific implementation method one, including:

[0036] S101: Obtain a wafer to be processed; the wafer to be processed is a wafer that has completed the front-side TSV process, including a silicon substrate and TSV metal pillars extending in the thickness direction of the silicon substrate.

[0037] S102: Thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal pillar does not exceed a first threshold.

[0038] The schematic diagram of the structure of the wafer to be processed after thinning is as follows Figure 2 shown.

[0039] Furthermore, the first threshold value ranges from 2 microns to 3 microns, including endpoint values ​​such as any one of 2.0 microns, 2.1 microns, or 3.0 microns. If the distance between the back surface and the bottom of the TSV metal pillar 102 is too large, the subsequent etching and planarization processes will be more difficult. If the distance between the back surface and the bottom of the TSV metal pillar 102 is too small, the flatness of the back surface will be further reduced. The above parameter range is the optimal range after extensive theoretical verification and practical testing. Of course, the parameter range can also be adjusted according to actual conditions, and the present invention is not limited here.

[0040] S103: providing a surface-planarized ion barrier layer on the back surface; a difference between an ion permeability of the ion barrier layer and an ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold.

[0041] The flattened ion barrier layer 103 means that the height error of the ion barrier layer 103 away from the surface of the silicon substrate 101 is less than a preset threshold value. Of course, the specific parameters of the threshold value can be selected according to actual conditions, and the present invention is not limited here. The structural diagram of the wafer to be processed with the surface flattened ion barrier layer 103 is shown in FIG. Figure 3 shown.

[0042] As a preferred embodiment, providing a surface-planarized ion barrier layer 103 on the back surface includes:

[0043] A1: A fluid layer is provided on the back surface by FCVD and / or spin coating.

[0044] The FCVD is flow chemical vapor deposition. Whether FCVD or spin coating is used, a fluid layer with excellent flatness, that is, a plastic layer with certain fluidity, can be obtained.

[0045] A2: baking and / or annealing the fluid layer to obtain the ion barrier layer 103 .

[0046] The fluid layer which still has a certain fluidity in the previous step is solidified by heat treatment means such as baking and / or annealing to form the ion barrier layer 103 .

[0047] In this preferred embodiment, the surface-flattened ion barrier layer 103 is set by the FCVD and / or spin coating method. FCVD itself is a CVD process with good fluidity and filling properties. The surface flatness of the obtained ion barrier layer 103 is very high. Spin coating can greatly improve production efficiency while ensuring good surface flatness. The specific process to be used can be selected according to actual conditions, and the present invention does not limit it here.

[0048] Furthermore, the ion barrier layer 103 includes at least one of a photoresist layer (PR), silicon oxide, a polyimide layer (PI) and a benzocyclobutene layer (BCB). The ion barrier layer 103 of the above four materials has very good fluidity and ductility, which can further effectively improve the surface flatness of the ion barrier layer 103. Of course, other materials can also be used as the ion barrier layer 103, such as other types of organic material layers, which is not limited in the present invention.

[0049] Furthermore, the second threshold value ranges from 8% to 13%, including endpoint values ​​such as any one of 8.0%, 10.2%, or 13.0%. Under ion implantation conditions with the same power, the percentage difference between the penetration depth of the ion barrier layer 103 and the penetration depth of the silicon substrate can be directly tested as a criterion for determining the second threshold value. Of course, other parameters can also be used as a criterion for the difference between the ion penetration rate of the ion barrier layer 103 and the ion penetration rate of the silicon substrate of the wafer to be processed. The above range is the optimal range after extensive theoretical calculations and actual testing. Of course, it can also be adjusted according to actual conditions, and will not be elaborated on here.

[0050] S104: Perform ion implantation on the back surface to form a highly doped region on a side of the silicon substrate close to the ion barrier layer.

[0051] In this step, the required ion implantation energy can be obtained through simulation and experiment, such as using a stepwise ion implantation from low energy (~10KeV) to high energy (~1000KeV), which is not limited in the present invention. Figure 4 As shown, the boundary between the high-doped region formed by ion implantation and the original silicon substrate 101 is Figure 4 Indicated by a dotted line composed of "X".

[0052] It should be noted that the highly doped region itself is part of the silicon substrate. After ion implantation into the back surface, a doping concentration gradient will be formed inside the silicon substrate, with the doping concentration gradually decreasing from the back surface to the inside. Since the ion barrier layer and the silicon substrate can be regarded as equivalent in terms of the effectiveness of blocking ions, the ion gradient interface inside the silicon substrate is consistent with the interface morphology of the ion barrier layer on the back surface, and has a very high flatness. In actual production, a specific doping concentration can be determined as needed, and the interface corresponding to the doping concentration can be determined. At this time, the area between the interface and the back surface is the highly doped region.

[0053] Preferably, the thickness range of the highly doped region is 3 microns to 4 microns, including endpoint values, such as any one of 3.0 microns, 3.5 microns or 4.0 microns. Within the above range, the highly doped region is neither too thick to slow down production efficiency nor too thin to cause too large an error. Of course, the parameter range can be adjusted according to actual needs.

[0054] S105: removing the ion barrier layer.

[0055] The method for removing the ion barrier layer 103 depends on the type of material of the ion barrier layer 103. For example, if photoresist spin coating is used, a conventional desmearing process (dry oxidation removal + wet cleaning) can be used. If it is other organic materials such as PI, BCB, etc., dry and wet etching processes can be used to stop at the surface of the silicon substrate to complete the removal of the ion barrier layer 103.

[0056] S106: wet-etching the wafer to be processed using a doping concentration sensitive solution to remove the highly doped area and expose the TSV metal pillar on the back surface.

[0057] The doping concentration sensitive solution is also an etching solution with a relatively large selectivity for etching high-doped silicon and low-doped silicon. After this step, it can be further determined that, in the case of determining the doping concentration sensitive solution in advance, the doping concentration corresponding to the high-doped region can be determined based on the etching selectivity of the doping concentration sensitive solution. Preferably, the etching selectivity of the doping concentration sensitive solution is greater than 100:1. Under the premise that the etching selectivity is greater than 100:1, the doping concentration sensitive solution will etch the non-high-doped stock group at a nearly stagnant speed after the high-doped region is etched, which can further ensure the flatness of the back surface of the silicon substrate 101 remaining after removing the high-doped region. Of course, other parameter ranges can also be selected, and the present invention is not limited here. The structural schematic diagram corresponding to this step is shown as follows: Figure 5 shown.

[0058] Specifically, the doping concentration sensitive solution is HNA solution, which is a hydrofluoric acid-nitric acid-acetic acid mixed etching solution. While maintaining a low cost, a higher etching selectivity ratio between highly doped silicon and low doped silicon is obtained. Of course, other doping concentration sensitive solutions can also be selected, and the present invention is not limited here.

[0059] The TSV back side exposure method provided by the present invention is to obtain a wafer to be processed; the wafer to be processed is a wafer that has completed the front TSV process, including a silicon substrate 101 and a TSV metal column 102 extending in the thickness direction of the silicon substrate; the back surface of the wafer to be processed is thinned so that the distance between the thinned back surface and the bottom of the TSV metal column 102 does not exceed a first threshold; a surface-flattened ion barrier layer 103 is provided on the back surface; the difference between the ion permeability of the ion barrier layer 103 and the ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold; ion implantation is performed on the back surface to form a highly doped region on the side of the silicon substrate 101 close to the ion barrier layer 103; the ion barrier layer 103 is removed; and the wafer to be processed is wet-etched using a doping concentration-sensitive solution to remove the highly doped region and expose the TSV metal column 102 on the back surface. The present invention sets a sufficiently flat ion barrier layer 103 on the surface that is not flat enough, and forms a highly doped area inside the silicon substrate through an ion implantation process. Since the ion penetration rates of the ion barrier layer 103 and the silicon substrate are similar, the boundary line between the highly doped area and the non-highly doped area corresponds to the surface of the ion barrier layer 103 away from the silicon substrate 101. Since the surface flatness of the ion barrier layer 103 is much higher than the flatness of the back surface of the wafer to be processed, a highly flat back surface can be obtained after etching away the highly doped area, which means that all TSVs can be exposed at the same time, reducing the difficulty of subsequent processes and improving the yield of finished products.

[0060] On the basis of the specific embodiment 1, the ion implantation is further limited to obtain the specific embodiment 2, and the corresponding flow diagram is as follows: Figure 6 As shown, it is called the second specific implementation method, including:

[0061] S201: Obtain a wafer to be processed; the wafer to be processed is a wafer that has completed the front TSV process, including a silicon substrate and TSV metal pillars extending in the thickness direction of the silicon substrate.

[0062] S202: Thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal pillar does not exceed a first threshold.

[0063] S203: providing a surface-planarized ion barrier layer on the back surface; a difference between an ion permeability of the ion barrier layer and an ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold.

[0064] S204 : performing ion boron or ion phosphorus implantation on the back surface to form a highly doped region on a side of the silicon substrate close to the ion barrier layer 103 .

[0065] S205: removing the ion barrier layer.

[0066] S206: wet-etching the wafer to be processed using a doping concentration sensitive solution to remove the highly doped region and expose the TSV metal pillar on the back surface.

[0067] The difference between this specific embodiment and the above specific embodiment is that the type of ions in the ion implantation is limited in this specific embodiment, and the remaining steps are the same as those in the above specific embodiment, which will not be described in detail here.

[0068] In this specific embodiment, the ion implantation is specifically limited to ion boron or ion phosphorus implantation. Boron and phosphorus have relatively small atomic masses, and therefore can be implanted to a relatively deep depth, providing a larger scope of application for the present invention. It can also improve the uniformity of ion implantation and the flatness of the back surface after wet etching.

[0069] The present invention also provides a wafer, which is a wafer obtained by any of the above-mentioned TSV back exposure methods. The TSV back exposure method provided by the present invention is as follows: obtaining a wafer to be processed; the wafer to be processed is a wafer that has completed the front TSV process, comprising a silicon substrate 101 and a TSV metal pillar 102 extending in the thickness direction of the silicon substrate; thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal pillar 102 does not exceed a first threshold; providing a surface-flattened ion barrier layer 103 on the back surface; the difference between the ion permeability of the ion barrier layer 103 and the ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold; performing ion implantation on the back surface to form a highly doped region on the side of the silicon substrate 101 close to the ion barrier layer 103; removing the ion barrier layer 103; wet etching the wafer to be processed using a doping concentration-sensitive solution to remove the highly doped region and expose the TSV metal pillar 102 on the back surface. The present invention sets a sufficiently flat ion barrier layer 103 on the surface that is not flat enough, and forms a highly doped area inside the silicon substrate through an ion implantation process. Since the ion penetration rates of the ion barrier layer 103 and the silicon substrate are similar, the boundary line between the highly doped area and the non-highly doped area corresponds to the surface of the ion barrier layer 103 away from the silicon substrate 101. Since the surface flatness of the ion barrier layer 103 is much higher than the flatness of the back surface of the wafer to be processed, a highly flat back surface can be obtained after etching away the highly doped area, which means that all TSVs can be exposed at the same time, reducing the difficulty of subsequent processes and improving the yield of finished products.

[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0071] It should be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0072] The above is a detailed introduction to the TSV backside exposure method and wafer provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A TSV backside exposure method, characterized in that: include: Obtaining wafers to be processed; The wafer to be processed is a wafer that has completed the front TSV process, including a silicon substrate and a TSV metal column extending in the thickness direction of the silicon substrate; Thinning the back surface of the wafer to be processed so that the distance between the thinned back surface and the bottom of the TSV metal column does not exceed a first threshold; An ion barrier layer with a flat surface is provided on the back surface; the difference between the ion permeability of the ion barrier layer and the ion permeability of the silicon substrate of the wafer to be processed is less than a second threshold value; Performing ion implantation on the back surface to form a highly doped region on a side of the silicon substrate close to the ion barrier layer; removing the ion barrier layer; The wafer to be processed is wet-etched using a doping concentration sensitive solution to remove the highly doped area and expose the TSV metal column on the back surface.

2. The TSV backside exposure method according to claim 1, wherein: The first threshold value ranges from 2 microns to 3 microns, inclusive.

3. The TSV backside exposure method according to claim 1, wherein: Providing a surface-planarized ion barrier layer on the back surface includes: providing a fluid layer on the back surface by FCVD and / or spin coating; The fluid layer is baked and / or annealed to obtain the ion barrier layer.

4. The TSV backside exposure method according to claim 1, wherein: The ion barrier layer includes at least one of a photoresist layer, a silicon oxide layer, a polyimide layer and a benzocyclobutene layer.

5. The TSV backside exposure method according to claim 1, wherein: The second threshold value ranges from 8% to 13%, inclusive.

6. The TSV backside exposure method according to claim 1, wherein: The thickness of the highly doped region ranges from 3 microns to 4 microns, inclusive.

7. The TSV backside exposure method according to claim 1, wherein: The step of implanting ions into the back surface comprises: Ion boron or ion phosphorus is implanted into the back surface.

8. The TSV backside exposure method according to any one of claims 1 to 7, wherein: The etching selectivity ratio of the doping concentration sensitive solution is greater than 100:

1.

9. The TSV backside exposure method according to claim 8, wherein: The doping concentration-sensitive liquid medicine is HNA liquid medicine.

10. A wafer, characterized in that: The wafer is a wafer obtained by the TSV backside exposure method according to any one of claims 1 to 9.

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