Multi-chip fan-out packaging structure and packaging method
Through the multi-chip fan-out packaging structure, the adhesive fixing chip and dry film protection of the BCB layer are used, combined with the thermal compression bonding of the silicon bridge chip, which solves the problem of I/O density reduction in the existing technology, and realizes high-density I/O connection and reduced package thickness.
Patent Information
- Application Number
- CN202510860978.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-09-16
AI Technical Summary
In existing silicon bridge front-end packaging solutions, the Molding Interposer process warpage control is stringent, resulting in the inability to further reduce I/O density.
A multi-chip fan-out packaging structure is adopted, the chip is fixed by the viscosity of the BCB layer, and dry film lamination is used to prevent plastic package deviation. Combined with the thermal compression bonding of the silicon bridge chip, high-density I/O interconnection is achieved.
This achieves high-density I/O connections, reduces package thickness, and increases I/O density in shrinking spaces.
Smart Images
Figure CN120657033A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, and in particular to a multi-chip fan-out packaging structure and a packaging method. Background Art
[0002] Existing silicon bridge advanced packaging solutions, such as Figure 3 As shown, the silicon bridge is essentially placed in the mold interposer, where solder joints are re-routed and soldered to the upper chip's HBM / NPU for FC soldering. This places stringent control on the mold interposer's warpage process. Consequently, the upper chip is limited by the FC+MR process, preventing further reduction in I / O density. Summary of the Invention
[0003] In order to overcome the deficiencies of the prior art, the present invention provides a multi-chip fan-out packaging structure and a packaging method.
[0004] To achieve the above objectives, a multi-chip fan-out packaging structure is designed, including a first redistribution layer, wherein a first UBM layer and a conductive structure are respectively provided on one surface of the first redistribution layer, the first UBM layer is electrically connected to the silicon bridge chip, and a second redistribution layer is provided on the other end of the conductive structure. A BCB layer is provided on the other surface of the first redistribution layer, a chip is provided on one side of the BCB layer, and a dry film is provided on the outside of the chip.
[0005] The BCB layer is provided with a plurality of opening areas, the positions of the opening areas match the positions of the I / O ports of the chip, and the I / O ports of the chip are electrically connected to the first rewiring layer.
[0006] Plastic sealing layers are respectively provided on both sides of the first rewiring layer, and the plastic sealing layer on one side is exposed to the silicon surface of the chip.
[0007] One side of the second redistribution layer is connected to the solder balls through the second UBM layer.
[0008] To achieve the above objectives, a packaging method for a multi-chip fan-out packaging structure is designed, comprising the following steps: S1, providing a carrier board and coating a release layer on the carrier board; S2, forming a BCB layer on the peeling layer and leaving a plurality of opening areas on the BCB layer; S3, flip the chip and fix it, so that the I / O port of the chip falls in the opening area; S4, performing dry film molding on the chip surface and curing; S5, first plastic sealing; S6, removing the carrier board and the peeling layer; S7, forming a first redistribution layer on the exposed chip surface, and forming a first UBM layer and a conductive structure at different positions of the first redistribution layer; S8, hot-pressing and welding the silicon bridge chip on the first UBM layer, and filling an NCF film between the silicon bridge chip and the first redistribution layer; S9, second plastic sealing, the plastic sealing height exceeds the height of the conductive structure; S10, thinning until one end surface of the conductive structure is exposed; S11, forming a second redistribution layer on the thinned surface, and performing UBM processing and ball planting respectively.
[0009] In the step S2, a mark required for flip-sticking the chip is formed on the BCB layer.
[0010] In the step S5, the thickness of the plastic package is greater than the thickness of the chip by 100 μm.
[0011] In step S7, the I / O port of the chip is electrically connected to the first redistribution layer. In step S8, the silicon bridge chip is electrically connected to the first redistribution layer through the first UBM layer.
[0012] In the step S7, the height of the conductive structure is greater than 100 um.
[0013] The method further includes step S12, thinning the chip a second time until the silicon surface of the chip is exposed.
[0014] Compared with the existing technology, the present invention utilizes the adhesiveness of BCB to first fix multiple chips, and then uses dry film lamination to prevent chip displacement during subsequent plastic packaging. In addition, high-density I / O interconnection is achieved through thermal compression bonding of silicon bridge chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a structural schematic diagram of the present invention.
[0016] Figure 2 It is a schematic diagram of the process of the present invention.
[0017] Figure 3 Schematic diagram of the process of the existing CoWoS_L structure before improvement by the present invention. DETAILED DESCRIPTION
[0018] The present invention will be further described below with reference to the accompanying drawings.
[0019] like Figure 1As shown, a first UBM layer 4 and a conductive structure 5 are provided on one side surface of the first redistribution layer 3. The first UBM layer 4 is electrically connected to the silicon bridge chip 6. A second redistribution layer 7 is provided on the other end of the conductive structure 5. A BCB layer 8 is provided on the other side surface of the first redistribution layer 3. A chip 9 is provided on one side of the BCB layer 8. A dry film 10 is provided on the outside of the chip 9.
[0020] The BCB layer 8 is provided with a plurality of opening areas 11 . The positions of the opening areas 11 match the positions of the I / O ports of the chip 9 . The I / O ports of the chip 9 are electrically connected to the first rewiring layer 3 .
[0021] Plastic sealing layers 12 are respectively provided on both sides of the first rewiring layer 3 , and the plastic sealing layer 12 on one side exposes the silicon surface of the chip 9 .
[0022] One side of the second redistribution layer 7 is connected to the solder ball 14 through the second UBM layer 13 .
[0023] like Figure 2 As shown, the packaging method of the multi-chip fan-out packaging structure includes the following steps: S1 , providing a carrier board 1 , and coating a release layer 2 on the carrier board 1 .
[0024] S2: Form a BCB layer 8 on the peeling layer 2, leaving several openings 11 in the BCB layer 8. Uncured BCB material is used for the BCB layer 8, which is adhesive. Marks for flip-sticking the chip 9 are also formed on the BCB layer 8 to facilitate flip-sticking the chip in subsequent processes.
[0025] S3 , flip-flopping and fixing the chip 9 , with the I / O port of the chip 9 located at the opening area 11 . In this embodiment, there are two chips 9 .
[0026] S4 , performing a dry film 10 molding process on the surface of the chip 9 and curing the dry film 10 to fix the chip 9 .
[0027] S5, the first plastic packaging, the thickness of the plastic packaging is greater than the thickness of the chip 9 by 100 μm.
[0028] S6, removing the carrier board 1 and the peeling layer 2.
[0029] S7: A first redistribution layer 3 is formed on the exposed surface of chip 9. A first UBM layer 4 and a conductive structure 5 are formed at different locations on the first redistribution layer 3. The I / O ports of chip 9 are electrically connected to the first redistribution layer 3. The first UBM layer 4 is used to form an electrical connection with the silicon bridge chip 6. The conductive structure 5 is greater than 100 μm in height and is used to form an electrical connection with the second redistribution layer 7.
[0030] S8 , thermally pressing and welding the silicon bridge chip 6 on the first UBM layer 4 , and filling the NCF film 15 between the silicon bridge chip 6 and the first redistribution layer 3 .
[0031] S9, the second plastic sealing, the plastic sealing height exceeds the height of the conductive structure 5.
[0032] S10, thinning until one end surface of the conductive structure 5 is exposed.
[0033] S11, forming a second redistribution layer 7 on the thinned surface, and performing UBM processing and ball planting respectively to form a structure electrically connected to the outside world.
[0034] S12, thinning for the second time until the silicon surface of the chip 9 is exposed, thereby reducing the thickness of the entire package.
[0035] The present invention forms a multi-chip fan-out packaging structure, in which a silicon bridge chip 6 is built in. The silicon bridge chip 6 is electrically connected to both chips through the first UBM layer and the first redistribution layer, respectively, to achieve high-density I / O interconnection. The viscosity of the BCB material before solidification is utilized to achieve adhesion and fixation of the chip 9 when it is flipped upside down. A dry film is used to form a protective film on the chip with reconstructed surface. After solidification, it prevents chip displacement caused by impact during subsequent plastic packaging. The pads on the chip surface are directly led out through the first redistribution layer 3, eliminating the need to make electrical connection structures on the chip surface in advance, thereby reducing impedance.
Claims
1. A multi-chip fan-out package structure, comprising a first redistribution layer, characterized in that: A first UBM layer (4) and a conductive structure (5) are respectively provided on one side surface of the first redistribution layer (3); the first UBM layer (4) is electrically connected to a silicon bridge chip (6); a second redistribution layer (7) is provided on the other end of the conductive structure (5); a BCB layer (8) is provided on the other side surface of the first redistribution layer (3); a chip (9) is provided on one side of the BCB layer (8); and a dry film (10) is provided on the outer side of the chip (9).
2. The multi-chip fan-out packaging structure according to claim 1, wherein: The BCB layer (8) is provided with a plurality of opening areas (11), the positions of the opening areas (11) match the positions of the I / O ports of the chip (9), and the I / O ports of the chip (9) are electrically connected to the first rewiring layer (3).
3. The multi-chip fan-out packaging structure according to claim 1, wherein: Plastic sealing layers (12) are respectively provided on both side surfaces of the first rewiring layer (3), wherein the plastic sealing layer (12) on one side exposes the silicon surface of the chip (9).
4. The multi-chip fan-out packaging structure according to claim 1, wherein: One side of the second redistribution layer (7) is connected to the solder ball (14) via the second UBM layer (13).
5. A packaging method for a multi-chip fan-out packaging structure, characterized in that: The steps include: S1, providing a carrier plate (1), and coating a release layer (2) on the carrier plate (1); S2, forming a BCB layer (8) on the peeling layer (2), and leaving a plurality of opening areas (11) on the BCB layer (8); S3, flip-sticking and fixing the chip (9), with the I / O port of the chip (9) falling on the opening area (11); S4, performing a dry film (10) molding process on the surface of the chip (9) and performing curing; S5, first plastic sealing; S6, removing the carrier plate (1) and the peeling layer (2); S7, forming a first redistribution layer (3) on the exposed surface of the chip (9), and forming a first UBM layer (4) and a conductive structure (5) at different positions of the first redistribution layer (3); S8, hot-pressing and welding the silicon bridge chip (6) on the first UBM layer (4), and filling the NCF film (15) between the silicon bridge chip (6) and the first redistribution layer (3); S9, the second plastic sealing, the plastic sealing height exceeds the height of the conductive structure (5); S10, thinning until one end surface of the conductive structure (5) is exposed; S11, making a second redistribution layer (7) on the thinned surface, and performing UBM processing and ball planting respectively.
6. The packaging method of a multi-chip fan-out packaging structure according to claim 5, characterized in that: In the step S2, a mark required for flip-sticking the chip (9) is formed on the BCB layer (8).
7. The packaging method of a multi-chip fan-out packaging structure according to claim 5, characterized in that: In the step S5, the thickness of the plastic package is greater than the thickness of the chip (9) by 100 μm.
8. The packaging method of a multi-chip fan-out packaging structure according to claim 5, characterized in that: In step S7, the I / O port of the chip (9) is electrically connected to the first redistribution layer (3), and in step S8, the silicon bridge chip (6) is electrically connected to the first redistribution layer (3) through the first UBM layer (4).
9. The packaging method of a multi-chip fan-out packaging structure according to claim 5, characterized in that: In the step S7, the height of the conductive structure (5) is greater than 100 um.
10. The packaging method of a multi-chip fan-out packaging structure according to claim 5, characterized in that: The method further includes step S12, thinning the chip (9) for the second time until the silicon surface is exposed.