Semiconductor assembly

Abstract

The invention discloses a semiconductor assembly which comprises a substrate, a shielding structure and an inductor. The shielding structure is arranged in the substrate and comprises a plurality of conductor filling layers and a plurality of high-dielectric-constant dielectric lining layers. And the plurality of conductor filling layers are arranged in the plurality of grooves of the substrate. And the plurality of high dielectric constant dielectric liners are arranged between the plurality of conductor filling layers and the substrate. The plurality of conductor filling layers are electrically connected with each other and grounded. And the inductor is positioned above the shielding structure.

Description

Technical Field

[0001] The present invention relates to an integrated circuit, and more particularly to a semiconductor component. Background Art

[0002] Inductors are a common passive component. During operation, the magnetic field in the inductor region easily generates eddy currents, which reduce the Q factor and thus affect the inductor's performance. Summary of the Invention

[0003] The present invention provides a semiconductor component which can cut off or reduce eddy current generated by a magnetic field in an inductor region when the inductor is in operation, thereby increasing the Q factor and improving the performance of the inductor.

[0004] In one embodiment of the present invention, a semiconductor device includes a substrate, a shielding structure, and an inductor. The shielding structure is disposed in the substrate and includes multiple conductor filling layers and multiple high-k dielectric liners. The multiple conductor filling layers are located in multiple grooves in the substrate. The multiple high-k dielectric liners are located between the multiple conductor filling layers and the substrate. The multiple conductor filling layers are electrically connected to each other and to ground. The inductor is located above the shielding structure.

[0005] In one embodiment of the present invention, a semiconductor device includes a substrate, a shielding structure, an inductor, and a dielectric layer. The shielding structure is disposed in the substrate. The shielding structure includes multiple high-k dielectric liners disposed in multiple recesses in the substrate, with at least some of the high-k dielectric liners not completely filling the recesses. The inductor is located above the shielding structure. The dielectric layer is located between the inductor and the shielding structure and fills the remaining spaces in the recesses.

[0006] Based on the above, the shielding structure provided under the inductor in the embodiment of the present invention can cut off or reduce the eddy current generated by the magnetic field in the inductor region during operation of the inductor, thereby improving the Q factor and the performance of the inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a three-dimensional diagram of a semiconductor component according to an embodiment of the present invention;

[0008] Figures 1B to 1G is a cross-sectional view of various units of the shielding structure according to an embodiment of the present invention;

[0009] Figure 2A and Figure 2B are a top view and a cross-sectional view of a semiconductor component according to an embodiment of the present invention;

[0010] Figure 3A and Figure 3Bare a top view and a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0011] Figure 4A and Figure 4B are cross-sectional views of semiconductor components according to other embodiments of the present invention;

[0012] Figure 5A and Figure 5B are a top view and a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0013] Figure 6A and Figure 6B are a top view and a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0014] Figure 7A and Figure 7B 1 and 2 are top views and cross-sectional views of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Reference Figure 1A , the semiconductor component of an embodiment of the present invention includes an inductor 50. The inductor 50 can be a spiral inductor. The inductor 50 can be used as a radio frequency inductor. When the inductor 50 is in operation, the magnetic field in the inductor area will generate eddy current (Eddy Current), which will reduce the Q factor. The Q factor is an important parameter that defines the performance of the radio frequency inductor. A decrease in the Q factor will lead to a decrease in the performance of the radio frequency inductor. Therefore, the embodiment of the present invention further provides a shielding structure 30 under the inductor 50 to reduce or cut off the eddy current so that the Q factor is maintained or improved.

[0017] The inductor 50 of the embodiment of the present invention is disposed above the substrate 10. The shielding structure 30 is disposed within the substrate 10. The material of the substrate 10 includes a semiconductor, such as silicon, or a semiconductor compound, such as silicon germanium. The inductor 50 is formed of a conductive material. The inductor 50 can be formed in the process of fabricating the interconnect structure 40 (shown in FIG. Figure 2B 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B) are formed simultaneously. The shielding structure 30 is disposed in the substrate 10. The size of the shielding structure 30 may be greater than or equal to the size of the inductor 50. The shielding structure 30 may be composed of various materials and may have various shapes. For example, the shielding structure 30 may include a high-k dielectric material, a low-k dielectric material, a conductor-filled material, or a combination thereof. A high-k dielectric material includes a dielectric material having a dielectric constant greater than 3.9. A low-k dielectric material includes a dielectric material having a dielectric constant less than 3.9. The conductor-filled material may include undoped polysilicon. Figures 1B to 1G Various units U1 , U2 , U3 , U4 , U5 , and U6 that make up shield structure 30 are shown.

[0018] Reference Figure 1B The unit U1 includes high-k dielectric liners 14 and 16 and a conductor filling layer 20. The high-k dielectric liners 14 and the conductor filling layer 20 are located in the groove 12 of the substrate 10. The high-k dielectric liners 16 cover the substrate 10.

[0019] A high-k dielectric liner 14 is located on the sidewalls and bottom surface of the recess 12 of the substrate 10. The high-k dielectric liner 14 is located between the conductor-filled layer 20 and the substrate 10. The high-k dielectric liner 16 is connected to the dielectric liner 14 to form a continuous layer 18. The continuous layer 18 is located on the sidewalls and bottom surface of the recess 12 of the substrate 10 and extends to cover the top surface of the substrate 10. The conductor-filled layer 20 fills the remaining space in the recess 12. The sidewalls and bottom surface of the conductor-filled layer 20 are covered by the high-k dielectric liner 14. The top surface of the conductor-filled layer 20 can be coplanar with the top surface of the high-k dielectric liner 16.

[0020] The high-k dielectric liner layers 14 and 16 include dielectric materials with a dielectric constant greater than 3.9, such as but not limited to silicon nitride (Si3N4), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf 0.5 Zr 0.5 The conductive fill layer 20 includes a semiconductor material such as undoped polysilicon, doped polysilicon, or a combination thereof.

[0021] In some embodiments, the recess 12 is rectangular, and the width W1 of the recess 12 is, for example, 250 nanometers to 340 nanometers. The depth dp1 of the recess 12 is, for example, 6000 nanometers to 12000 nanometers. The thickness t1 of the high-k dielectric liner 14 and the thickness t2 of the high-k dielectric liner 16 can be the same or different. Thicknesses t1 and t2 can be in the range of 20 nanometers to 50 nanometers, although greater or lesser thicknesses may also be used. The width W2 of the conductive fill layer 20 is, for example, 150 nanometers to 300 nanometers.

[0022] Reference Figure 1C Unit U2 is similar to unit U1. Unit U2 includes a high-k dielectric liner 14 and a conductor fill layer 20, but does not include a high-k dielectric liner 16. The top surface of substrate 10 is not covered by high-k dielectric liner 16. The top surface of conductor fill layer 20 can be coplanar with the top surface of high-k dielectric liner 16 and the top surface of substrate 10. The materials of the high-k dielectric liner 14 and conductor fill layer 20 are as described above and will not be repeated here.

[0023] Reference Figure 1D , unit U3 is similar to unit U1. Unit U3 includes high-dielectric-constant dielectric liners 14 and 16 and a dielectric layer 22. In other words, the dielectric layer 22 of unit U3 replaces the conductor filling layer 20 of unit U1. The high-dielectric-constant dielectric liner 14 and the dielectric layer 22 fill the groove 12 of the substrate 10. The high-dielectric-constant dielectric liner 16 covers the substrate 10. The dielectric layer 22 fills the remaining space of the groove 12. The sidewalls and bottom surface of the dielectric layer 22 are covered by the high-dielectric-constant dielectric liner 14. The top surface of the dielectric layer 22 can be coplanar with the top surfaces of the high-dielectric-constant dielectric liners 14 and 16. In other embodiments, the dielectric layer 22 can also be part of the dielectric layer 32 of the upper interconnect structure 40 (shown in FIG. Figure 4A and Figure 4B ), which portion extends continuously from the top of the substrate 10 to the groove 12, which will be described in detail later.

[0024] The materials and thicknesses of the dielectric constant dielectric liners 14 and 16 are as described in the above embodiments and are not further described here. The dielectric constant of the dielectric layer 22 can be less than or equal to the dielectric constant of the high-k dielectric liner 14. The dielectric layer 22 can be, for example, silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), a low-k material, or a combination thereof. The low-k material includes a dielectric material having a dielectric constant less than or equal to 3.9. Low-k materials include fluorine-doped silicate glass (FSG); silicon sesquioxides such as hydrogen silsesquioxnane (HSQ), methylsilsesquioxane (MSQ), and hybrido-organosiloxane polymers (HOSP); aromatic hydrocarbons such as SiLK; organosilicate glass such as black diamond (BD), 3MS, and 4MS; parylene; fluorinated polymers such as PFCB, CYTOP, and Teflon; poly(arylethers) such as PAE-2 and FLARE; porous polymers such as XLK, Nanofoam, and Awrogel; and Coral. Other suitable low-k dielectric materials are also contemplated by the present disclosure. In some embodiments, the recess 12 is rectangular, and the width W1 of the recess 12 is, for example, 250 nanometers to 340 nanometers. The depth dp1 of the recess 12 is, for example, 6000 nanometers to 12000 nanometers. The thickness t1 of the high-k dielectric liner 14 and the thickness t2 of the high-k dielectric liner 16 can be the same or different. Thicknesses t1 and t2 can be in the range of 20 nanometers to 50 nanometers, although greater or lesser thicknesses may also be used. The width W3 of the dielectric layer 22 is, for example, 150 nanometers to 300 nanometers. The depth dp3 of the recess 12 is, for example, 6000 nanometers to 12000 nanometers.

[0025] Reference Figure 1E , unit U4 is similar to unit U3. Unit U4 includes a high-k dielectric liner 14 and a dielectric layer 22, but does not include a high-k dielectric liner 16. The top surface of substrate 10 is not covered by the high-k dielectric liner 16. The top surface of dielectric layer 22 can be coplanar with the top surface of high-k dielectric liner 16 and the top surface of substrate 10. In other embodiments, dielectric layer 22 can also be part of the dielectric layer of the upper interconnect structure. The materials of the dielectric constant dielectric liner 14 and dielectric layer 22 are as described above and will not be repeated here.

[0026] Reference Figure 1F Unit U5 is similar to unit U3. Unit U5 includes high-k dielectric liners 14 and 16, but does not include dielectric layer 22. Recess 12 of substrate 10 is filled with high-k dielectric liner 14. The materials of dielectric liners 14 and 16 are as described above and are not further described here. In some embodiments, recess 12 is rectangular, and the width W1 of recess 12 is, for example, 250 nanometers to 340 nanometers. The depth dp5 of recess 12 is, for example, 6000 nanometers to 12000 nanometers.

[0027] Reference Figure 1G Unit U6 is similar to unit U5. Unit U6 includes high-k dielectric liner 14, but does not include high-k dielectric liner 16. The top surface of substrate 10 is not covered by high-k dielectric liner 16. The material of high-k dielectric liner 14 is as described above and will not be repeated here.

[0028] The top view of the above units U1, U2, U3, U4, U5, and U6 can have various shapes, such as rectangle (or strip), square, L-shape or a combination thereof, such as Figure 2A 、 Figure 3A 、 Figure 5A 、 Figure 6A and Figure 7A As shown. Figures 1A to 1G , the shielding structure 30 of the embodiment of the present invention can be formed by one of the units U1, U2, U3, U4, U5, U6 or a combination thereof. In other words, the shielding structure 30 can be composed of the same unit, or composed of two or more different units. Therefore, the grooves 12 of the multiple units (U1, U2, U3, U4, U5 and / or U6) constituting the shielding structure 30 can have the same or different shapes. The shape of the groove 12 is, for example, rectangular (or strip-shaped), square, L-shaped or a combination thereof. The grooves 12 can have the same or different lengths, widths or depths. The distance between the grooves 12 can be the same or different. The density of the grooves 12 in different areas can be the same or different. The grooves 12 can completely overlap, partially overlap or not overlap with the inductor 50. Some embodiments are given below for illustration, however, the embodiments of the present invention are not limited thereto.

[0029] Figure 2A 、 Figure 3A 、 Figure 5A 、 Figure 6A and Figure 7A A top view of a semiconductor component including various shielding structures 30 and an inductor 50 is shown. Figure 2B 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5B 、 Figure 6B and Figure 7B A cross-sectional view of a semiconductor component including various shielding structures 30 and an inductor 50 is shown. Figure 2B 、 Figure 3B 、 Figure 5B 、 Figure 6B and Figure 7B They are Figure 2A 、 Figure 3A 、 Figure 5A 、 Figure 6A and Figure 7A Cross-sectional view along line II'.

[0030] Reference Figure 2A and Figure 2B , the inductor 50 is arranged in the interconnect structure 40 above the substrate 10. The inductor 50 can be arranged at the same height as any conductor layer of the interconnect structure 40, such as the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer or a higher conductor layer. The inductor 50 is separated from the substrate 10 by a dielectric layer 32. The dielectric layer 32 can be a single layer or a multi-layer. The shielding structure 30 is arranged in the substrate 10 and covered by the dielectric layer 32. The shielding structure 30 is composed of a plurality of identical units U1 arranged together. The unit U1 (or the groove 12) may partially overlap or not overlap with the inductor 50. The conductor filling layers 20 of the plurality of units U1 can be electrically connected to each other and grounded, such as Figure 2B shown.

[0031] Reference Figure 2A , the unit U1 may include a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 are connected to each other. The top view of the unit U1 composed of the first portion P1 and the second portion P2 is rectangular or oblong (long strip). Figure 2A , the angle θ1 between the first part P1 and the second part P2 of the unit U1 is a right angle (90 degrees), and the top view of the unit U1 is L-shaped. However, the angle θ1 is not limited to this. In other embodiments, the angle θ1 between the first part P1 and the second part P2 may also be an acute angle or an obtuse angle. The multiple units U1 are arranged from the four corners toward the central axis (or center) C1 of the inductor 50. The lengths L1 of the multiple first parts P1 and the lengths L2 of the multiple second parts P2 gradually increase from the four corners toward the central axis C1 of the inductor 50. The multiple units U1 can be arranged into four blocks B1, B2, B3 and B4. The four blocks B1, B2, B3 and B4 can be symmetrical to each other, but are not limited to this.

[0032] Reference Figure 2B, the multiple units U1 have the same depth dp1, but this is not limited to this. In other embodiments, the multiple units U1 may have different depths dp1. For example, the depth dp1 of the unit U1 closer to the central axis C1 of the inductor 50 is deeper, while the depth dp1 of the unit U1 farther from the central axis C1 of the inductor 50 is shallower.

[0033] In this embodiment, the distance d1 between the two grooves 12 of two adjacent units U1 is the same. The distance d1 between the two grooves 12 of two adjacent units U1 in the central region R1 close to the central axis C1 is equal to the distance d1 between the two grooves 12 of two adjacent units U1 in the peripheral region R2 away from the central axis C1. In other words, the density of the grooves 12 in the central region R1 is equal to the density of the grooves 12 in the peripheral region R2. However, the invention is not limited to this.

[0034] Reference Figure 3A and Figure 3B In other embodiments, the two grooves 12 of two adjacent units U1 in the central region R1 have the same distance d1, and the two grooves 12 of two adjacent units U1 in the peripheral region R2 away from the central axis C1 have the same distance d2. The distance d1 and the distance d2 are not equal. The density of the grooves 12 in the central region R1 is not equal to the density of the grooves 12 in the peripheral region R2. In some embodiments, the distance d2 is greater than the distance d1. The distance d2 can be 1.2 times to 5 times the distance d1. In other words, the density of the grooves 12 in the central region R1 is greater than the density of the grooves 12 in the peripheral region R2. The high density of the units U1 in the central region R1 can effectively reduce the eddy currents in the central region R1. The reduced density of the units U1 in the peripheral region R2 can reduce the pattern density and reduce the burden of the process. In addition, in Figure 3A In the embodiment, the number of distances d1 between two adjacent units U1 may be less than or equal to the number of distances d2 between two adjacent units U1.

[0035] exist Figure 2B and Figure 3B In the shield structure 30 shown, the plurality of dielectric liners 16 of the unit U1 can be connected to each other and form a continuous layer 18 with the plurality of dielectric liners 14. The continuous layer 18 separates the dielectric layer 32 from the substrate 10. In other embodiments, the shield structure 30 may not include the plurality of dielectric liners 16, but may be composed of a plurality of units U2 ( Figure 1C ) (not shown), so that the substrate 10 between two adjacent units U2 is in direct contact with the dielectric layer 32.

[0036] Reference Figure 4A, the shielding structure 30 is formed by arranging a plurality of identical units U3. The top view of the groove 12 of the unit U3 can be rectangular or square. When the groove 12 of the unit U3 is rectangular or square, the depth dp3 can be, for example, 6000 nanometers to 12000 nanometers. When the top view of the groove 12 of the unit U3 is square, the width of the square can be, for example, 320 nanometers to 640 nanometers. The wider the width of the square, the deeper the depth dp3 can be. In this embodiment, the dielectric layer 22 of the shielding structure 30 is part of the dielectric layer 32 of the interconnect structure 40. In other words, after the high-k dielectric liner 14 and 16 are formed on the groove 12 and the substrate 10, the deposition process of the dielectric layer 32 of the interconnect structure 40 is performed so that the dielectric layer 32 can be formed above the substrate 10 and filled in the groove 12 to serve as the dielectric layer 22 of the shielding structure 30. Therefore, in this embodiment, there is no interface between the dielectric layers 22 and 32.

[0037] The distance d3 between the two grooves 12 of two adjacent units U3 is the same. In other words, the distance d3 between the two grooves 12 of two adjacent units U3 in the central region R1 close to the central axis C1 is equal to the distance d3 between the two grooves 12 of two adjacent units U3 in the peripheral region R2 away from the central axis C1. However, the invention is not limited to this. In other embodiments, the distance d3 between the two grooves 12 of two adjacent units U3 in the central region R1 is different from the distance d3 between the two grooves 12 of two adjacent units U3 in the peripheral region R2 away from the central axis C1. For example, the distance d3 between the two grooves 12 of two adjacent units U3 in the central region R1 is smaller than the distance d3 between the two grooves 12 of two adjacent units U3 in the peripheral region R2 away from the central axis C1.

[0038] exist Figure 4A In the embodiment, the plurality of units U3 of the shielding structure 30 have the same depth dp3. However, the embodiment of the present invention is not limited thereto. In other examples, referring to Figure 4BShielding structure 30 includes multiple units U3a and U3b. Unit U3a is located in central region R1, and unit U3b is located in peripheral region R2. The top view of recess 12a of unit U3a and recess 12b of unit U3b can be rectangular or square. When recess 12a and recess 12b are square in top view, the width of the square is, for example, 320 nanometers to 640 nanometers. The wider the square, the deeper the depths dp3a and dp3b can be. Recess 12a of unit U3a has the same depth dp3a. Recess 12b of unit U3b has the same depth dp3b. Depth dp3a is greater than depth dp3b. Depth dp3a is 1.2 to 6 times the depth dp3b. When the grooves 12a and 12b are rectangular or square, the depth dp3a can be, for example, 2400 nm to 12000 nm, and the depth dp3b can be, for example, 2000 nm to 9000 nm. A predetermined dielectric constant can be obtained by adjusting the depths dp3a and dp3b of the grooves 12a and 12b.

[0039] In other embodiments, Figure 4A and Figure 4B The shielding structure 30 may also not include multiple dielectric constant dielectric liner 16, and instead be composed of multiple units U4 ( Figure 1D ) (not shown). The substrate 10 between two adjacent units U2 is in direct contact with the dielectric layer 32. The shielding structure 30 of the subsequent embodiment may also not include multiple dielectric constant dielectric liner layers 16, which will not be described one by one hereafter. Figure 4A and Figure 4B The top view of the shielding structure 30 can be compared with Figure 2A or Figure 3A Similarly, or as will be explained later Figure 5A or Figure 6A shown.

[0040] Reference Figure 5A and Figure 5B Shielding structure 30 is composed of cells U3 and U5. Cell U5 is located in central region R1, while cell U3 is located in peripheral region R2. Cell U5 (or its recess 12) in central region R1 does not overlap with inductor 50. Cell U3 (or its recess 12) in peripheral region R2 overlaps, partially overlaps, or does not overlap with inductor 50.

[0041] Reference Figure 5B, the grooves 12 of unit U3 have the same depth dp3 and the same distance d3. The grooves 12 of unit U5 have the same depth dp5 and the same distance d5. In this embodiment, the depth dp3 is equal to the depth dp5, and the distance d3 is equal to the distance d5. However, the embodiment of the present invention is not limited to this. The depth dp3 may be greater than the depth dp5. The distance d5 may be greater than the distance d3. The distance d5' between adjacent units U5 and units U3 may be greater than, equal to, or less than the distance d5 or d3. In other embodiments, in the central region R1, the distance d5a between the units U5 closer to the central axis C1 is different from the distance d5b between the units U5 farther away from the central axis C1, such as Figure 6A shown.

[0042] Reference Figure 5A , the units U3 and U5 of the shielding structure 30 have the same shape, for example, both are square in top view. From the top view, the units U3 and U5 have the same size and area. However, the embodiments of the present invention are not limited thereto. In other embodiments, the units U3 and U5 may also have different sizes and areas (not shown). In other embodiments, the units U3 (U3c and U3d) and U5 may have different shapes, such as Figure 6A shown.

[0043] Reference Figure 6A and Figure 6B , the shielding structure 30 includes units U5 and U3. Unit U5 is arranged in the central region R1, and unit U3 is arranged in the peripheral region R2. Units U5 and U3 have different shapes. The top view of the groove 12 of unit U5 is, for example, square. Unit U3 includes units U3c and U3d. Unit U3c is arranged at a corner. Unit U3d is arranged between two units U3c. The top view of the groove 12c of unit U3c and the top view of the groove 12d of unit U3d have different shapes. In this embodiment, the top view of unit U3c is L-shaped, and the top view of unit U3d is I-shaped. Unit U5 (or its groove 12) does not overlap with the inductor 50. Units U3c and U3d (or their grooves 12) partially overlap or do not overlap with the inductor 50.

[0044] In this embodiment, in the central region R1, the distance d5a between the units U5 closer to the central axis C1 is smaller than the distance d5b between the units U5 farther from the central axis C1. However, the present invention is not limited to this. The units U5 in the central region R1 can have a single distance, or three or more different distances.

[0045] Units U3c may have the same distance d3c. Units U3d may have the same distance d3d. Distance d3c may be equal to, less than, or greater than distance d3d. In other examples, units U3c may have different distances d3c (not shown). Units U3d may have different distances d3d (not shown).

[0046] Reference Figure 7A and Figure 7B The shielding structure 30 includes units U1 and U3. Unit U1 is arranged in the central region R1 and extends to the peripheral region R2, and unit U3 is arranged outside the unit U1. The conductor filling layers 20 of the plurality of units U1 can be electrically connected to each other and can be grounded, as shown in FIG. Figure 7B As shown. Units U1 and U3 have the same shape, for example, both are L-shaped in top view. Figure 7A As shown, the unit U1 (or its groove 12) partially overlaps with the inductor 50. The unit U3 (or its groove 12) partially overlaps with the inductor 50 or does not overlap.

[0047] In this embodiment, the distance d1 between the units U1 is the same, and the distance d3 between the units U3 is the same. Distance d1 may be less than or equal to distance d3. In other examples, the distance d1 between the units U1 may be different, and the distance d3 between the units U3 may be different (not shown). The depth dp1 of the groove 12 of the unit U1 may be equal to or greater than the depth dp3 of the groove 12 of the unit U3.

[0048] In summary, in some embodiments of the present invention, a shielding structure disposed beneath an inductor comprising a dielectric material with a high dielectric constant can block or reduce eddy currents generated by the magnetic field in the inductor region during operation, thereby improving the Q factor and, consequently, the inductor's performance. Furthermore, the shielding structure disposed beneath the inductor comprising a dielectric material with a high dielectric constant can generate a higher capacitance to ground, thereby achieving a lower self-resonant frequency.

[0049] Furthermore, in some other embodiments of the present invention, a shielding structure disposed beneath the inductor comprising a low-dielectric-constant material can block or reduce eddy currents generated by the magnetic field in the inductor region during operation, thereby improving the Q factor and, consequently, the inductor's performance. Furthermore, the shielding structure disposed beneath the inductor of the present invention comprising a low-dielectric-constant dielectric material can produce a lower capacitance to ground, thereby enabling a higher self-resonant frequency.

[0050] In yet other embodiments of the present invention, a shielding structure provided below the inductor with a conductive filling layer can block or reduce eddy currents generated by the magnetic field in the inductor region during operation, thereby improving the Q factor and, consequently, the inductor's performance. Furthermore, the shielding structure provided below the inductor with a conductive filling layer can generate a higher capacitance to ground, thereby achieving a lower self-resonant frequency.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor component, characterized in that include: substrate; A shielding structure, disposed in the substrate, comprising: a plurality of conductor filling layers in the plurality of grooves of the substrate; a plurality of high-k dielectric liners between the plurality of conductor-filled layers and the substrate, wherein the plurality of conductor-filled layers are electrically connected to each other and to ground; and The inductor is located above the shielding structure. 2 . The semiconductor device according to claim 1 , wherein the high-k dielectric liners further extend to cover the surface of the substrate between the grooves to form a continuous layer. The semiconductor component according to claim 1 , wherein the plurality of grooves are equidistant from one another.

4. The semiconductor component according to claim 1 , wherein the plurality of recesses comprises: a plurality of first grooves; as well as A plurality of second grooves are outside the plurality of first grooves, wherein the plurality of first grooves are closer to the center of the inductor than the plurality of second grooves. The semiconductor component according to claim 1 , wherein a second distance between the plurality of second grooves is greater than a first distance between the plurality of first grooves. The semiconductor component according to claim 1 , wherein a density of the plurality of second recesses is smaller than a density of the plurality of first recesses. The semiconductor component according to claim 1 , wherein the plurality of grooves have an L-shape.

8. A semiconductor component, characterized in that: include: substrate; A shielding structure is provided in the substrate, comprising: a plurality of high-k dielectric liners, wherein at least a portion of the plurality of high-k dielectric liners does not fill the plurality of grooves in the substrate; an inductor located above the shielding structure; and The dielectric layer is located between the inductor and the shielding structure and fills the remaining spaces of the grooves. 9 . The semiconductor device according to claim 8 , wherein the high-k dielectric liners further extend to cover the surface of the substrate between the grooves to form a continuous layer. 10 . The semiconductor component according to claim 8 , wherein the plurality of grooves are equidistant from one another. The semiconductor device according to claim 8 , wherein the plurality of grooves are shaped like a square, a rectangle, an L-shape, or a combination thereof.

12. The semiconductor component according to claim 8, wherein the plurality of recesses comprises: a plurality of first grooves; as well as A plurality of second grooves are outside the plurality of first grooves. 13 . The semiconductor component according to claim 12 , wherein the plurality of first grooves do not overlap with the inductor, and the plurality of second grooves overlap with the inductor. The semiconductor component according to claim 12 , wherein a first depth of the plurality of first recesses is greater than a second depth of the plurality of second recesses. The semiconductor device according to claim 12 , wherein the plurality of first recesses and the second recesses comprise different materials. 16 . The semiconductor device according to claim 15 , wherein the first recesses are filled with the high-k dielectric liners, and the second recesses are filled with the high-k dielectric liners and the dielectric layer. The semiconductor component according to claim 16 , wherein the shapes of the plurality of first grooves are the same as the shapes of the plurality of second grooves. The semiconductor component according to claim 16 , wherein shapes of the plurality of first recesses are different from shapes of the plurality of second recesses. 19 . The semiconductor device according to claim 18 , wherein the shapes of the first grooves include squares, and the shapes of the second grooves include strips and L-shapes.

20. The semiconductor device according to claim 15, wherein the plurality of first grooves are filled with the plurality of high-k dielectric liners and a plurality of conductor filling layers, and the plurality of second grooves are filled with the plurality of high-k dielectric liners and the dielectric layer, wherein the plurality of conductor filling layers are electrically connected to each other and to ground.

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