Control circuit of Buck converter, Buck converter and power supply chip

Abstract

The embodiment of the invention provides a control circuit of a Buck converter, the Buck converter and a power supply chip. The control circuit comprises a mode determination module, a main control module and an auxiliary control module, and the mode determination module can determine whether a 100% duty ratio condition is met or not according to the upper tube conduction duration, determine whether a light load condition is met or not according to the upper tube current, determine a mode signal according to a duty ratio detection signal and a load detection signal, and control the main control module according to the mode signal. When the 100% duty ratio condition and the light load condition are met, the main control module controls the upper tube to be switched off according to the mode signal so as to control the Buck converter to enter a Burst mode, and when the 100% duty ratio condition is met and the light load condition is not met, the auxiliary control module controls the upper tube to be switched on so as to control the Buck converter to enter the 100% duty ratio. The control circuit can reduce the power consumption of the Buck converter and improve the stability of the Buck converter.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a control circuit of a Buck converter, a Buck converter, and a power supply chip. Background Art

[0002] In practical applications of Buck converters, as the load consumes the stored energy of the power supply, the power supply voltage gradually decreases. This means that the input voltage of the Buck converter gradually decreases, and the output voltage of the Buck converter decreases as the input voltage decreases. When the output voltage drops close to the input voltage, the Buck converter enters a 100% duty cycle, making the output voltage equal to the input voltage, thereby maintaining normal load operation.

[0003] In a traditional Buck converter control scheme, when the sum of the output voltage and a first voltage threshold is greater than the input voltage, the Buck converter enters a 100% duty cycle. When the input voltage is greater than the sum of the output voltage and a second voltage threshold, the Buck converter exits the 100% duty cycle. However, when the input voltage approaches the output voltage and the Buck converter is lightly loaded, the Buck converter enters a 100% duty cycle, resulting in higher power consumption. Summary of the Invention

[0004] The present disclosure provides a control circuit of a Buck converter, a Buck converter, and a power supply chip, which can reduce the power consumption of the Buck converter and improve the stability of the Buck converter.

[0005] In a first aspect, the present disclosure provides a control circuit for a Buck converter, wherein the Buck converter includes an upper tube and a lower tube, wherein the upper tube is connected in series between a voltage input terminal and ground, and the control circuit includes a mode determination module, a main control module, and an auxiliary control module, wherein the output terminal of the mode determination module is connected to the control terminal of the main control module, the first output terminal of the main control module and the output terminal of the auxiliary control module are connected to the control terminal of the upper tube, and the second output terminal of the main control module is connected to the control terminal of the lower tube.

[0006] The mode determination module is configured to determine a duty cycle detection signal based on the conduction time of the upper tube to determine whether a 100% duty cycle condition is met; determine a load detection signal based on the upper tube current to determine whether a light load condition is met; and determine a mode signal based on the duty cycle detection signal and the load detection signal.

[0007] The main control module is configured to control the high-side transistor to turn off according to the mode signal when the 100% duty cycle condition and the light load condition are met, thereby controlling the Buck converter to enter Burst mode. The auxiliary control module is configured to control the high-side transistor to turn on when the 100% duty cycle condition is met and the light load condition is not met, thereby controlling the Buck converter to enter 100% duty cycle.

[0008] In some embodiments of the present disclosure, the mode determination module includes a duty cycle detection unit, a load detection unit and a logic unit, the input end of the duty cycle detection unit is connected to the control end of the upper tube, the output end of the duty cycle detection unit is connected to the first input end of the logic unit, the first input end of the load detection unit is connected to the voltage input end, the second input end of the load detection unit is connected to the switch node, the output end of the load detection unit is connected to the second input end of the logic unit, and the output end of the logic unit is connected to the control end of the main control module; wherein the switch node is the connection point between the upper tube and the lower tube.

[0009] The duty cycle detection unit is configured to determine that the duty cycle detection signal is a second level signal when the upper tube conduction duration is greater than a first preset duration, and to determine that the duty cycle detection signal is a first level signal when the upper tube conduction duration is not greater than the first preset duration. The load detection unit is configured to determine that the load detection signal is a second level signal when the upper tube current is less than a preset current, and to determine that the load detection signal is a first level signal when the upper tube current is not less than the preset current.

[0010] The logic unit is configured to determine that the mode signal is a Burst mode signal when the duty cycle detection signal and the load detection signal are second level signals, and to determine that the mode signal is a non-Burst mode signal when the duty cycle detection signal is the second level signal and the load detection signal is the first level signal.

[0011] In some embodiments of the present disclosure, the logic unit includes a first AND gate, a second AND gate and a first RS trigger, the first input end of the first AND gate is connected to the output end of the duty cycle detection unit, the second input end of the first AND gate is connected to the output end of the load detection unit, the output end of the first AND gate is connected to the input end of the first RS trigger, the first input end of the second AND gate is connected to the third output end of the main control module, the second input end of the second AND gate is connected to the output end of the first RS trigger, and the output end of the second AND gate is connected to the reset end of the first RS trigger.

[0012] The logic unit is further configured to, when the Buck converter is in the Burst mode, determine whether to exit the Burst mode according to the error amplified signal.

[0013] In some embodiments of the present disclosure, the duty cycle detection unit includes a first inverter, a third AND gate and a first delay device, the input end of the first inverter is connected to the reset end of the first RS trigger, the output end of the first inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the control end of the upper tube, and the output end of the third AND gate is connected to the first input end of the logic unit through the first delay device.

[0014] In some embodiments of the present disclosure, the load detection unit includes a first comparator and a voltage source, the non-inverting input terminal of the first comparator is connected to the switch node through the voltage source, the inverting input terminal of the first comparator is connected to the voltage input terminal, and the power supply terminal of the first comparator is connected to the control terminal of the upper tube.

[0015] In some embodiments of the present disclosure, the mode determination module further includes a lower tube detection unit, the input end of the lower tube detection unit is connected to the fourth output end of the main control module, and the output end of the lower tube detection unit is connected to the third input end of the logic unit.

[0016] The lower tube detection unit is configured to determine a lower tube detection signal based on whether the duration of the upper tube control signal being an off control signal is greater than a second preset duration, and the second preset duration is less than the first preset duration. The logic unit is further configured to determine a mode signal based on the lower tube detection signal when the duty cycle detection signal is a first level signal.

[0017] In some embodiments of the present disclosure, the logic unit also includes a first OR gate, the first input end of the first OR gate is connected to the output end of the first AND gate, the second input end of the first OR gate is connected to the output end of the lower tube detection unit, and the output end of the first OR gate is connected to the input end of the first RS trigger.

[0018] The logic unit is further configured to, when the duty cycle detection signal is a first level signal and the lower tube detection signal is a second level signal, determine that the mode signal is a Burst mode signal; and when the duty cycle detection signal and the lower tube detection signal are first level signals, determine that the mode signal is a non-Burst mode signal.

[0019] In some embodiments of the present disclosure, the lower tube detection unit includes a second inverter, a fourth AND gate and a second delay device, the input end of the second inverter is connected to the reset end of the first RS trigger, the output end of the second inverter is connected to the first input end of the fourth AND gate, the second input end of the fourth AND gate is connected to the fourth output end of the main control module, and the output end of the fourth AND gate is connected to the third input end of the logic unit through the second delay device.

[0020] In some embodiments of the present disclosure, the main control module includes a feedback unit, a control unit and a driving unit, the first input end of the feedback unit is connected to the reference voltage, the second input end of the feedback unit is connected to the voltage output end, the output end of the feedback unit is connected to the first input end of the control unit, the second input end of the control unit is connected to the switching node, the first output end of the control unit is connected to the first input end of the driving unit, the second output end of the control unit is connected to the second input end of the driving unit, the first output end of the driving unit is connected to the control end of the upper tube and the output end of the auxiliary control module, the second output end of the driving unit is connected to the control end of the lower tube, and the control end of the feedback unit and the control end of the control unit are connected to the output end of the mode determination module.

[0021] The feedback unit is configured to determine an error amplification signal based on a reference voltage and a first feedback voltage; when the mode signal is a non-Burst mode signal, determine a feedback signal based on the error amplification signal and a second feedback voltage; wherein the sum of the first feedback voltage and the first preset voltage is equal to the output voltage, and the second feedback voltage is the product of the output voltage and a coefficient less than 1.

[0022] The control unit is configured to, when the mode signal is a Burst mode signal, pull down the upper tube control signal to control the driving unit to drive the upper tube to turn off; when the mode signal is a non-Burst mode signal, determine the upper tube control signal and the lower tube control signal according to the fixed-frequency pulse signal, the feedback signal and the switch node voltage to control the driving unit to drive the upper tube and the lower tube to turn on and off.

[0023] In some embodiments of the present disclosure, the feedback unit includes a first resistor, a first current source and an error amplifier, the voltage output end is connected to the inverting input end of the error amplifier and the input end of the first current source through the first resistor, the reference voltage is connected to the non-inverting input end of the error amplifier, and the output end of the first current source is grounded; wherein, the product of the current provided by the first current source and the resistance value of the first resistor is a first preset voltage.

[0024] In some embodiments of the present disclosure, the feedback unit also includes a second resistor and a second current source, the reference voltage is connected to the positive input terminal of the error amplifier and the input terminal of the second current source through the second resistor, the output terminal of the second current source is grounded, and the control terminal of the second current source is connected to the output terminal of the mode determination module.

[0025] The error amplifier is configured to, when the mode signal is a non-burst mode signal, determine an error amplified signal between a reference voltage and a first feedback voltage; and when the mode signal is a burst mode signal, compare a target reference voltage with the first feedback voltage to obtain the error amplified signal. The sum of the target reference voltage and a second preset voltage is equal to the reference voltage, the product of the current provided by the second current source and the resistance of the second resistor is the second preset voltage, and the second preset voltage is greater than the first preset voltage.

[0026] In some embodiments of the present disclosure, the feedback unit also includes a control switch, a capacitor and a second comparator, the control switch is connected between the output end of the error amplifier and the positive input end of the second comparator, the capacitor is connected between the positive input end of the second comparator and the ground, the inverting input end of the second comparator receives the second feedback voltage, the output end of the second comparator is connected to the first input end of the control unit, and the power supply end of the second comparator and the control end of the control switch are connected to the output end of the mode determination module.

[0027] When the mode signal is a Burst mode signal, the second comparator is turned on and the control switch is turned on; when the mode signal is a non-Burst mode signal, the second comparator is turned off and the control switch is turned off.

[0028] In some embodiments of the present disclosure, the control unit includes an upper tube control subunit and a lower tube control subunit, the control end of the upper tube control subunit is connected to the output end of the mode determination module, the input end of the upper tube control subunit is connected to the output end of the feedback unit, the output end of the upper tube control subunit is connected to the first input end of the driving unit and the first input end of the lower tube control subunit, the second input end of the lower tube control subunit is connected to the switch node, and the output end of the lower tube control subunit is connected to the second input end of the driving unit.

[0029] The upper tube control subunit is configured to determine the fixed-frequency pulse signal according to the input voltage and the output voltage when the upper tube is turned on; determine the upper tube control signal according to the fixed-frequency pulse signal and the feedback signal when the mode signal is a non-Burst mode signal; and pull down the upper tube control signal when the mode signal is a Burst mode signal.

[0030] The lower tube control subunit is configured to determine the lower tube control signal according to the upper tube control signal and the switch node voltage.

[0031] In some embodiments of the present disclosure, the upper tube control subunit includes a timer, a third inverter, a fifth AND gate, a sixth AND gate, a second OR gate, a third OR gate and a second RS trigger, the input end of the third inverter is connected to the first input end of the second OR gate and the output end of the feedback unit, the output end of the third inverter is connected to the first input end of the fifth AND gate, the second input end of the second OR gate is connected to the output end of the load detection unit, the output end of the second OR gate is connected to the first input end of the sixth AND gate, the second input end of the sixth AND gate receives the inverted signal of the mode signal, and the output end of the sixth AND gate is connected to the input end of the second RS trigger.

[0032] The second input end of the fifth AND gate is connected to the output end of the timer, the output end of the fifth AND gate is connected to the first input end of the third OR gate, the second input end of the third OR gate receives the mode signal, the output end of the third OR gate is connected to the reset end of the second RS trigger, the output end of the second RS trigger is connected to the first input end of the driving unit and the first input end of the lower tube control subunit, the first input end of the timer is connected to the voltage input end, the second input end of the timer is connected to the voltage output end, and the control end of the timer is connected to the control end of the upper tube.

[0033] The upper tube control subunit is further configured to, when the mode signal is a non-Burst mode signal, pull down the upper tube control signal when the fixed-frequency pulse signal is a second level signal and the feedback signal is a first level signal.

[0034] In some embodiments of the present disclosure, the lower tube control subunit includes a third comparator, a fourth inverter and a third RS trigger, the input end of the fourth inverter is connected to the output end of the upper tube control subunit, the output end of the fourth inverter is connected to the power supply end of the third comparator and the input end of the third RS trigger, the positive input end of the third comparator is connected to the switch node, the inverting input end of the third comparator is grounded, the output end of the third comparator is connected to the reset end of the third RS trigger, and the output end of the third RS trigger is connected to the second input end of the driving unit.

[0035] The lower tube control subunit is further configured to pull down the lower tube control signal when the switch node voltage is greater than zero and the upper tube control signal is a first level signal.

[0036] In some embodiments of the present disclosure, the auxiliary control module includes a boost charge pump, the input end of the boost charge pump is connected to the voltage input end, and the output end of the boost charge pump is connected to the control end of the upper tube.

[0037] The boost charge pump is configured to boost the input voltage and output the boosted voltage when the duty cycle detection signal and the load detection signal are second level signals, so as to increase the control voltage of the upper tube.

[0038] In a second aspect, the present disclosure provides a Buck converter, comprising any control circuit provided in the first aspect.

[0039] In a third aspect, the present disclosure provides a power supply chip, comprising any control circuit provided in the first aspect.

[0040] The technical solution disclosed herein provides a control circuit for a Buck converter, including a mode determination module, a main control module, and an auxiliary control module. The mode determination module can determine a duty cycle detection signal based on the conduction time of an upper tube to determine whether a 100% duty cycle condition is met, and determine a load detection signal based on the upper tube current to determine whether a light load condition is met. A mode signal is determined based on the duty cycle detection signal and the load detection signal. When the 100% duty cycle condition and the light load condition are met, the main control module can control the upper tube to be turned off based on the mode signal to control the Buck converter to enter a Burst mode, thereby reducing the power consumption of the Buck converter. When the 100% duty cycle condition is met and the light load condition is not met, the auxiliary control module can control the upper tube to be turned on to control the Buck converter to enter a 100% duty cycle. The Buck converter can enter the Burst mode before entering and after exiting the 100% duty cycle, thereby achieving a slow change in the output voltage when entering and exiting the 100% duty cycle, thereby improving the stability of the Buck converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] Figure 1 Schematic diagram of the output voltage of a Buck converter in the prior art varying with the input voltage.

[0043] Figure 2 A schematic diagram of the structure of a Buck converter provided in an embodiment of the present disclosure.

[0044] Figure 3 A schematic structural diagram of a control circuit provided in an embodiment of the present disclosure.

[0045] Figure 4 A schematic structural diagram of another control circuit provided in an embodiment of the present disclosure.

[0046] Figure 5 A circuit diagram of a mode determination module provided in an embodiment of the present disclosure.

[0047] Figure 6 A circuit diagram of a main control module provided in an embodiment of the present disclosure.

[0048] Figure 7 A circuit diagram of another main control module provided in an embodiment of the present disclosure.

[0049] Figure 8This is a timing diagram of the operation of the Burst mode in a 100% duty cycle scenario provided by an embodiment of the present disclosure.

[0050] Figure 9 A circuit diagram of another mode determination module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0053] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0054] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0055] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0056] In the description of the present disclosure, unless otherwise specified, the meanings of "multiple" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0057] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0058] Figure 1 It is a schematic diagram of the output voltage of a Buck converter in the prior art changing with the input voltage. As Figure 1 shown, when the sum of the output voltage Vout and the first voltage threshold Vth1 is greater than the input voltage Vin, that is, Vin < Vout + Vth1, the Buck converter enters a 100% duty cycle, and the output voltage Vout follows the input voltage Vin. When the input voltage Vin is greater than the sum of the output voltage Vout and the second voltage threshold Vth2, that is, Vin > Vout + Vth2, the Buck converter exits the 100% duty cycle. When the output voltage Vout is close to the input voltage Vin, the Buck converter satisfies the 100% duty cycle condition, and the Buck converter enters the 100% duty cycle. At this time, if the Buck converter is lightly loaded, it will cause a relatively large power consumption of the Buck converter.

[0059] To solve the above technical problems, the present disclosure provides a control circuit for a Buck converter, including a mode determination module, a main control module, and an auxiliary control module. The mode determination module can determine a duty cycle detection signal according to the conduction duration of the upper switch to determine whether the 100% duty cycle condition is satisfied, determine a load detection signal according to the upper switch current to determine whether the light load condition is satisfied, and determine a mode signal according to the duty cycle detection signal and the load detection signal. When the 100% duty cycle condition and the light load condition are satisfied, the main control module can control the upper switch to turn off according to the mode signal to control the Buck converter to enter the Burst mode, which can reduce the power consumption of the Buck converter. When the 100% duty cycle condition is satisfied and the light load condition is not satisfied, the auxiliary control module can control the upper switch to conduct to control the Buck converter to enter the 100% duty cycle, and the Buck converter can enter the Burst mode before entering the 100% duty cycle and after exiting the 100% duty cycle, realizing a slow change in the output voltage when entering and exiting the 100% duty cycle, thereby improving the stability of the Buck converter.

[0060] The technical solutions provided by the present disclosure will be described in detail below with several specific embodiments.

[0061] Figure 2 It is a schematic structural diagram of a Buck converter provided by an embodiment of the present disclosure. As Figure 2As shown, the Buck converter 10 includes a high-side transistor HS, a low-side transistor LS, an inductor L, and an output capacitor Cout. The high-side transistor HS and the low-side transistor LS are connected in series between the voltage input terminal IN of the Buck converter 10 and ground. The connection point between the high-side transistor HS and the low-side transistor LS is a switching node SW. The switching node SW is connected to the voltage output terminal OUT of the Buck converter 10 through the inductor L. The output capacitor Cout is connected between the voltage output terminal OUT and ground.

[0062] Buck converter 10 also includes a control circuit 100. A first output terminal of control circuit 100 is connected to the control terminal of high-side switch HS. Control circuit 100 generates a high-side switch control signal Ctr_HS and controls the on / off state of high-side switch HS based on the high-side switch control signal Ctr_HS. A second output terminal of control circuit 100 is connected to the control terminal of low-side switch LS. Control circuit 100 generates a low-side switch control signal Ctr_LS and controls the on / off state of low-side switch LS based on the low-side switch control signal Ctr_LS.

[0063] For example, the high-side transistor HS can be an NMOS transistor. When the high-side transistor control signal Ctr_HS is a high-level signal, the control circuit 100 controls the high-side transistor HS to be turned on. When the high-side transistor control signal Ctr_HS is a low-level signal, the control circuit 100 controls the high-side transistor HS to be turned off. Alternatively, the high-side transistor HS can be a PMOS transistor. When the high-side transistor control signal Ctr_HS is a low-level signal, the control circuit 100 controls the high-side transistor HS to be turned on. When the high-side transistor control signal Ctr_HS is a high-level signal, the control circuit 100 controls the high-side transistor HS to be turned off.

[0064] The lower tube LS can be an NMOS transistor. When the lower tube control signal Ctr_LS is a high-level signal, the control circuit 100 controls the lower tube LS to be turned on. When the lower tube control signal Ctr_LS is a low-level signal, the control circuit 100 controls the lower tube LS to be turned off. Alternatively, the lower tube LS can be a PMOS transistor. When the lower tube control signal Ctr_LS is a low-level signal, the control circuit 100 controls the lower tube LS to be turned on. When the lower tube control signal Ctr_LS is a high-level signal, the control circuit 100 controls the lower tube LS to be turned off.

[0065] Figure 3 A schematic diagram of a control circuit according to an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the control circuit 100 includes a mode determination module 110, a main control module 120 and an auxiliary control module 130, wherein the output end of the mode determination module 110 is connected to the control end of the main control module 120, the first output end of the main control module 120 and the output end of the auxiliary control module 130 are connected to the control end of the upper tube HS, and the second output end of the main control module 120 is connected to the control end of the lower tube LS.

[0066] The mode determination module 110 is configured to determine the duty cycle detection signal Det_duty according to the high-side tube conduction duration Ton_HS to determine whether the 100% duty cycle condition is met, determine the load detection signal Det_load according to the high-side tube current I_HS to determine whether the light load condition is met, and determine the mode signal Mode according to the duty cycle detection signal Det_duty and the load detection signal Det_load.

[0067] The main control module 120 is configured to, when both the 100% duty cycle condition and the light load condition are met, control the high-side transistor HS to be turned off according to the mode signal Mode, thereby controlling the Buck converter 10 to enter the Burst mode. The auxiliary control module 130 is configured to, when both the 100% duty cycle condition and the light load condition are met, control the high-side transistor HS to be turned on, thereby controlling the Buck converter 10 to enter the 100% duty cycle condition.

[0068] For example, Figure 4 A structural diagram of another control circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the mode determination module 110 includes a duty cycle detection unit 111 , a load detection unit 112 and a logic unit 113 .

[0069] Among them, the input end of the duty cycle detection unit 111 is connected to the control end of the upper tube HS, the output end of the duty cycle detection unit 111 is connected to the first input end of the logic unit 113, the first input end of the load detection unit 112 is connected to the voltage input end IN, the second input end of the load detection unit 112 is connected to the switch node SW, the output end of the load detection unit 112 is connected to the second input end of the logic unit 113, and the output end of the logic unit 133 is connected to the control end of the main control module 110.

[0070] Figure 5 A circuit diagram of a mode determination module provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the logic unit 113 includes a first AND gate AND1, a second AND gate AND2 and a first RS flip-flop FF1, a first input end of the first AND gate AND1 is connected to the output end of the duty cycle detection unit 111, a second input end of the first AND gate AND1 is connected to the output end of the load detection unit 112, an output end of the first AND gate AND1 is connected to the input end S of the first RS flip-flop FF1, a first input end of the second AND gate AND2 is connected to the third output end of the main control module 120, a second input end of the second AND gate AND2 is connected to the output end Q of the first RS flip-flop FF1, and an output end of the second AND gate AND2 is connected to the reset end R of the first RS flip-flop FF1.

[0071] The first AND gate AND1 can receive the load detection signal Det_load output by the load detection unit 112, wherein the load detection signal Det_load is used to indicate whether the Buck converter 10 meets the light load condition. When the load detection signal Det_load is a first level signal, it indicates that the Buck converter 10 does not meet the light load condition. When the load detection signal Det_load is a second level signal, it indicates that the Buck converter 10 meets the light load condition.

[0072] The first AND gate AND1 can receive the duty cycle detection signal Det_duty output by the duty cycle detection unit 111, wherein the duty cycle detection signal Det_duty is used to indicate whether the Buck converter 10 meets the 100% duty cycle condition. When the duty cycle detection signal Det_duty is a first level signal, it indicates that the Buck converter 10 does not meet the 100% duty cycle condition. When the duty cycle detection signal Det_duty is a second level signal, it indicates that the Buck converter 10 meets the 100% duty cycle condition.

[0073] Among them, the first level signal can be a low level signal, and the second level signal can be a high level signal, or the first level signal can be a high level signal, and the second level signal can be a low level signal. The embodiment of the present disclosure is only illustratively described by taking the first level signal as a low level signal and the second level signal as a high level signal as an example.

[0074] The first AND gate AND1 performs an AND operation on the load detection signal Det_load and the duty cycle detection signal Det_duty to obtain an AND operation result. When the duty cycle detection signal Det_duty and the load detection signal Det_load are high-level signals, the AND operation result is a high-level signal; when the load detection signal Det_load is low-level signal, the AND operation result is a low-level signal; when the duty cycle detection signal Det_duty is low-level signal, the AND operation result is a low-level signal.

[0075] The AND operation result of the load detection signal Det_load and the duty cycle detection signal Det_duty is the input signal of the first RS trigger FF1. When the input signal of the first RS trigger FF1 is a high-level signal, the mode signal Mode output by the first RS trigger FF1 is a high-level signal, that is, a Burst mode signal. When the input signal of the first RS trigger FF1 is a low-level signal, the mode signal Mode is a low-level signal, that is, a non-Burst mode signal.

[0076] In this way, when the duty cycle detection signal Det_duty and the load detection signal Det_load are second level signals, the logic unit 113 determines that the mode signal Mode is a Burst mode signal; when the duty cycle detection signal Det_duty is a second level signal and the load detection signal Det_load is a first level signal, the logic unit 113 determines that the mode signal Mode is a non-Burst mode signal.

[0077] The second AND gate AND2 can receive the error amplification signal Veao and the mode signal Mode, and perform an AND operation on the error amplification signal Veao and the mode signal Mode to obtain a reset signal RST of the first RS flip-flop FF1. When the mode signal Mode is a high-level signal, the reset signal RST depends on the error amplification signal Veao.

[0078] When the Buck converter 10 is in the Burst mode, the mode signal Mode is a high-level signal. If the error amplification signal Veao is a high-level signal, the reset signal RST is a high-level signal, and the mode signal Mode is a low-level signal, the Buck converter 10 exits the Burst mode. If the error amplification signal Veao is a low-level signal, the reset signal RST is a low-level signal, the mode signal Mode is still a Burst mode signal, and the Buck converter 10 remains in the Burst mode.

[0079] In this way, when the Buck converter 10 is in the Burst mode, the logic unit 113 can determine whether to exit the Burst mode according to the error amplification signal Veao. That is, regardless of whether the Buck converter 10 meets the 100% duty cycle condition, it can be determined whether the Buck converter 10 in the Burst mode exits the Burst mode.

[0080] For example, see Figure 5 The duty cycle detection unit 111 includes a first inverter INV1, a third AND gate AND3 and a first delay device Dly1. The input end of the first inverter INV1 is connected to the reset end R of the first RS flip-flop FF1, the output end of the first inverter INV1 is connected to the first input end of the third AND gate AND3, the second input end of the third AND gate AND3 is connected to the control end of the high tube HS, and the output end of the third AND gate AND3 is connected to the first input end of the logic unit 113 through the first delay device Dly1.

[0081] The third AND gate AND3 can receive the on-state signal HS_on of the high-side transistor HS. The on-state signal HS_on is the voltage signal at the control terminal of the high-side transistor HS when the high-side transistor HS is on. The duration of the on-state signal HS_on is the high-side transistor on-state duration Ton_HS. The third AND gate AND3 can also receive the inverted signal of the reset signal RST. When the reset signal RST is at a low level, the third AND gate AND3 inputs the on-state signal HS_on to the first delay device Dly1.

[0082] The first delay device Dly1 is configured with a first preset duration Tpre1 (e.g., Tpre1 = 60 μs). The first delay device Dly1 determines whether the high-side transistor on-time duration Ton_HS is greater than the first preset duration Tpre1. Based on this, the duty cycle detection signal Det_duty is determined. When the high-side transistor on-time duration Ton_HS is greater than the first preset duration Tpre1, the duty cycle detection signal Det_duty is high. When the high-side transistor on-time duration Ton_HS is less than the first preset duration Tpre1, the duty cycle detection signal Det_duty is low.

[0083] In this way, when the upper tube conduction duration Ton_HS is greater than the first preset duration Tpre1, the duty cycle detection unit 111 determines that the duty cycle detection signal Det_duty is a second level signal; when the upper tube conduction duration Ton_HS is not greater than the first preset duration Tpre1, the duty cycle detection unit 111 determines that the duty cycle detection signal Det_duty is a first level signal.

[0084] For example, see Figure 5 The load detection unit 112 includes a first comparator CMP1 and a voltage source VOS. The non-inverting input terminal of the first comparator CMP1 is connected to the switch node SW through the voltage source VOS, the inverting input terminal of the first comparator CMP1 is connected to the voltage input terminal IN, and the power supply terminal of the first comparator CMP1 is connected to the control terminal of the high tube HS.

[0085] The inverting input voltage of the first comparator CMP1 is the input voltage Vin, and the non-inverting input voltage of the first comparator CMP1 is the sum of the switching node voltage Vsw and the voltage Vos provided by the voltage source VOS, that is, Vsw+Vos, and the switching node voltage Vsw=Vin-Ron_HS*I_HS, where Ron_HS is the on-resistance of the high-side transistor HS.

[0086] When the conduction signal HS_on of the high-side transistor HS is received, the first comparator CMP1 is enabled. The first comparator CMP1 can compare the input voltage Vin and Vsw + Vos. When Vin < Vsw + Vos, then Vin < Vin - Ron_HS * I_HS + Vos, that is, I_HS < Vos / Ron_HS, and a high-level signal is output. When Vin ≥ Vsw + Vos, then Vin ≥ Vin - Ron_HS * I_HS + Vos, that is, I_HS ≥ Vos / Ron_HS, and a low-level signal is output.

[0087] Regarding Vos / Ron_HS as a preset current Ipre. For example, Ipre = Vos / Ron_HS = 50 mA. Then the first comparator CMP1 can compare the high-side transistor current I_HS and the preset current Ipre to obtain the load detection signal Det_load. When the high-side transistor current I_HS is less than the preset current Ipre, the load detection signal Det_load is a high-level signal. When the high-side transistor current I_HS is not less than the preset current Ipre, the load detection signal Det_load is a low-level signal.

[0088] In this way, when the high-side transistor current I_HS is less than the preset current Ipre, the load detection unit 112 determines that the load detection signal Det_load is a second-level signal. When the high-side transistor current I_HS is not less than the preset current Ipre, the load detection unit 112 determines that the load detection signal Det_load is a first-level signal.

[0089] Exemplarily, continue to refer to Figure 4 As shown, the main control module 120 includes a feedback unit 121, a control unit 122, and a driving unit 123.

[0090] Among them, the first input terminal of the feedback unit 121 is connected to the reference voltage Vref, the second input terminal of the feedback unit 121 is connected to the voltage output terminal OUT, the output terminal of the feedback unit 121 is connected to the first input terminal of the control unit 122, the second input terminal of the control unit 122 is connected to the switch node SW, the first output terminal of the control unit 122 is connected to the first input terminal of the driving unit 123, the second output terminal of the control unit 122 is connected to the second input terminal of the driving unit 123, the first output terminal of the driving unit 123 is connected to the control terminal of the high-side transistor HS and the output terminal of the auxiliary control module 110, the second output terminal of the driving unit 123 is connected to the control terminal of the low-side transistor LS, and the control terminals of the feedback unit 121 and the control unit 122 are connected to the output terminal of the mode determination module 110.

[0091] Figure 6 A circuit schematic diagram of a main control module provided by an embodiment of the present disclosure, as Figure 6As shown, the feedback unit 121 includes a first resistor R1, a first current source IB1 and an error amplifier EA, the voltage output terminal OUT is connected to the inverting input terminal of the error amplifier EA and the input terminal of the first current source IB1 through the first resistor R1, the reference voltage Vref is connected to the non-inverting input terminal of the error amplifier EA, and the output terminal of the first current source IB1 is grounded.

[0092] The first resistor R1 and the first current source IB1 form a first voltage divider structure. The product of the resistance R1 of the first resistor R1 and the current Ib1 provided by the first current source IB1 is a first preset voltage Vpre1, i.e., Ib1*R1=Vpre1. For example, if Ib1=10nA and R1=1MΩ, then Vpre1=10mV. After the output voltage Vout passes through the first voltage divider structure, a first feedback voltage Vfb1 is generated. The sum of the first feedback voltage Vfb1 and the first preset voltage Vpre1 ​​equals the output voltage Vout, i.e., Vfb1=Vout-Vpre1. The first feedback voltage Vfb1 serves as the inverting input voltage of the error amplifier EA.

[0093] The non-inverting input voltage of the error amplifier EA is the reference voltage Vref. The error amplifier EA can determine the error amplified signal Veao between the first feedback voltage Vfb1 and the reference voltage Vref. Therefore, the feedback unit 121 can determine the error amplified signal Veao according to the reference voltage Vref and the first feedback voltage Vfb1.

[0094] For example, see Figure 6 The feedback unit 121 further includes a control switch K, a capacitor C, and a second comparator CMP2. The control switch K is connected between the output of the error amplifier EA and the non-inverting input of the second comparator CMP2. The capacitor C is connected between the non-inverting input of the second comparator CMP2 and ground. The inverting input of the second comparator CMP2 receives the second feedback voltage Vfb2. The output of the second comparator CMP2 is connected to the first input of the control unit 122. The power supply of the second comparator CMP2 and the control terminal of the control switch K are connected to the output of the mode determination module 110.

[0095] The inverting input voltage of the second comparator CMP2 is the second feedback voltage Vfb2 , which is the product of the output voltage Vout and a coefficient less than 1, ie, Vfb2 = a*Vout and a<1. For example, if a=0.5, then Vfb2 = 0.5*Vout.

[0096] When the mode signal Mode is a high-level signal, the control switch K is turned off and the second comparator CMP2 is turned off. When the mode signal Mode is a low-level signal, the control switch K is turned on and the second comparator CMP2 is turned on. The non-inverting input terminal of the second comparator CMP2 can receive the error amplification signal Veao and compare the voltage of the error amplification signal Veao with the second feedback voltage Vfb2 to generate the feedback signal FB.

[0097] When the voltage of the error amplified signal Veao is greater than the second feedback voltage Vfb2 , the feedback signal FB is a high level signal. When the voltage of the error amplified signal Veao is not greater than the second feedback voltage Vfb2 , the feedback signal FB is a low level signal.

[0098] In this way, when the mode signal Mode is a non-Burst mode signal, the second comparator CMP2 is turned on, and the feedback unit 121 can determine the feedback signal FB according to the error amplification signal Veao and the second feedback voltage Vfb2. When the mode signal Mode is a Burst mode signal, the second comparator CMP2 is turned off, which can reduce the power consumption of the Buck converter in Burst mode.

[0099] Continue to see Figure 6 The control unit 122 includes an upper tube control subunit 1221 and a lower tube control subunit 1222. The control end of the upper tube control subunit 1221 is connected to the output end of the mode determination module 110, the input end of the upper tube control subunit 1221 is connected to the output end of the feedback unit 121, the output end of the upper tube control subunit 1221 is connected to the first input end of the driving unit 123 and the first input end of the lower tube control subunit 1222, the second input end of the lower tube control subunit 1222 is connected to the switch node SW, and the output end of the lower tube control subunit 1222 is connected to the second input end of the driving unit 123.

[0100] For example, Figure 6 As shown, the upper tube control subunit 1221 includes a timer Timer, a third inverter INV3, a fifth AND gate AND5, a sixth AND gate AND6, a second OR gate OR2, a third OR gate OR3 and a second RS flip-flop FF2.

[0101] Among them, the input end of the third inverter INV3 is connected to the first input end of the second OR gate OR2 and the output end of the feedback unit 121, the output end of the third inverter INV3 is connected to the first input end of the fifth AND gate AND5, the second input end of the second OR gate OR2 is connected to the output end of the load detection unit 112, the output end of the second OR gate OR2 is connected to the first input end of the sixth AND gate AND6, the second input end of the sixth AND gate AND6 receives the inverted signal of the mode signal Mode, and the output end of the sixth AND gate AND6 is connected to the input end S of the second RS flip-flop FF2.

[0102] A second input terminal of the fifth AND gate AND5 is connected to an output terminal of the timer Timer, an output terminal of the fifth AND gate AND5 is connected to a first input terminal of the third OR gate OR3, a second input terminal of the third OR gate OR3 receives a mode signal Mode, an output terminal of the third OR gate OR3 is connected to a reset terminal R of the second RS flip-flop FF2, an output terminal Q of the second RS flip-flop FF2 is connected to a first input terminal of the driving unit 123 and a first input terminal of the lower tube control unit 1221, a first input terminal of the timer Timer is connected to a voltage input terminal IN, a second input terminal of the timer Timer is connected to a voltage output terminal OUT, and a control terminal of the timer Timer is connected to a control terminal of the upper tube HS.

[0103] When receiving the on-signal HS_on from the high-side switch HS, the timer Timer is enabled. The timer Timer can determine the fixed-frequency pulse signal On_timer based on the input voltage Vin and the output voltage Vout, and input the fixed-frequency pulse signal On_timer to the fifth AND gate AND5. The third inverter INV3 can invert the feedback signal FB to obtain an inverted signal of the feedback signal FB, and input the inverted signal of the feedback signal FB to the fifth AND gate AND5.

[0104] In this way, when the high-side switch HS is turned on, the high-side switch control subunit 1221 can determine the fixed-frequency pulse signal On_timer according to the input voltage Vin and the output voltage Vout.

[0105] The fifth AND gate AND5 can perform an AND operation on the inverted signal of the feedback signal FB and the fixed-frequency pulse signal On_timer, and input the AND operation result to the third OR gate OR3. The third OR gate OR3 can then perform an OR operation on the mode signal Mode and the AND operation result to obtain a reset signal for the second RS flip-flop FF2.

[0106] After the second OR gate OR2 performs an OR operation on the feedback signal FB and the load detection signal Det_load, the OR operation result is input to the sixth AND gate AND6. The sixth AND gate AND6 can then perform an AND operation on the inverted signal of the mode signal Mode and the OR operation result to obtain an input signal of the second RS flip-flop FF2.

[0107] When the mode signal Mode is a high-level signal, the reset signal of the second RS flip-flop FF2 is a high-level signal, the input signal of the second RS flip-flop FF2 is a low-level signal, and the upper tube control signal Ctr_HS output by the second RS flip-flop FF2 is a low-level signal to control the driving unit 123 to drive the upper tube HS to turn off.

[0108] When the mode signal Mode is a low-level signal, if the feedback signal FB is a low-level signal and the fixed-frequency pulse signal On_timer is a high-level signal, the upper tube control signal Ctr_HS output by the second RS flip-flop FF2 is a low-level signal to control the driving unit 123 to drive the upper tube HS to turn off; if the feedback signal FB is a high-level signal, the upper tube control signal Ctr_HS output by the second RS flip-flop FF2 is a high-level signal to control the driving unit 123 to drive the upper tube HS to turn on.

[0109] In this way, when the mode signal Mode is a non-Burst mode signal, the upper tube control subunit 1221 determines the upper tube control signal Ctr_HS according to the fixed-frequency pulse signal On_timer and the feedback signal FB to control the driving unit 123 to drive the upper tube HS on and off. When the mode signal Mode is a Burst mode signal, the upper tube control subunit 1221 pulls down the upper tube control signal Ctr_HS to control the driving unit 123 to drive the upper tube HS off.

[0110] For example, Figure 6 As shown, the lower tube control subunit 1222 includes a third comparator CMP3, a fourth inverter INV4, and a third RS flip-flop FF3. The input of the fourth inverter INV4 is connected to the output of the upper tube control subunit 1221, the output of the fourth inverter INV4 is connected to the power supply of the third comparator CMP3 and the input S of the third RS flip-flop FF3, the non-inverting input of the third comparator CMP3 is connected to the switch node SW, the inverting input of the third comparator CMP3 is grounded, the output of the third comparator CMP3 is connected to the reset terminal R of the third RS flip-flop FF3, and the output Q of the third RS flip-flop FF3 is connected to the second input of the driving unit 123.

[0111] The fourth inverter INV4 can invert the upper tube control signal Ctr_HS and use the inverted signal of the upper tube control signal Ctr_HS as the input signal of the third RS trigger FF3. When the upper tube control signal Ctr_HS is a low level signal, the input signal of the third RS trigger FF3 is a high level signal. When the upper tube control signal Ctr_HS is a high level signal, the input signal of the third RS trigger FF3 is a low level signal.

[0112] When the upper tube control signal Ctr_HS is a low-level signal, the third comparator CMP3 is turned on. The third comparator CMP3 can compare the switch node voltage Vsw with zero voltage to obtain a reset signal for the third RS flip-flop FF3. For example, when the upper tube control signal Ctr_HS is a low-level signal and Vsw ≤ 0, the reset signal of the third RS flip-flop FF3 is a low-level signal, and the lower tube control signal Ctr_LS output by the third RS flip-flop FF3 is a high-level signal, thereby controlling the driver unit 123 to drive the lower tube LS to conduct. When the upper tube control signal Ctr_HS is a low-level signal and Vsw > 0, the reset signal of the third RS flip-flop FF3 is a high-level signal, and the lower tube control signal Ctr_LS is a low-level signal, thereby controlling the driver unit 123 to drive the lower tube LS to turn off.

[0113] In this way, the lower tube control sub-unit 1222 can determine the lower tube control signal Ctr_LS according to the upper tube control signal Ctr_HS and the switch node voltage Vsw, so as to control the driving unit 123 to drive the lower tube LS on and off.

[0114] For example, Figure 4 As shown, the auxiliary control module 130 includes a boost charge pump 131 , an input end of the boost charge pump 131 is connected to the voltage input end IN, and an output end of the boost charge pump 131 is connected to the control end of the high-side tube HS.

[0115] The control terminal of the boost charge pump 131 is connected to the output terminal of the first AND gate AND1. When the load detection signal Det_load and the duty cycle detection signal Det_duty are high, the boost charge pump 131 is enabled. The boost charge pump 131 can boost the received input voltage Vin to generate an auxiliary control voltage Vaux and output it to the control terminal of the high-side transistor HS. For example, Vaux = 2*Vin.

[0116] At this time, the high-side control signal Ctr_HS is a low-level signal, and the boost charge pump 131 can forcibly pull up the control voltage of the high-side HS to control the high-side HS to be turned on. In this way, an NMOS can be selected as the high-side HS. Compared with the existing PMOS as the high-side HS of the Buck converter 10, the area of ​​the high-side HS can be reduced, thereby reducing the area of ​​the Buck converter.

[0117] To sum up, in the scenario of 100% duty cycle, when the Buck converter 10 is lightly loaded, the Buck converter 10 can enter the Burst mode, which can reduce the power consumption of the Buck converter 10. When the Buck converter 10 is heavily loaded, the upper tube HS is kept normally open to make the Buck converter 10 enter the 100% duty cycle. The Buck converter 10 can enter the Burst mode before entering the 100% duty cycle and after exiting the 100% duty cycle, which can achieve a slow change of the output voltage Vout when entering and exiting the 100% duty cycle, thereby improving the stability of the Buck converter 10.

[0118] In some embodiments, Figure 7 A circuit diagram of another main control module provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the feedback unit 121 further includes a second resistor R2 and a second current source IB2. The reference voltage Vref is connected to the non-inverting input terminal of the error amplifier EA and the input terminal of the second current source IB2 via the second resistor R2. The output terminal of the second current source IB2 is grounded, and the control terminal of the second current source IB2 is connected to the output terminal of the mode determination module 110.

[0119] The error amplifier EA is configured to, when the mode signal Mode is a non-Burst mode signal, determine the error amplified signal Veao of the reference voltage Vref and the first feedback voltage Vfb1; and when the mode signal Mode is a Burst mode signal, compare the target reference voltage Vref' and the first feedback voltage Vfb1 to obtain the error amplified signal Veao.

[0120] Exemplarily, the sum of the target reference voltage Vref' and the second preset voltage Vpre2 is equal to the reference voltage Vref, i.e., Vref'=Vref-Vpre2. The second preset voltage Vpre2 is the product of the resistance R2 of the second resistor R2 and the current Ib2 provided by the second current source IB2, i.e., Ib2*R2=Vpre2, and Vpre2>Vpre1. For example, if Ib2=20nA and the resistance R2=1MΩ, then Vpre2=20mV.

[0121] The second resistor R2 and the second current source IB2 form a second voltage divider structure. When the mode signal Mode is a low-level signal, the second voltage divider structure is not connected to the inverting input terminal of the error amplifier EA. The non-phase input voltage of the error amplifier EA is the reference voltage Vref. The error amplifier EA can determine the error amplified signal Veao between the first feedback voltage Vfb1 and the reference voltage Vref.

[0122] When the mode signal Mode is high, the second voltage-divider structure is connected to the inverting input of the error amplifier EA. After the reference voltage Vref passes through the second voltage-divider structure, it is converted into the target reference voltage Vref'. At this point, the non-inverting input voltage of the error amplifier EA is the target reference voltage Vref'. The error amplifier EA can compare the first feedback voltage Vfb1 with the target reference voltage Vref' to generate the amplified error signal Veao. For example, when the target reference voltage is greater than Vfb1, the amplified error signal Veao is high; when the target reference voltage is not greater than Vfb1, the amplified error signal Veao is low.

[0123] For example, Figure 8 The working timing diagram of the Burst mode in the 100% duty cycle scenario provided by the embodiment of the present disclosure is as follows: Figure 8 As shown, in the 100% duty cycle scenario, the duty cycle detection signal Det_duty is a high-level signal. When the Buck converter 10 is lightly loaded, the load current ILOAD is low, the inductor current IL is low, the load detection signal Det_load is a high-level signal, the enable signal EN of the auxiliary control module 130 is a low-level signal, and the mode signal Mode is a high-level signal, so that the Buck converter enters the Burst mode.

[0124] When the Buck converter 10 is heavily loaded, the load current ILOAD is high, the inductor current IL is high, the load detection signal Det_load is low, and the enable signal EN of the auxiliary control module 130 is high. The mode signal Mode is low, causing the Buck converter to enter a 100% duty cycle. Before the Buck converter enters a 100% duty cycle, the Buck converter is in Burst mode and must exit Burst mode. After the Buck converter exits 100% duty cycle, the mode signal Mode enters Burst mode.

[0125] In this way, when the Buck converter 10 is in the Burst mode, the error amplifier EA acts as a comparator to compare the first feedback voltage Vfb1 with the target reference voltage Vref' to obtain the error amplification signal Veao to determine whether to exit the Burst mode. No additional comparator is required, which can reduce the area and power consumption of the control circuit 100, thereby reducing the area and power consumption of the Buck converter 10.

[0126] In some embodiments, Figure 9 A circuit diagram of another mode determination module provided in an embodiment of the present disclosure is shown in FIG. Figure 9As shown, the mode determination module 110 further includes a lower transistor detection unit 114. The input end of the lower transistor detection unit 114 is connected to the fourth output end of the main control module 120, and the output end of the lower transistor detection unit 114 is connected to the third input end of the logic unit 113.

[0127] Exemplarily, as Figure 9 shown, the lower transistor detection unit 114 includes a second inverter INV2, a fourth AND gate AND4, and a second delay unit Dly2. The input end of the second inverter INV2 is connected to the reset end R of the first RS flip-flop FF1. The output end of the second inverter INV2 is connected to the first input end of the fourth AND gate AND4. The second input end of the fourth AND gate AND4 is connected to the fourth output end of the main control module 120. The output end of the fourth AND gate AND4 is connected to the third input end of the logic unit 113 through the second delay unit Dly2.

[0128] The fourth AND gate AND4 can receive the inverted signal of the upper transistor control signal Ctr_HS and the inverted signal of the reset signal RST, and when the reset signal RST is a low-level signal, input the inverted signal of the upper transistor control signal Ctr_HS to the second delay unit Dly2.

[0129] A second preset duration Tpre2 is set in the second delay unit Dly2, and the second preset duration Tpre2 is less than the first preset duration Tpre1, that is, Tpre2 < Tpre1. For example, Tpre2 = 25 μs. The second delay unit Dly2 can determine whether the duration when the inverted signal of the upper transistor control signal Ctr_HS is a high-level signal is greater than the second preset duration Tpre2, that is, can determine whether the duration when the upper transistor control signal Ctr_HS is a turn-off control signal is greater than the second preset duration Tpre2, so as to determine the lower transistor detection signal Det_LS.

[0130] When the duration when the upper transistor control signal Ctr_HS is a turn-off control signal is greater than the second preset duration Tpre2, the lower transistor detection signal Det_LS is a high-level signal, indicating that the Buck converter 10 is lightly loaded under the condition that the input voltage Vin is greater than the output voltage Vout. When the duration when the upper transistor control signal Ctr_HS is a turn-off control signal is not greater than the second preset duration Tpre2, the lower transistor detection signal Det_LS is a low-level signal.

[0131] In this way, the lower transistor detection unit 114 can determine the lower transistor detection signal Det_LS according to whether the duration when the upper transistor control signal Ctr_HS is a turn-off control signal is greater than the second preset duration Tpre2, so as to determine whether the Buck converter 10 is lightly loaded under the condition that the input voltage Vin is greater than the output voltage Vout.

[0132] The logic unit 113 further includes a first OR gate OR1, a first input end of the first OR gate OR1 is connected to the output end of the first AND gate AND1, a second input end of the first OR gate OR1 is connected to the output end of the lower tube detection unit 114, and an output end of the first OR gate OR1 is connected to the input end S of the first RS trigger.

[0133] When the input voltage Vin is greater than the output voltage Vout, the duty cycle detection signal Det_duty is a low-level signal. If the Buck converter 10 is lightly loaded, the lower-side tube detection signal Det_LS is a high-level signal, the input signal of the first RS trigger is a high-level signal, and the mode signal Mode is a high-level signal. If the Buck converter 10 is heavily loaded, the lower-side tube detection signal Det_LS is a low-level signal, and the mode signal Mode is a low-level signal.

[0134] Thus, when the duty cycle detection signal Det_duty is a first level signal, the logic unit 123 can determine the mode signal Mode according to the low-side tube detection signal Det_LS, and can control the Buck converter 10 to enter the Burst mode under the light load condition when the input voltage Vin is greater than the output voltage Vout.

[0135] The present disclosure further provides a power supply chip, comprising the control circuit 100 provided in any one of the above embodiments.

[0136] The power chip provided in the embodiment of the present disclosure includes the control circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the control circuit 100, which will not be repeated here.

[0137] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0138] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a Buck converter, the Buck converter comprising an upper tube and a lower tube, the upper tube and the lower tube being connected in series between a voltage input terminal and ground, characterized in that: The control circuit includes a mode determination module, a main control module and an auxiliary control module; The output end of the mode determination module is connected to the control end of the main control module, the first output end of the main control module and the output end of the auxiliary control module are connected to the control end of the upper tube, and the second output end of the main control module is connected to the control end of the lower tube; The mode determination module is configured to determine a duty cycle detection signal according to the conduction time of the upper tube to determine whether a 100% duty cycle condition is met; and determine a load detection signal according to the current of the upper tube to determine whether a light load condition is met; determining a mode signal according to the duty cycle detection signal and the load detection signal; The main control module is configured to, when the 100% duty cycle condition and the light load condition are met, control the upper tube to be turned off according to the mode signal, so as to control the Buck converter to enter the Burst mode; The auxiliary control module is configured to, when the 100% duty cycle condition is met and the light load condition is not met, control the upper tube to be turned on, so as to control the Buck converter to enter a 100% duty cycle.

2. The control circuit according to claim 1, wherein: The mode determination module includes a duty cycle detection unit, a load detection unit and a logic unit; The input end of the duty cycle detection unit is connected to the control end of the upper tube, the output end of the duty cycle detection unit is connected to the first input end of the logic unit, the first input end of the load detection unit is connected to the voltage input end, the second input end of the load detection unit is connected to the switch node, the output end of the load detection unit is connected to the second input end of the logic unit, and the output end of the logic unit is connected to the control end of the main control module; wherein the switch node is the connection point between the upper tube and the lower tube; The duty cycle detection unit is configured to, when the upper tube is on for a duration greater than a first preset duration, determine that the duty cycle detection signal is a second level signal; and when the upper tube is on for a duration not greater than the first preset duration, determine that the duty cycle detection signal is a first level signal; The load detection unit is configured to, when the upper tube current is less than a preset current, determine that the load detection signal is a second level signal; and when the upper tube current is not less than the preset current, determine that the load detection signal is a first level signal; The logic unit is configured to, when the duty cycle detection signal and the load detection signal are second level signals, determine that the mode signal is a Burst mode signal; and when the duty cycle detection signal is the second level signal and the load detection signal is the first level signal, determine that the mode signal is a non-Burst mode signal.

3. The control circuit according to claim 2, characterized in that: The logic unit includes a first AND gate, a second AND gate and a first RS trigger; A first input end of the first AND gate is connected to the output end of the duty cycle detection unit, a second input end of the first AND gate is connected to the output end of the load detection unit, an output end of the first AND gate is connected to the input end of the first RS trigger, a first input end of the second AND gate is connected to the third output end of the main control module, a second input end of the second AND gate is connected to the output end of the first RS trigger, and an output end of the second AND gate is connected to a reset end of the first RS trigger; The logic unit is further configured to, when the Buck converter is in the Burst mode, determine whether to exit the Burst mode according to the error amplification signal.

4. The control circuit according to claim 3, characterized in that: The duty cycle detection unit includes a first inverter, a third AND gate and a first delay device; The input end of the first inverter is connected to the reset end of the first RS trigger, the output end of the first inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the control end of the upper tube, and the output end of the third AND gate is connected to the first input end of the logic unit through the first delay device.

5. The control circuit according to claim 3, characterized in that: The load detection unit includes a first comparator and a voltage source; The non-inverting input terminal of the first comparator is connected to the switch node through the voltage source, the inverting input terminal of the first comparator is connected to the voltage input terminal, and the power supply terminal of the first comparator is connected to the control terminal of the upper tube.

6. The control circuit according to claim 3, characterized in that: The mode determination module further includes a lower tube detection unit; The input end of the lower tube detection unit is connected to the fourth output end of the main control module, and the output end of the lower tube detection unit is connected to the third input end of the logic unit; The lower tube detection unit is configured to determine the lower tube detection signal according to whether the duration of the upper tube control signal being the off control signal is greater than a second preset duration, and the second preset duration is less than the first preset duration; The logic unit is further configured to, when the duty cycle detection signal is a first level signal, determine the mode signal according to the lower tube detection signal.

7. The control circuit according to claim 6, characterized in that: The logic unit further includes a first OR gate; A first input end of the first OR gate is connected to an output end of the first AND gate, a second input end of the first OR gate is connected to an output end of the lower tube detection unit, and an output end of the first OR gate is connected to an input end of a first RS trigger; The logic unit is further configured to, when the duty cycle detection signal is a first level signal and the lower tube detection signal is a second level signal, determine that the mode signal is the Burst mode signal; and when the duty cycle detection signal and the lower tube detection signal are first level signals, determine that the mode signal is the non-Burst mode signal.

8. The control circuit according to claim 6, wherein: The lower tube detection unit includes a second inverter, a fourth AND gate and a second delay device; The input end of the second inverter is connected to the reset end of the first RS trigger, the output end of the second inverter is connected to the first input end of the fourth AND gate, the second input end of the fourth AND gate is connected to the fourth output end of the main control module, and the output end of the fourth AND gate is connected to the third input end of the logic unit through the second delay device.

9. The control circuit according to claim 3, characterized in that: The main control module includes a feedback unit, a control unit and a drive unit; A first input terminal of the feedback unit is connected to a reference voltage, a second input terminal of the feedback unit is connected to a voltage output terminal, an output terminal of the feedback unit is connected to a first input terminal of the control unit, a second input terminal of the control unit is connected to the switch node, a first output terminal of the control unit is connected to a first input terminal of the drive unit, a second output terminal of the control unit is connected to a second input terminal of the drive unit, a first output terminal of the drive unit is connected to a control terminal of the upper tube and an output terminal of the auxiliary control module, a second output terminal of the drive unit is connected to a control terminal of the lower tube, and a control terminal of the feedback unit and a control terminal of the control unit are connected to an output terminal of the mode determination module; The feedback unit is configured to determine the error amplification signal based on the reference voltage and the first feedback voltage; and when the mode signal is the non-burst mode signal, determine the feedback signal based on the error amplification signal and the second feedback voltage; wherein the sum of the first feedback voltage and the first preset voltage is equal to the output voltage, and the second feedback voltage is the product of the output voltage and a coefficient less than 1; The control unit is configured to, when the mode signal is the Burst mode signal, pull down the upper tube control signal to control the driving unit to drive the upper tube to turn off; when the mode signal is the non-Burst mode signal, determine the upper tube control signal and the lower tube control signal according to the fixed-frequency pulse signal, the feedback signal and the switch node voltage to control the driving unit to drive the upper tube and the lower tube to turn on and off.

10. The control circuit according to claim 9, characterized in that: The feedback unit includes a first resistor, a first current source and an error amplifier; The voltage output end is connected to the inverting input end of the error amplifier and the input end of the first current source through the first resistor, the reference voltage is connected to the non-inverting input end of the error amplifier, and the output end of the first current source is grounded; wherein, the product of the current provided by the first current source and the resistance value of the first resistor is the first preset voltage.

11. The control circuit according to claim 10, characterized in that: The feedback unit further includes a second resistor and a second current source; The reference voltage is connected to the non-inverting input terminal of the error amplifier and the input terminal of the second current source through the second resistor, the output terminal of the second current source is grounded, and the control terminal of the second current source is connected to the output terminal of the mode determination module; The error amplifier is configured to, when the mode signal is the non-Burst mode signal, determine the error amplified signal of the reference voltage and the first feedback voltage; and when the mode signal is the Burst mode signal, compare the target reference voltage and the first feedback voltage to obtain the error amplified signal; The sum of the target reference voltage and the second preset voltage is equal to the reference voltage, the product of the current provided by the second current source and the resistance of the second resistor is the second preset voltage, and the second preset voltage is greater than the first preset voltage.

12. The control circuit according to claim 10 or 11, characterized in that: The feedback unit further includes a control switch, a capacitor and a second comparator; The control switch is connected between the output terminal of the error amplifier and the non-inverting input terminal of the second comparator, the capacitor is connected between the non-inverting input terminal of the second comparator and ground, the inverting input terminal of the second comparator receives the second feedback voltage, the output terminal of the second comparator is connected to the first input terminal of the control unit, and the power supply terminal of the second comparator and the control terminal of the control switch are connected to the output terminal of the mode determination module; When the mode signal is the Burst mode signal, the second comparator is turned on and the control switch is turned on; when the mode signal is the non-Burst mode signal, the second comparator is turned off and the control switch is turned off.

13. The control circuit according to claim 9, characterized in that: The control unit includes an upper tube control subunit and a lower tube control subunit; The control end of the upper tube control subunit is connected to the output end of the mode determination module, the input end of the upper tube control subunit is connected to the output end of the feedback unit, the output end of the upper tube control subunit is connected to the first input end of the driving unit and the first input end of the lower tube control subunit, the second input end of the lower tube control subunit is connected to the switch node, and the output end of the lower tube control subunit is connected to the second input end of the driving unit; The upper tube control subunit is configured to, when the upper tube is turned on, determine the fixed-frequency pulse signal according to the input voltage and the output voltage; When the mode signal is the non-Burst mode signal, determining the upper tube control signal according to the fixed-frequency pulse signal and the feedback signal; when the mode signal is the Burst mode signal, pulling down the upper tube control signal; The lower tube control subunit is configured to determine the lower tube control signal according to the upper tube control signal and the switch node voltage.

14. The control circuit according to claim 13, wherein: The upper tube control subunit includes a timer, a third inverter, a fifth AND gate, a sixth AND gate, a second OR gate, a third OR gate and a second RS flip-flop; An input end of the third inverter is connected to a first input end of the second OR gate and an output end of the feedback unit, an output end of the third inverter is connected to a first input end of the fifth AND gate, a second input end of the second OR gate is connected to an output end of the load detection unit, an output end of the second OR gate is connected to a first input end of a sixth AND gate, a second input end of the sixth AND gate receives an inverted signal of the mode signal, and an output end of the sixth AND gate is connected to an input end of the second RS flip-flop; The second input terminal of the fifth AND gate is connected to the output terminal of the timer, the output terminal of the fifth AND gate is connected to the first input terminal of the third OR gate, the second input terminal of the third OR gate receives the mode signal, the output terminal of the third OR gate is connected to the reset terminal of the second RS flip-flop, the output terminal of the second RS flip-flop is connected to the first input terminal of the driving unit and the first input terminal of the lower tube control subunit, the first input terminal of the timer is connected to the voltage input terminal, the second input terminal of the timer is connected to the voltage output terminal, and the control terminal of the timer is connected to the control terminal of the upper tube; The upper tube control subunit is further configured to, when the mode signal is the non-Burst mode signal, pull down the upper tube control signal when the fixed-frequency pulse signal is a second level signal and the feedback signal is a first level signal.

15. The control circuit according to claim 13, wherein: The lower tube control subunit includes a third comparator, a fourth inverter and a third RS trigger; The input end of the fourth inverter is connected to the output end of the upper tube control subunit, the output end of the fourth inverter is connected to the power supply end of the third comparator and the input end of the third RS trigger, the non-inverting input end of the third comparator is connected to the switch node, the inverting input end of the third comparator is grounded, the output end of the third comparator is connected to the reset end of the third RS trigger, and the output end of the third RS trigger is connected to the second input end of the driving unit; The lower tube control subunit is further configured to pull down the lower tube control signal when the switch node voltage is greater than zero and the upper tube control signal is a first level signal.

16. The control circuit according to any one of claims 1 to 11, characterized in that: The auxiliary control module includes a boost charge pump; The input end of the boost charge pump is connected to the voltage input end, and the output end of the boost charge pump is connected to the control end of the upper tube; The boost charge pump is configured to boost and output the input voltage when the duty cycle detection signal and the load detection signal are second level signals, so as to increase the control voltage of the upper tube.

17. A Buck converter, characterized in that: The control circuit comprises the control circuit according to any one of claims 1 to 16.

18. A power chip, characterized in that: The control circuit comprises the control circuit according to any one of claims 1 to 16.

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