Method for manufacturing semiconductor memory device

Abstract

Provided is a method for manufacturing a semiconductor memory device capable of easily manufacturing the semiconductor memory device. According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a laminated film in which a plurality of first layers including an oxide and a plurality of second layers including a nitride and each having a thickness thicker than that of the first layers are alternately laminated layer by layer in a first direction; forming an opening portion penetrating through the laminated film and extending in the first direction; oxidation of the laminated film having the opening increases the film thickness of each of the plurality of first layers and decreases the film thickness of each of the plurality of second layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor memory device. Background Art

[0002] We have developed a large-capacity nonvolatile memory that enables low-voltage / low-current operation, high-speed switching, and miniaturization and high integration of memory cells.

[0003] The memory cell arrays of large-capacity nonvolatile memories are arranged with multiple metal wirings called bit lines and word lines. Voltages are applied to the bit lines and word lines connected to the cells, and data is written to the memory cells corresponding to those bit lines and word lines. A semiconductor memory device with a three-dimensional array of memory cells is proposed, comprising a laminated film composed of alternating conductive and insulating layers that serve as word lines. Summary of the Invention

[0004] A method for manufacturing a semiconductor memory device that facilitates the manufacture of the semiconductor memory device is provided. The method of manufacturing a semiconductor memory device in one embodiment forms a stacked film comprising a plurality of first layers comprising oxides and a plurality of second layers comprising nitrides, each thicker than the first layers, alternately stacked layer by layer in a first direction; forms an opening penetrating the stacked film and extending in the first direction; and oxidizes the stacked film having the opening, thereby increasing the thickness of each of the first layers and reducing the thickness of each of the second layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a block diagram of a semiconductor memory device according to an embodiment.

[0006] Figure 2 This is an equivalent circuit diagram of a semiconductor memory device according to an embodiment.

[0007] Figure 3 This is a schematic cross-sectional view of a main portion of a semiconductor memory device according to an embodiment.

[0008] Figure 4 Schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0009] Figure 5 Schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0010] Figure 6 Schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0011] Figure 7 Schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figure 8 It is a schematic cross-sectional view showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment.

[0013] Figure 9 It is a schematic cross-sectional view showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment.

[0014] Figure 10 It is a schematic cross-sectional view showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, the embodiment will be described using the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

[0016] In this specification, the upper direction in the drawings is described as "upper," and the lower direction in the drawings is described as "lower" to indicate the positional relationship of components, etc. In this specification, the concepts of "upper" and "lower" do not necessarily indicate the relationship with the direction of gravity.

[0017] (Implementation Method)

[0018] A method for manufacturing a semiconductor storage device according to an embodiment forms a stacked film in which a plurality of first layers comprising oxide and a plurality of second layers comprising nitride and having film thicknesses thicker than the plurality of first layers are alternately stacked layer by layer in a first direction; an opening portion is formed that penetrates the stacked film and extends along the first direction; and the film thicknesses of the plurality of first layers are increased and the film thicknesses of the plurality of second layers are reduced by oxidizing the stacked film having the opening portion.

[0019] The following describes the overall structure of the semiconductor storage device 100. The semiconductor storage device 100 of this embodiment is a NAND flash memory that can store data in a nonvolatile manner. Figure 1 2 is a block diagram of semiconductor memory device 100 according to this embodiment.

[0020] The semiconductor memory device 100 includes a memory cell array 90, a row decoder 91, a column decoder 98, a sense amplifier 99, an input / output circuit 94, a command register 95, an address register 96, and a sequencer (control circuit) 97.

[0021] Memory cell array 90 includes j blocks BLK0 to BLK(j-1). j is an integer greater than or equal to 1. Each of the multiple blocks BLK includes multiple memory cell transistors. The memory cell transistors include electrically rewritable memory cells. Memory cell array 90 includes multiple bit lines, multiple word lines, and source lines to control the voltage applied to the memory cell transistors. The specific structure of the block BLK is described later.

[0022] The row decoder 91 receives and decodes the row address from the address register 96. Based on the decoded row address, the row decoder 91 selects a word line and other elements. Furthermore, the row decoder 91 transmits multiple voltages required for write, read, and erase operations to the memory cell array 90.

[0023] The column decoder 98 receives and decodes the column address from the address register 96. The column decoder 98 selects a bit line based on the decoded column address.

[0024] The sense amplifier 99 detects and amplifies data read from the memory cell transistor to the bit line during a read operation, and transmits write data to the bit line during a write operation.

[0025] The input / output circuit 94 is connected to an external device (host device) via a plurality of input / output lines (DQ lines). The input / output circuit 94 receives commands CMD and addresses ADD from the external device. The commands CMD received by the input / output circuit 94 are sent to the command register 95. The addresses ADD received by the input / output circuit 94 are sent to the address register 96. The input / output circuit 94 also transmits and receives data DAT to and from the external device.

[0026] Sequencer 97 receives control signals CNT from an external device. Control signals CNT include chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. The "n" in the signal name indicates active low. Sequencer 97 controls the overall operation of semiconductor memory device 100 based on command CMD stored in command register 95 and control signals CNT.

[0027] Figure 2 2 is an equivalent circuit diagram of semiconductor memory device 100 according to this embodiment.

[0028] like Figure 2As shown, the semiconductor memory device 100 includes a plurality of word lines WL, a common source line CSL, a source select gate line SGS, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS.

[0029] The memory string MS includes a source select transistor STS, a plurality of memory cell transistors MT, and a drain select transistor STD, which are connected in series between a common source line CSL and a bit line BL.

[0030] In addition, the number of word lines WL, the number of bit lines BL, the number of memory strings MS, and the number of drain select gate lines SGD are not limited to Figure 2 The number of

[0031] Figure 3 This is a schematic cross-sectional view of a main portion of the semiconductor memory device according to this embodiment.

[0032] The substrate 11 is, for example, a semiconductor layer made of single crystal silicon (silicon). For example, a semiconductor wafer or an SOI wafer can be used as the substrate 11.

[0033] Here, the x direction, the y direction perpendicular to the x direction, and the z direction perpendicular to the x and y directions are defined. The substrate 11 is provided parallel to the xy plane. The z direction is an example of a first direction.

[0034] A plurality of first layers 13 made of oxide and a plurality of conductive layers 6b are alternately stacked layer by layer in the z direction on the substrate 11. Thus, a stacked film S2 is provided on the substrate 11. Here, the oxide is, for example, silicon oxide.

[0035] A memory pillar H1 penetrates the stacked film S2 in the z direction. A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage film 4, and an insulating film 5a are provided in the memory pillar H1.

[0036] A core insulating film 1 is provided in the memory pillar H1. The core insulating film 1 includes, for example, silicon oxide.

[0037] A channel semiconductor layer 2 is provided around the core insulating film 1 in the memory pillar H1. The channel semiconductor layer 2 functions as a channel of the memory pillar H1. The channel semiconductor layer 2 is a pillar made of a semiconductor material such as polysilicon.

[0038] A tunnel insulating film 3 is provided around the channel semiconductor layer 2. The tunnel insulating film 3 is an insulating film that allows current to flow when a predetermined voltage is applied. The tunnel insulating film 3 is made of, for example, silicon oxynitride.

[0039] The charge storage film 4 is provided around the tunnel insulating film 3. The charge storage film 4 is a film containing a material capable of storing charge. For example, the charge storage film 4 contains silicon nitride.

[0040] The insulating film 5a is provided around the charge storage film 4. The insulating film 5a is made of, for example, silicon oxide.

[0041] The insulating film 5 b , the barrier metal layer 6 a , and the conductive layer 6 b are provided between adjacent first layers 13 .

[0042] The insulating film 5b is provided on the lower surface of the first layer 13 adjacent to the upper side, the upper surface of the first layer 13 adjacent to the lower side, and the side surface of the insulating film 5a. The insulating film 5b is made of a metal insulating material such as aluminum.

[0043] The barrier metal layer 6a is provided on the lower surface of the upper insulating film 5b, the upper surface of the lower insulating film 5b, and the side surfaces of the insulating film 5b. The barrier metal layer 6a includes, for example, titanium nitride.

[0044] The conductive layer 6b is provided in the barrier metal layer 6a. The conductive layer 6b contains, for example, W (tungsten). The conductive layer 6b corresponds to the word line WL.

[0045] The film thickness L1 of the first layer 13 in the z direction is, for example, 17 nm. The distance L2 between adjacent first layers 13 in the z direction is, for example, 22 nm. The film thickness L1 of the first layer 13 in the z direction and the distance L2 between adjacent first layers 13 in the z direction are not limited to the above.

[0046] Memory cells MC are provided in portions of the memory pillars H1 facing the conductive layer 6b. A plurality of memory cells MC provided in one memory pillar H1 is included in one memory string MS. Each memory cell MC includes a memory cell transistor MT.

[0047] In addition, Figure 3 In the figure, Figure 2 The semiconductor memory device 100 includes a plurality of memory pillars H1.

[0048] In addition, for example, a common source line CSL, a source selection gate line SGS, and a plurality of source selection transistors STS (not shown) are provided between the stacked film S2 and the substrate 11 .

[0049] Furthermore, on the stacked film S2 , for example, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are provided.

[0050] Figures 4 to 7 Schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to this embodiment.

[0051] like Figure 4 As shown, a common source line CSL, a source selection gate line SGS, and a plurality of source selection transistors STS (not shown) are formed on a substrate 11. The substrate 11 is placed on a stage T in a reaction chamber for manufacturing a semiconductor memory device, for example.

[0052] Next, a plurality of first layers 13 comprising oxides and a plurality of second layers 14 comprising nitrides are alternately stacked layer by layer in the z direction by, for example, CVD (Chemical Vapor Deposition). Thus, a stacked film S1 is formed. Here, the oxide is, for example, silicon oxide. In addition, the nitride is, for example, silicon nitride. In addition, Figure 4 In the embodiment, the film thickness L3 of the first layer 13 in the z direction is, for example, 5.6 nm. In addition, the film thickness L4 of the second layer 14 in the z direction is, for example, 30.6 nm. Thus, the film thickness L4 of the second layer 14 is thicker than the film thickness L3 of the first layer. Next, by, for example, RIE (Reactive Ion Etching), an opening H2 (through hole) is formed that penetrates the stacked film S1 in the z direction and extends in the z direction. Figure 4 Here, the temperature of the stage T on which the laminated film S1 is placed when the opening H2 is formed is preferably 70 degrees or lower.

[0053] Then, if Figure 5 As shown, a fifth layer 17 (an example of the third layer) made of a nitride such as silicon nitride is formed on the side surfaces of the plurality of first layers 13 and the side surfaces of the plurality of second layers 14 exposed in the opening H2 by, for example, ALD (Atomic Layer Deposition). The fifth layer 17 has, for example, a cylindrical shape having the opening H2. Figure 5 In the embodiment, the fifth layer 17 is formed on the side surface of the opening H2, but may be formed on the bottom surface of the opening H2.

[0054] Then, if Figure 6As shown, the laminated film S1 having the opening H2 is oxidized. Here, by oxidizing a portion of the second layer 14 including the lower surface of the second layer 14, a third layer 15 including an oxide is formed between the second layer 14 and the first layer 13 adjacent below the second layer 14. In addition, by oxidizing a portion of the second layer 14 including the upper surface of the second layer 14, a fourth layer 16 including an oxide is formed between the second layer 14 and the first layer 13 adjacent above the second layer 14. In addition, by oxidizing the laminated film S1 having the opening H2, the fifth layer 17 is oxidized to form a sixth layer 18 including an oxide (an example of the fourth layer). (Hereinafter, sometimes Figure 6 The oxidation process shown is called "oxidation".)

[0055] Thus, the film thicknesses of the plurality of second layers 14 including nitride are reduced by oxidation.

[0056] Here, by oxidizing the stacked film S1 having the opening H2, as described above, the third layer 15 made of oxide and the fourth layer 16 made of oxide are formed. Here, if it is assumed that each first layer 13 includes the fourth layer 16 formed below each first layer 13 and the third layer 15 formed above each first layer 13, it can be assumed that the film thickness of the plurality of first layers 13 made of oxide is increased by the film thickness of each of the third layer 15 and the fourth layer 16.

[0057] In addition, Figure 3 In Figure 6 The first layers 13 , the fourth layers 16 formed under the first layers 13 , and the third layers 15 formed on the first layers 13 are collectively illustrated as “first layers 13 ”.

[0058] In other words, by oxidizing the stacked film S1 having the opening H2, the portion of the second layer 14 that is in contact with the first layer 13 is oxidized. Consequently, the thickness of each of the plurality of first layers 13 comprising oxide increases by the thickness of each of the third layer 15 and the fourth layer 16. Furthermore, the thickness of each of the plurality of second layers 14 comprising nitride decreases.

[0059] In addition, the process of increasing the film thickness of each of the plurality of first layers 13 and the process of decreasing the film thickness of each of the plurality of second layers 14 are not limited to the above-described process.

[0060] Here, the film thickness L5 of the third layer 15 in the z direction is 5.7 nm, for example. The film thickness L6 of the fourth layer 16 in the z direction is 5.7 nm, for example. The film thickness L7 of the second layer 14 after oxidation in the z direction is greater than Figure 4 and Figure 5The film thickness L4 of the second layer 14 shown is reduced. The film thickness L7 of the second layer 14 in the z direction is, for example, 22 nm.

[0061] Figure 6 The sum of the thickness L5 of the third layer 15 in the z direction, the thickness L6 of the fourth layer 16 in the z direction, and the thickness L7 of the second layer 14 in the z direction (L5+L6+L7) is greater than Figure 4 and Figure 5 The thickness L4 of the second layer 14 in the z direction is thick. This is because silicon nitride is oxidized to silicon oxide, thereby increasing its volume. Therefore, the thickness (L4) of the laminated film S1 after oxidation is 10 ) and the difference (L 10 -L 11 ) is greater than 0.1 μm. For example, in the case of a laminated film S1 formed by repeating the first layer 13 and the second layer 14 320 times, the difference in film thickness (L 10 -L 11 ) is about 2μm.

[0062] As another example, the film thickness L3 of the first layer 13 in the z-direction before oxidation is 2.3 nm, for example. Furthermore, the film thickness L4 of the second layer 14 in the z-direction before oxidation is 30.6 nm, for example. Furthermore, the film thickness L5 of the third layer 15 in the z-direction after oxidation is 7.35 nm, for example. Furthermore, the film thickness L6 of the fourth layer 16 in the z-direction after oxidation is 7.35 nm, for example. Furthermore, the film thickness L7 of the second layer 14 in the z-direction after oxidation is 22 nm, for example.

[0063] As another example, the film thickness L3 of the first layer 13 in the z-direction before oxidation is 4.4 nm, for example. Furthermore, the film thickness L4 of the second layer 14 in the z-direction before oxidation is 30.6 nm, for example. Furthermore, the film thickness L5 of the third layer 15 in the z-direction after oxidation is 6.3 nm, for example. Furthermore, the film thickness L6 of the fourth layer 16 in the z-direction after oxidation is 6.3 nm, for example. Furthermore, the film thickness L7 of the second layer 14 in the z-direction after oxidation is 22 nm, for example.

[0064] In this embodiment, the film thickness L3 of the first layer 13 in the z-direction before oxidation is preferably, for example, not less than 0.3 nm and not more than 10 nm, and the film thickness L4 of the second layer 14 in the z-direction before oxidation is preferably, for example, not less than 25 nm and not more than 45 nm. The film thickness L3 of the first layer 13 in the z-direction before oxidation has a ratio of not less than 0.5% and not more than 30% to the total film thickness of the film thickness L3 of the first layer 13 and the film thickness L4 of the second layer 14 in the z-direction before oxidation.

[0065] In this embodiment, the film thickness L1 (L3+L5+L6) of the first layer 13 in the z direction after oxidation is increased to a ratio of greater than 35% and less than 45% relative to the total film thickness L1 of the first layer 13 in the z direction after oxidation and the film thickness L7 of the second layer 14.

[0066] The oxidation of the stacked film S1 having the opening H2 is preferably performed by wet oxidation (e.g., H2O annealing) under high pressure conditions. Here, the wet oxidation is performed, for example, by supplying water vapor (H2O) generated by a combustion reaction of hydrogen and oxygen into a reaction chamber for manufacturing a semiconductor memory device.

[0067] Here, the partial pressure of water vapor (H2O) in the reaction chamber is preferably 10 atmospheres or higher, which is a high pressure condition, and may be 20 atmospheres or higher. Furthermore, the temperature in the reaction chamber is preferably 400 degrees Celsius or higher. Furthermore, the oxidation time for the laminated film S1 is preferably 10 minutes or longer and 1 hour or shorter, for example, about 30 minutes.

[0068] Next, in the opening H2, a charge storage film 4, a tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are sequentially formed by, for example, ALD (Atomic Layer Deposition). Figure 3 The insulating film 5a shown. Next, the sixth layer 18, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are removed from the bottom of the opening H2 by, for example, etching. Next, the remaining portion of the channel semiconductor layer 2 and the core insulating film 1 are sequentially formed in the opening H2 by, for example, ALD (Atomic Layer Deposition). As a result, the sixth layer 18, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed in the opening H2. Figure 7 ).

[0069] Next, a slit (not shown) is formed in the laminate film S1. A solution such as phosphoric acid is then supplied through the slit to remove the plurality of second layers 14. Next, an insulating film 5b, a barrier metal layer 6a, and a conductive layer 6b are sequentially formed in the portion where the plurality of second layers 14 have been removed. Thus, a laminate film S2 is formed.

[0070] Next, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are formed on the stacked film S2 , thereby obtaining the semiconductor memory device 100 of the embodiment.

[0071] Figures 8 to 10 It is a schematic cross-sectional view showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment.

[0072] The common source line CSL, the source selection gate line SGS, and the plurality of source selection transistors STS (not shown) are formed on the substrate 11, the stacked film S1 is formed, and the opening H2 (through hole) is formed ( Figure 3 ) is the same as the manufacturing method of the semiconductor storage device in the embodiment.

[0073] Next, the laminate film S2 having the opening H2 is oxidized without forming the fifth layer 17. Here, the third layer 15 and the fourth layer 16 are formed, and the side surfaces of the first layers 13 exposed in the opening H2 are oxidized to form the seventh layer 19 ( Figure 8 ).

[0074] Next, for example, the seventh layer 19, a portion of the second layer 14, a portion of the third layer 15, and a portion of the fourth layer 16 are removed using RIE. This exposes the side surface of the second layer 14 that has not been oxidized ( Figure 9 ).

[0075] Next, in the opening H2, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are sequentially formed by, for example, the ALD (Atomic Layer Deposition) method. Next, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are removed from the bottom of the opening H2 by, for example, etching. Next, the remaining portion of the channel semiconductor layer 2 and the core insulating film 1 are sequentially formed in the opening H2 by, for example, the ALD (Atomic Layer Deposition) method. As a result, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed in the opening H2. Figure 10 ). In addition, the subsequent manufacturing process is the same as the manufacturing process of the semiconductor manufacturing device of the embodiment.

[0076] Next, the effects of the method for manufacturing the semiconductor memory device according to the embodiment will be described.

[0077] As the stacked film S1 becomes higher, the depth of the formed opening H2 in the z direction increases, which makes it difficult to form the opening H2.

[0078] Furthermore, when forming the opening H2, the processing of the first layer 13 and the processing of the second layer 14 are performed alternately. Therefore, the conditions for optimal processing vary depending on, for example, the thickness of the first layer 13, the thickness of the second layer 14, and the ratio of the thickness of the first layer 13 to the thickness of the second layer 14. This also becomes a major factor that makes the formation of the opening H2 difficult.

[0079] Therefore, in the manufacturing method of the semiconductor storage device of the embodiment, a stacked film is formed by alternately stacking a plurality of first layers including oxide and a plurality of second layers including nitride and having a film thickness thicker than the film thickness of the plurality of first layers in a first direction; an opening portion is formed that penetrates the stacked film and extends along the first direction; and by oxidizing the stacked film having the opening portion, the film thickness of the plurality of first layers is increased, and the film thickness of the plurality of second layers is reduced.

[0080] When a portion of the second layer 14 containing nitride is oxidized to form a layer containing oxide, the film thickness of the portion of the second layer 14 that has been oxidized to become oxide increases compared to the film thickness before oxidation. This is because the volume of silicon oxide per Si atom is greater than the volume of silicon nitride per Si atom.

[0081] Therefore, when the opening H2 is formed before oxidizing the stacked film S1, the overall thickness of the stacked film S1 in the z-direction is thinner, making it easier to form the opening H2. Furthermore, by oxidizing the stacked film S1 after forming the opening H2, the thickness of the first layer 13 containing oxide can be increased. Therefore, for example, it is easier to suppress data destruction between adjacent memory cells MC and ensure insulation between adjacent word lines WL.

[0082] Furthermore, when forming the opening H2, the second layer 14 containing nitride can be made thicker. Therefore, by making the processing conditions for forming the opening H2 more suitable for processing the second layer 14 than for processing the first layer 13, the opening H2 can be easily processed.

[0083] The oxidation of the stacked film S1 is preferably performed by wet oxidation under high-pressure conditions. Generally, unless a highly reactive manufacturing method such as free radical oxidation is used, it is difficult to form the first layer 13 comprising an oxide by oxidizing the second layer 14 comprising a nitride. However, there is the problem of a decrease in oxidizing power due to, for example, the deactivation of free radicals. On the other hand, when wet oxidation is performed under high-pressure conditions, a decrease in oxidizing power due to, for example, the deactivation of free radicals does not occur. Therefore, for example, an increase in the oxidation rate and an increase in the coverage of the formed oxide layer can be expected.

[0084] Here, in order to perform the above-mentioned wet oxidation, the partial pressure of water vapor (H2O) in the reaction chamber is preferably 10 atmospheres or more. In addition, in order to perform the above-mentioned wet oxidation, the temperature in the reaction chamber is preferably 400 degrees Celsius or more.

[0085] The temperature of the stage T on which the laminated film S1 is placed when forming the processed portion is preferably 70 degrees or lower. The processing speed of the second layer 14 containing nitride is particularly increased when the temperature of the stage T is 70 degrees or lower. Therefore, the opening H2 can be formed more quickly.

[0086] According to the method for manufacturing a semiconductor storage device of this embodiment, a method for manufacturing a semiconductor storage device that can easily manufacture the semiconductor storage device can be provided.

[0087] While several embodiments and examples of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0088] Description of Reference Numerals

[0089] 1: Core insulating film 2: Channel semiconductor layer 3: Tunnel insulating film 4: Charge storage film 5a: Insulating film 5b: Insulating film 6a: Barrier metal layer 6b: Conductive layer 11: Substrate 13: First layer 14: Second layer 15: Third layer 16: Fourth layer 17: Fifth layer (third layer) 18: Sixth layer (fourth layer) 19: Seventh layer 100: Semiconductor storage device T: Stage H2: Opening S1: Laminated film S2: Laminated film

Claims

1. A method for manufacturing a semiconductor memory device, forming a stacked film in which a plurality of first layers including oxide and a plurality of second layers including nitride and each having a film thickness thicker than the plurality of first layers are alternately stacked layer by layer in a first direction; forming an opening penetrating the laminated film and extending along the first direction; and By oxidizing the stacked film having the opening, the thicknesses of the plurality of first layers are increased, and the thicknesses of the plurality of second layers are decreased.

2. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The oxidation is wet oxidation.

3. The method for manufacturing a semiconductor memory device according to claim 2, wherein: The wet oxidation is performed by hydrogen and oxygen.

4. The method for manufacturing a semiconductor memory device according to claim 2, wherein: The partial pressure of water vapor (H 2 O) in the reaction chamber for manufacturing the semiconductor memory device during the wet oxidation is 10 atmospheres or more.

5. The method for manufacturing a semiconductor memory device according to claim 2, wherein: The temperature in the reaction chamber for manufacturing the semiconductor memory device during the wet oxidation is 400 degrees or higher.

6. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The temperature of the stage on which the stacked film is placed when forming the opening penetrating the stacked film and extending in the first direction is 70 degrees or less.

7. The method for manufacturing a semiconductor memory device according to claim 1, wherein: A difference between a film thickness of the stacked film after the oxidation and a film thickness of the stacked film before the oxidation is greater than 0.1 μm.

8. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The thickness of one of the multiple first layers in the first direction before the oxidation is greater than 0.3 nm and less than 10 nm, and the thickness of the second layer in the first direction that is in contact with one of the multiple first layers is greater than 25 nm and less than 45 nm.

9. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The thickness of one of the plurality of first layers after the oxidation is greater than or equal to 35% and less than or equal to 45% of the total thickness of the one of the plurality of first layers and the second layer in contact with the one of the plurality of first layers.

10. The method for manufacturing a semiconductor memory device according to claim 1, wherein: After forming the opening penetrating the stacked film and extending in the first direction, and before oxidizing the stacked film having the opening, forming a third layer including a nitride on side surfaces of the plurality of first layers and side surfaces of the plurality of second layers exposed in the opening; When the stacked film having the opening is oxidized, the third layer is oxidized.

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