Three-dimensional NAND type ferroelectric memory and preparation method thereof

Abstract

The invention provides a three-dimensional NAND type ferroelectric memory and a preparation method thereof. The three-dimensional NAND type ferroelectric memory comprises a stacking structure located on one side of a substrate; the stacked structure comprises gate insulating layers and gate metal layers which are alternately stacked; a through hole is formed in the stacked structure; a first barrier layer, a charge trapping layer, a first ferroelectric layer, a second barrier layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer which are sequentially stacked are arranged in the direction, pointing to the center of the through hole, of the stacked structure. The charge trapping layer not only can trap charges from the gate metal layer, but also can enhance polarization in the ferroelectric layer and enlarge a storage window. In addition, the first barrier layer can prevent the charges trapped by the charge trapping layer from being detrapped, so that the window is reduced, and the retention characteristic is improved. The ferroelectric layer is divided into the first ferroelectric layer and the second ferroelectric layer through the second barrier layer, so that the remanent polarization intensity in the ferroelectric layer is increased, and the effect of widening the storage window is achieved.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a three-dimensional NAND ferroelectric memory and a preparation method thereof. Background Art

[0002] With the rapid development of big data, artificial intelligence (AI), and the Internet of Things (IoT), storage devices urgently need to overcome the bottlenecks in capacity, speed, and reliability. Three-dimensional NAND flash memory has broken through density limits by stacking over 100 layers, but the exponential growth of charge-coupled interference between storage cells leads to problems such as reduced read and write speeds, threshold voltage drift, and reduced data retention.

[0003] Three-dimensional NAND-type ferroelectric memory uses ferroelectric field effect transistors (FeFETs) as storage cells for data storage. FeFETs have attracted considerable attention due to their low power consumption, ease of miniaturization, high read / write speeds, non-destructive read access, and compatibility with complementary metal oxide semiconductor (CMOS) processes, making them a key development direction for new semiconductor memory. Currently, research on constructing FeFETs as memory devices by replacing high-k metal gates with ferroelectric layers as gate dielectrics has become a hot area of ​​exploration for researchers.

[0004] However, the storage window of existing three-dimensional NAND ferroelectric memories is relatively small and cannot meet actual usage requirements. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a three-dimensional NAND ferroelectric memory and a preparation method thereof, which can expand the storage window of the memory. The specific solution is as follows:

[0006] In one aspect, the present application provides a three-dimensional NAND ferroelectric memory, comprising:

[0007] A stacked structure located on one side of the substrate; the stacked structure includes alternately stacked gate insulating layers and gate metal layers;

[0008] The stacked structure has a through hole; in the direction of the stacked structure pointing to the center of the through hole, there are a first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer stacked in sequence.

[0009] Optionally, the material of the first barrier layer is at least one of Al2O3 and SiO2.

[0010] Optionally, the charge trapping layer is made of a high-K material.

[0011] Optionally, the material of the charge trapping layer is at least one of HfO2 and ZrO2.

[0012] Optionally, the thickness of the first blocking layer or the charge trapping layer is in the range of 2 nm to 6 nm.

[0013] Optionally, the material of the second barrier layer is at least one of Al2O3 and AlN.

[0014] Optionally, the thickness of the second barrier layer is less than 5 nm.

[0015] Optionally, the material of the first ferroelectric layer or the second ferroelectric layer is a hafnium-based ferroelectric material.

[0016] In another aspect, an embodiment of the present application further provides a method for preparing a three-dimensional NAND ferroelectric memory, the method comprising:

[0017] forming a stacked structure on one side of the substrate; the stacked structure comprises alternately stacked gate insulating layers and gate metal layers;

[0018] etching the stacked structure to form a through hole;

[0019] A first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer are sequentially deposited on the sidewall of the through hole; the isolation layer completely fills the through hole.

[0020] Optionally, a first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer are sequentially deposited on the sidewalls of the through hole, comprising:

[0021] depositing the first blocking layer and the charge trapping layer over the stacked structure;

[0022] selectively etching the first blocking layer and the charge trapping layer to retain the first blocking layer and the charge trapping layer on the sidewalls of the through hole;

[0023] depositing the first ferroelectric layer over the stacked structure;

[0024] selectively etching the first ferroelectric layer to retain the first ferroelectric layer on the sidewall of the through hole;

[0025] depositing the second barrier layer over the stacked structure;

[0026] selectively etching the second barrier layer to retain the second barrier layer on the sidewall of the through hole;

[0027] depositing the second ferroelectric layer over the stacked structure;

[0028] selectively etching the second ferroelectric layer to retain the second ferroelectric layer located on the sidewall of the through hole;

[0029] forming the interface oxide layer and the channel layer above the stack structure;

[0030] Selectively etching the interface oxide layer and the channel layer to retain the interface oxide layer and the channel layer on the sidewall of the through hole;

[0031] The isolation layer is completely filled in the through hole and is planarized.

[0032] The present invention provides a three-dimensional NAND ferroelectric memory and a method for preparing the same. The three-dimensional NAND ferroelectric memory comprises: a stacked structure located on one side of a substrate; the stacked structure includes alternating gate insulating layers and gate metal layers; a through-hole in the stacked structure; and a first barrier layer, a charge-trapping layer, a first ferroelectric layer, a second barrier layer, a second ferroelectric layer, an interfacial oxide layer, a channel layer, and an isolation layer stacked sequentially in the direction of the stacked structure toward the center of the through-hole. The charge-trapping layer can capture charges from the gate metal layer. The charges from the gate metal layer have opposite polarity to the charges injected from the channel into the interface between the interfacial oxide layer and the second ferroelectric layer, affecting the threshold voltage of the device and increasing the memory window. The charges from the gate metal layer can also strengthen the polarization in the ferroelectric layer, further increasing the memory window. Furthermore, the presence of the first barrier layer prevents the de-trapping of charges captured by the charge-trapping layer, thereby reducing the window and improving the retention characteristics. The second barrier layer separates the ferroelectric layer into the first ferroelectric layer and the second ferroelectric layer, thereby increasing the remanent polarization strength in the two ferroelectric layers and widening the memory window. In short, by adding the first blocking layer, the charge trapping layer and the second blocking layer, the storage window of the three-dimensional NAND ferroelectric memory can be enlarged, the memory's ability to accurately read and write data can be improved, and the storage capacity can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A schematic cross-sectional view of a three-dimensional NAND ferroelectric memory device according to an embodiment of the present application is shown;

[0035] Figure 2 A partial cross-sectional schematic diagram of a three-dimensional NAND ferroelectric memory provided by an embodiment of the present application is shown;

[0036] Figure 3 A schematic diagram showing the effect of charge injection on gate voltage provided by an embodiment of the present application is shown;

[0037] Figure 4 A schematic flow chart of a method for preparing a three-dimensional NAND ferroelectric memory provided in an embodiment of the present application is shown;

[0038] Figure 5A-17 A cross-sectional schematic diagram of another three-dimensional NAND ferroelectric memory provided by an embodiment of the present application is shown.

[0039] Reference numerals

[0040] Substrate 10, gate insulating layer 11, gate metal layer 12, through hole 20, first blocking layer 131, charge trapping layer 132, stack 13 of first blocking layer and charge trapping layer, first ferroelectric layer 14, second blocking layer 15, second ferroelectric layer 16, interface oxide layer 17, channel layer 18, isolation layer 19. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0043] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0044] As described in the background, existing three-dimensional NAND ferroelectric memories have a small storage window, which cannot meet practical application requirements. In a memory cell with a gate metal layer-ferroelectric layer-insulating layer-channel (MFIS) structure, the channel easily injects charge into the interface between the ferroelectric layer and the insulating layer. This charge counteracts the polarization in the ferroelectric layer, thereby shielding the polarization to a certain extent. This is detrimental to data reading and writing, resulting in poor threshold voltage stability and a narrower storage window, which seriously affects the accurate reading and writing of data by the memory cell and the improvement of storage capacity.

[0045] Furthermore, as the number of memory cell operating cycles continues to climb and operating time continues to increase, the degradation of the gate stack structure becomes increasingly prominent. For example, during the ferroelectric polarization reversal process, oxygen vacancy migration triggers polarization fatigue, causing the polarization performance of hafnium-based ferroelectric memory cells to gradually degrade, increasing the risk of stored data loss.

[0046] Based on the above technical problems, embodiments of the present application provide a three-dimensional NAND ferroelectric memory and a method for preparing the same. The three-dimensional NAND ferroelectric memory comprises: a stacked structure located on one side of a substrate; the stacked structure comprises alternating gate insulating layers and gate metal layers; a through-hole in the stacked structure; and a first barrier layer, a charge-trapping layer, a first ferroelectric layer, a second barrier layer, a second ferroelectric layer, an interfacial oxide layer, a channel layer, and an isolation layer stacked sequentially in the direction of the stacked structure toward the center of the through-hole. Thus, the charge-trapping layer can capture charges from the gate metal layer. The charges from the gate metal layer have opposite polarity to the charges injected from the channel into the interface of the interfacial oxide layer and the second ferroelectric layer, affecting the threshold voltage of the device and increasing the memory window. The charges from the gate metal layer can also strengthen the polarization in the ferroelectric layer, further increasing the memory window. Furthermore, the presence of the first barrier layer can prevent the de-trapping of charges captured by the charge-trapping layer, thereby reducing the window and improving the retention characteristics. The second barrier layer separates the ferroelectric layer into the first ferroelectric layer and the second ferroelectric layer, thereby increasing the remanent polarization strength in the two ferroelectric layers and widening the memory window. In short, by adding the first blocking layer, the charge trapping layer and the second blocking layer, the storage window of the three-dimensional NAND ferroelectric memory can be enlarged, the memory's ability to accurately read and write data can be improved, and the storage capacity can be increased.

[0047] For ease of understanding, a three-dimensional NAND ferroelectric memory and a method for manufacturing the same provided in an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0048] refer to Figure 1, which is a cross-sectional schematic diagram of a three-dimensional NAND ferroelectric memory provided in an embodiment of the present application. The three-dimensional NAND ferroelectric memory includes a stacked structure located on one side of a substrate 10, and the stacked structure includes alternately stacked gate insulating layers 11 and gate metal layers 12.

[0049] The substrate 10 may be a polycrystalline silicon (Poly-Si) substrate 10 , a common silicon substrate 10 , a germanium substrate 10 , etc., and may be configured based on actual conditions.

[0050] There are alternatingly stacked gate insulating layers 11 and gate metal layers 12 above the substrate 10. The number of layers of the gate insulating layers 11 and the gate metal layers 12 is not specifically limited. Adjacent gate metal layers 12 are separated by the gate insulating layers 11. The material of the gate metal layers 12 can be, for example, TiN, W or a combination thereof, and the material of the gate insulating layers 11 can be, for example, silicon dioxide.

[0051] In addition, the deposition process of the gate metal layer 12 or the gate insulating layer 11 is not limited here, and can be physical vapor deposition, chemical vapor deposition or atomic layer deposition. Figure 1 As shown, a stacked structure is provided above the substrate 10 , and the stacked structure includes a gate insulating layer 11 , a gate metal layer 12 , a gate insulating layer 11 , a gate metal layer 12 and a gate insulating layer 11 deposited sequentially from bottom to top.

[0052] The stacked structure includes a through hole 20. The shape and specific location of the through hole 20 can be set based on actual needs. For example, the through hole 20 is square or circular. In the direction of the stacked structure toward the center of the through hole 20, a first barrier layer 131, a charge trapping layer 132, a first ferroelectric layer 14, a second barrier layer 15, a second ferroelectric layer 16, an interface oxide layer 17, a channel layer 18, and an isolation layer 19 are stacked in this order.

[0053] The stacked structure points to the center of the through hole 20, that is, the sidewall of the through hole 20 points to the center of the through hole 20. In other words, the sidewall of the through hole 20 has the first barrier layer 131, the charge trapping layer 132, the first ferroelectric layer 14, the second barrier layer 15, the second ferroelectric layer 16, the interface oxide layer 17, the channel layer 18 and the isolation layer 19 deposited in sequence. Figure 1 The stacked layer 13 of the first blocking layer 131 and the charge trapping layer 132 is shown together. The stacked structure, the first blocking layer 131, the charge trapping layer 132, the first ferroelectric layer 14, the second blocking layer 15, the second ferroelectric layer 16, the interface oxide layer 17, the channel layer 18, and the isolation layer 19 together constitute a gate stack structure.

[0054] The present application adds a charge trapping layer 132 between the ferroelectric layer and the gate metal layer 12. The charge trapping layer 132 can capture charges from the gate metal layer 12. This part of the charge will accumulate near the interface between the first ferroelectric layer 14 and the charge trapping layer 132, as well as in the charge trapping layer 132. This part of the charge has an opposite polarity to the charge injected from the channel to the interface between the interface oxide layer 17 and the second ferroelectric layer 16, affecting the threshold voltage, thereby increasing the storage window. In addition, the charge from the gate metal layer can also strengthen the polarization in the ferroelectric layer, further increasing the storage window.

[0055] In addition, a first blocking layer 131 is added between the charge trapping layer 132 and the gate metal layer 12. Due to the presence of ferroelectric polarization in the first ferroelectric layer 14, the electric field in the first blocking layer 131 and the charge trapping layer 132 can be enhanced, further increasing the charge injection on the gate metal layer 12 side, so that the amount of charge injected into the charge trapping layer 132 will be greater, which can further increase the storage window.

[0056] Furthermore, the combination of first blocking layer 131 and charge-trapping layer 132 forms a composite potential barrier at the interface. This barrier effectively prevents charges captured by charge-trapping layer 132 from diffusing into the surrounding environment, thereby reducing the de-trapping of charges. Charges captured by charge-trapping layer 132 can remain trapped for a longer period of time, preventing de-trapping of charges trapped by the charge-trapping layer and reducing the window, thereby improving retention characteristics.

[0057] Furthermore, in this application, the second barrier layer 15 is used to separate the ferroelectric layer into a first ferroelectric layer 14 and a second ferroelectric layer 16, thereby reducing the thickness of the single ferroelectric layer. By reducing the thickness of the single ferroelectric layer, the m-phase in each ferroelectric layer is reduced, increasing the remanent polarization intensity in each ferroelectric layer, thereby increasing the memory window. In short, the addition of the first barrier layer 131, the charge trapping layer 132, and the second barrier layer 15 can increase the memory window of the three-dimensional NAND ferroelectric memory, improve the memory's ability to accurately read and write data, and increase storage capacity.

[0058] The presence of the second barrier layer 15 can not only increase the storage window, but also improve the fatigue characteristics and retention characteristics of the three-dimensional NAND ferroelectric memory. Specifically, the presence of the second barrier layer 15 can inhibit the migration of oxygen vacancies and the formation of continuous grain boundaries in the ferroelectric layer, thereby reducing leakage current, inhibiting the fatigue phenomenon of the ferroelectric layer during repeated polarization, and effectively improving fatigue characteristics and retention characteristics. Inhibiting the formation of continuous grain boundaries can be understood as the presence of the second barrier layer 15 being able to block the formation of leakage channels in the first ferroelectric layer 14 and the second ferroelectric layer 16, avoiding the breakdown of the ferroelectric layer, thereby reducing leakage current in the first ferroelectric layer 14 and the second ferroelectric layer 16. In addition, the introduction of the second barrier layer 15 also enhances the structural stability of the ferroelectric layer, extends the service life of the storage unit, and enhances the reliability of the storage device.

[0059] Next, we will explain the physical principle of increasing the storage window. Figure 2 As shown, it is a partial cross-sectional schematic diagram of a three-dimensional NAND ferroelectric memory provided in an embodiment of the present application. From left to right, the film layers are the gate metal layer 12, the first barrier layer 131, the charge trapping layer 132, the first ferroelectric layer 14, the second barrier layer 15, the second ferroelectric layer 16, the interface oxide layer 17, the channel layer 18 and the isolation layer 19.

[0060] When a positive voltage is applied to the gate metal layer 12, the gate metal layer 12 injects positive charges into the interface between the charge trapping layer 132 and the first ferroelectric layer 14, and injects positive charges into the charge trapping layer 132. The channel injects negative charges into the interface between the interface oxide layer 17 and the second ferroelectric layer 16. Generally, the polarization direction pointing to the channel is defined as the positive direction. The expression of the memory window (MW) is:

[0061]

[0062] Among them, P r represents the polarization intensity in the ferroelectric layer, Q′ it represents the charge amount of the charge trapping layer 132, Q it represents the amount of charge injected from the channel to the interface between the interface oxide layer 17 and the second ferroelectric layer 16, C FE represents the capacitance of the ferroelectric layer, C TDL represents the equivalent capacitance of the charge trapping layer 132 and the first blocking layer 131 .

[0063] The change in threshold voltage is expressed as:

[0064]

[0065] Among them, C ox It represents the equivalent capacitance. It can be seen that when a forward voltage is applied to the gate metal layer 12, Q′ it is positive, which will cause the threshold voltage to drift negatively, and Qit If it is negative, the threshold voltage will drift positively. The principle of applying a negative voltage to the gate metal layer 12 is basically similar. Therefore, it can be known that the charge captured from the gate metal layer 12 will increase the storage window, and the charge captured from the channel will reduce the storage window.

[0066] refer to Figure 3 As shown in FIG. 1 , a schematic diagram of the effect of charge injection on gate voltage provided by an embodiment of the present application is shown, where the horizontal axis represents the gate voltage V g , the vertical axis is the drain current I d (a) shows that when a positive pulse is applied to the gate metal layer 12, the effect of the charge injection at the upper interface (i.e., the interface between the charge trapping layer 132 and the first ferroelectric layer 14) causes the positive pulse reference line to move a large distance to the left, the effect of the first ferroelectric layer 14 causes the positive pulse reference line to move a small distance to the left, and the effect of the charge injection at the lower interface (i.e., the interface between the interface oxide layer 17 and the second ferroelectric layer 16) causes the positive pulse reference line to move to the right. (b) shows that when a negative pulse is applied to the gate metal layer 12, the effect of the charge injection at the upper interface causes the negative pulse reference line to move a large distance to the right, the effect of the first ferroelectric layer 14 causes the negative pulse reference line to move a small distance to the right, and the effect of the charge injection at the lower interface causes the negative pulse reference line to move to the left.

[0067] In short, in the traditional FEFET structure, due to the charge injection at the lower interface, only a storage window of about 1V can be achieved, which cannot meet the requirements of 3D NAND multi-value storage, and seriously limits the application of FEFET structure in 3D NAND. This application captures the charge through the upper interface to achieve a larger storage window.

[0068] In one possible implementation, the material of the first barrier layer 131 can be at least one of Al2O3 and SiO2, although other insulating materials are also possible. Using Al2O3 or SiO2 as the first barrier layer 131 improves insulation performance and interfacial compatibility, while reducing manufacturing costs. Al2O3 has high chemical stability and good insulating properties. Its wide bandgap of approximately 8.7 eV effectively blocks the tunneling of electrons and holes.

[0069] In one possible implementation, the material of the charge trapping layer 132 is a high-K material, which is a material with a high dielectric constant. Generally, a material with a dielectric constant significantly higher than that of silicon dioxide is used as a high-K material. The dielectric constant of silicon dioxide is 3.9, and the dielectric constant of high-K material is usually above 10, and can even reach dozens or higher. By selecting a high-K material as the charge trapping layer 132, the charge trapping ability of the charge trapping layer 132 can be improved, so that it can store more charges, further enhancing the polarization effect in the ferroelectric layer.

[0070] In a possible implementation, the material of the charge trapping layer 132 may be at least one of HfO 2 and ZrO 2 , thereby reducing the material cost of the charge trapping layer 132 and ensuring that the charge trapping layer 132 has good charge trapping capability.

[0071] In one possible implementation, the thickness of the first blocking layer 131 or the charge-trapping layer 132 is in the range of 2 nm to 6 nm. In other words, the thickness of the first blocking layer 131 can be in the range of 2 nm to 6 nm, thereby preventing the first blocking layer 131 from being too thin, which would easily cause the charges captured by the charge-trapping layer 132 to be de-trapped, and preventing the first blocking layer 131 from being too thick, which would result in an excessively long charge injection path and increase the difficulty of charge injection.

[0072] The thickness of the charge trapping layer 132 can range from 2nm to 6nm, thereby avoiding the charge trapping layer 132 being too thin, resulting in fewer defects in the charge trapping layer 132, unable to retain a large amount of charge, and capturing too little charge. It can also avoid the charge trapping layer 132 being too thick, resulting in waste of charge trapping layer 132 materials, thereby reducing preparation costs.

[0073] In a possible implementation, the material of the second barrier layer 15 may be at least one of Al 2 O 3 and AlN. By selecting Al 2 O 3 or AlN as the second barrier layer 15 , the material cost of the second barrier layer 15 can be reduced, and excellent charge isolation effect can be achieved.

[0074] In one possible implementation, the thickness of the second barrier layer 15 can be less than 5 nm, thereby preventing the second barrier layer 15 from being too thick, causing the distance between the ferroelectric layers on both sides to be too large, affecting the polarization effect of the ferroelectric layer, and causing problems in data reading and writing.

[0075] In one possible implementation, the material of the first ferroelectric layer 14 or the second ferroelectric layer 16 can be a hafnium-based ferroelectric material. Typically, the material of the first ferroelectric layer 14 and the material of the second ferroelectric layer 16 can be the same to facilitate process preparation. Of course, the materials of the two ferroelectric layers can also be different.

[0076] In practical applications, the first ferroelectric layer 14 or the second ferroelectric layer 16 can be made of hafnium-based ferroelectric materials of various doping types, such as Hf 0.5 Zr 0.5 O2, or HfO2 ferroelectric material doped with Si, Al, etc. The thickness of the two ferroelectric layers can be in the range of 3 to 10 nm.

[0077] In addition, the material of the interface oxide layer 17 can be silicon dioxide, etc., and the thickness of the interface oxide layer 17 can be in the range of 0 to 5 nm. The material of the channel layer 18 can be polysilicon, etc., for example.

[0078] refer to Figure 4 , which is a flow chart of a method for preparing a three-dimensional NAND ferroelectric memory provided by an embodiment of the present application, the method includes S101 - S103 .

[0079] S101 , forming a stacking structure on one side of the substrate 10 .

[0080] A stacked structure is formed on a substrate 10, and the stacked structure includes alternately stacked gate insulating layers 11 and gate metal layers 12. Specifically, the gate insulating layers 11 and gate metal layers 12 can be alternately formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The gate insulating layer 11 is, for example, silicon dioxide, and the gate metal layer 12 is, for example, TiN / W. Figure 5A As shown, a gate insulating layer 11 is formed on the substrate 10, referring to Figure 5B As shown, in order to continue forming a gate metal layer 12, refer to Figure 6 As shown, three gate insulating layers 11 and two gate metal layers 12 are formed on a substrate 10 .

[0081] S102 , etching the stacked structure to form a through hole 20 .

[0082] Specifically, the gate stack layer 13 may be etched to form a through hole 20, as shown in FIG. Figure 7 shown.

[0083] S103, depositing a first blocking layer 131, a charge trapping layer 132, a first ferroelectric layer 14, a second blocking layer 15, a second ferroelectric layer 16, an interface oxide layer 17, a channel layer 18 and an isolation layer 19 on the sidewalls of the through hole 20 in sequence; the isolation layer 19 completely fills the through hole 20.

[0084] On the sidewall of the through hole 20, a first blocking layer 131, a charge trapping layer 132, a first ferroelectric layer 14, a second blocking layer 15, a second ferroelectric layer 16, an interface oxide layer 17, a channel layer 18 and an isolation layer 19 are sequentially deposited, and the isolation layer 19 is used to completely fill the through hole 20. Figure 1 shown.

[0085] In this way, the charge-trapping layer can capture charges from the gate metal layer. The charges from the gate metal layer have opposite polarity to the charges injected from the channel into the interface oxide layer and the second ferroelectric layer, affecting the threshold voltage of the device and increasing the memory window. The charges from the gate metal layer can also strengthen the polarization in the ferroelectric layer, further increasing the memory window. In addition, the presence of the first barrier layer can prevent the charges captured by the charge-trapping layer from being de-trapped, thereby reducing the window and improving the retention characteristics. The second barrier layer separates the ferroelectric layer into the first ferroelectric layer and the second ferroelectric layer, thereby increasing the remanent polarization strength in these two ferroelectric layers and thus widening the memory window. In short, the addition of the first barrier layer, the charge-trapping layer, and the second barrier layer can increase the memory window of the three-dimensional NAND ferroelectric memory, improve the memory's ability to accurately read and write data, and increase storage capacity.

[0086] Next, how to deposit the above-mentioned film layers on the sidewalls of the through hole 20 is described. In one possible implementation, S103 sequentially deposits a first barrier layer 131, a charge trapping layer 132, a first ferroelectric layer 14, a second barrier layer 15, a second ferroelectric layer 16, an interface oxide layer 17, a channel layer 18, and an isolation layer 19 on the sidewalls of the through hole 20, which may include S1031-S10311.

[0087] S10301 , depositing a first blocking layer 131 and a charge trapping layer 132 on the stacked structure.

[0088] refer to Figure 8 As shown, a stack 13 of a first blocking layer 131 and a charge trapping layer 132 is deposited on the stack structure, wherein the first blocking layer 131 and the charge trapping layer 132 are not specifically distinguished, and the first blocking layer 131 contacts the sidewall of the through hole 20. The deposition process can adopt atomic layer deposition to ensure the density of the film layer.

[0089] S10302 , selectively etching the first blocking layer 131 and the charge trapping layer 132 to retain the first blocking layer 131 and the charge trapping layer 132 located on the sidewall of the through hole 20 .

[0090] refer to Figure 9 As shown, the first blocking layer 131 and the charge trapping layer 132 located on the surface of the gate insulating layer 11, as well as the first blocking layer 131 and the charge trapping layer 132 on the bottom wall of the through hole 20 are removed, thereby retaining the first blocking layer 131 and the charge trapping layer 132 located on the side wall of the through hole 20.

[0091] In actual process, vertical etching can be achieved by adjusting the ion beam etching angle to retain the first blocking layer 131 and the charge trapping layer 132 on the sidewall of the through hole 20 as much as possible and remove the first blocking layer 131 and the charge trapping layer 132 in the horizontal direction.

[0092] S10303 , depositing a first ferroelectric layer 14 on the stacked structure.

[0093] refer to Figure 10 As shown, the first ferroelectric layer 14 is continuously deposited on the gate stack, and the first ferroelectric layer 14 covers the surface of the through hole 20 and the gate insulating layer 11 .

[0094] S10304 , selectively etching the first ferroelectric layer 14 to retain the first ferroelectric layer 14 located on the sidewall of the through hole 20 .

[0095] refer to Figure 11 As shown, the first ferroelectric layer 14 on the surface of the gate insulating layer 11 and the first ferroelectric layer 14 on the bottom wall of the through hole 20 are removed by selective etching, and the first ferroelectric layer 14 on the side wall of the through hole 20 is retained. The specific process of selective etching will not be repeated. Please refer to the description of the selective etching of the first blocking layer 131 and the charge trapping layer 132. The etching of other film layers can also refer to the above description.

[0096] The material of the first ferroelectric layer 14 can be a HfO 2 -based ferroelectric thin film having ferroelectricity, such as HfZrO 2 or HfSiO 2 .

[0097] S10305 , depositing a second barrier layer 15 on the stacked structure.

[0098] refer to Figure 12 As shown, deposition continues above the gate stack to form a second barrier layer 15 . The material of the second barrier layer 15 is, for example, a silicon dioxide layer.

[0099] S10306 , selectively etching the second barrier layer 15 to retain the second barrier layer 15 located on the sidewall of the through hole 20 .

[0100] refer to Figure 13 As shown, the second barrier layer 15 is selectively etched to remove the second barrier layer 15 on the surface of the gate insulating layer 11 and the bottom wall of the through hole 20, and retain the second barrier layer 15 on the sidewall of the through hole 20. The second barrier layer 15 is, for example, SiO2 or Al2O3.

[0101] S10307 , depositing a second ferroelectric layer 16 on the stacked structure.

[0102] refer to Figure 14 As shown, deposition is continued to form the second ferroelectric layer 16 , and the material of the second ferroelectric layer 16 can be the same as that of the first ferroelectric layer 14 .

[0103] S10308 , selectively etching the second ferroelectric layer 16 to retain the second ferroelectric layer 16 located on the sidewall of the through hole 20 .

[0104] refer to Figure 15 As shown, the second ferroelectric layer 16 is selectively etched to remove the second ferroelectric layer 16 located on the surface of the gate insulating layer 11 and the bottom wall of the through hole 20, while retaining the second ferroelectric layer 16 on the side wall of the through hole 20.

[0105] S10309 , forming an interface oxide layer 17 and a channel layer 18 above the stacked structure.

[0106] refer to Figure 16 As shown, the interface oxide layer 17 and the channel layer 18 are continuously deposited. The interface oxide layer 17 is, for example, silicon dioxide, and the material of the channel layer 18 is, for example, polysilicon.

[0107] S10310 , selectively etching the interface oxide layer 17 and the channel layer 18 to retain the interface oxide layer 17 and the channel layer 18 on the sidewall of the through hole 20 .

[0108] refer to Figure 17 As shown, the interface oxide layer 17 and the channel layer 18 are selectively etched to remove the interface oxide layer 17 and the channel layer 18 located on the surface of the gate insulating layer 11 and the bottom wall of the through hole 20, while retaining the interface oxide layer 17 and the channel layer 18 located on the side wall of the through hole 20.

[0109] S10311, completely fill the through hole 20 with the isolation layer 19 and perform a planarization process.

[0110] As shown in Reference 1 , the through hole 20 is completely filled with an isolation layer 19, and the surface of the isolation layer 19 is planarized to make the film surface smooth. The isolation layer 19 is made of, for example, silicon dioxide.

[0111] In addition, this application mainly describes the formation process of the gate stack structure, that is, the gate structure. When forming a complete memory device, it can be prepared by using a gate-first process, that is, forming the gate structure first and then forming the source and drain, or it can be prepared by using a gate-last process, that is, forming the source and drain and then forming the gate structure. This application does not make specific restrictions on this, and it can be selected based on the actual process.

[0112] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by program instruction hardware, and the above-mentioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the above-mentioned storage medium can be at least one of the following media: read-only memory (English: Read-only Memory, abbreviated: ROM), RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0113] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the apparatus embodiments. For relevant portions, refer to the description of the apparatus embodiments.

[0114] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A three-dimensional NAND ferroelectric memory, characterized in that: include: A stacked structure located on one side of the substrate; the stacked structure includes alternately stacked gate insulating layers and gate metal layers; The stacked structure has a through hole; In the direction from the stacked structure to the center of the through hole, there are a first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer stacked in sequence.

2. The three-dimensional NAND ferroelectric memory according to claim 1, wherein: The material of the first barrier layer is at least one of Al2O3 and SiO2.

3. The three-dimensional NAND ferroelectric memory according to claim 1, wherein: The charge trapping layer is made of a high-K material.

4. The three-dimensional NAND ferroelectric memory according to claim 3, wherein: The material of the charge trapping layer is at least one of HfO2 and ZrO2.

5. The three-dimensional NAND ferroelectric memory according to any one of claims 1 to 4, wherein: The thickness of the first blocking layer or the charge trapping layer is in the range of 2 nm to 6 nm.

6. The three-dimensional NAND ferroelectric memory according to any one of claims 1 to 4, wherein: The material of the second barrier layer is at least one of Al2O3 and AlN.

7. The three-dimensional NAND ferroelectric memory according to any one of claims 1 to 4, wherein: The thickness of the second barrier layer is less than 5 nm.

8. The three-dimensional NAND ferroelectric memory according to any one of claims 1 to 4, wherein: The material of the first ferroelectric layer or the second ferroelectric layer is a hafnium-based ferroelectric material.

9. A method for preparing a three-dimensional NAND ferroelectric memory, characterized in that: The method comprises: forming a stacked structure on one side of the substrate; the stacked structure comprises alternately stacked gate insulating layers and gate metal layers; etching the stacked structure to form a through hole; A first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer are sequentially deposited on the sidewall of the through hole; the isolation layer completely fills the through hole.

10. The method for preparing a three-dimensional NAND ferroelectric memory according to claim 9, wherein: A first blocking layer, a charge trapping layer, a first ferroelectric layer, a second blocking layer, a second ferroelectric layer, an interface oxide layer, a channel layer and an isolation layer are sequentially deposited on the sidewall of the through hole, comprising: depositing the first blocking layer and the charge trapping layer over the stacked structure; selectively etching the first blocking layer and the charge trapping layer to retain the first blocking layer and the charge trapping layer on the sidewalls of the through hole; depositing the first ferroelectric layer over the stacked structure; selectively etching the first ferroelectric layer to retain the first ferroelectric layer on the sidewall of the through hole; depositing the second barrier layer over the stacked structure; selectively etching the second barrier layer to retain the second barrier layer on the sidewall of the through hole; depositing the second ferroelectric layer over the stacked structure; selectively etching the second ferroelectric layer to retain the second ferroelectric layer located on the sidewall of the through hole; forming the interface oxide layer and the channel layer above the stack structure; Selectively etching the interface oxide layer and the channel layer to retain the interface oxide layer and the channel layer on the sidewall of the through hole; The isolation layer is completely filled in the through hole and is planarized.

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