High electron mobility transistor and integrated HEMT device

Abstract

The embodiment of the invention provides a high electron mobility transistor and an integrated HEMT device. The high electron mobility transistor comprises a composite cap layer, the composite cap layer comprises a plurality of composite structure layers which are arranged in a stacked mode, and each composite structure layer comprises a GaAs layer; the In < x > Ga < 1-x > As layer is arranged on the upper surface of the GaAs layer; wherein the In components of the plurality of In < x > Ga < 1-x > As layers are gradually increased along the epitaxial growth direction. According to the high-electron-mobility transistor provided by the embodiment of the invention, the cap layer is arranged to be of the alternately stacked structure of the GaAs layers and the In < x > Ga < 1-x > As layers, the In components of the plurality of In < x > Ga < 1-x > As layers are gradually increased along the epitaxial growth direction, and the composite cap layer has a structure similar to a superlattice period, so that electron tunneling is facilitated, the resistance is further reduced, and the performance of the transistor is improved. And the In < x > Ga < 1-x > As layer on the outermost layer uses a high In component material as a semiconductor in contact with ohmic metal, so that the contact resistance of the device can be greatly reduced, and the high-frequency electrical property of the high-electron-mobility transistor is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and an integrated HEMT device. Background Art

[0002] As a three-terminal device, the gallium arsenide pseudomorphic high electron mobility transistor (GaAs pHEMT) offers higher electron mobility and less scattering than other three-terminal devices, making it more widely used in scenarios with high frequency and noise requirements. In microwave RF chips, GaAs pHEMTs are used as power amplifiers (PAs), low-noise amplifiers (LNAs), switches, and logic devices. Key performance parameters for GaAs pHEMTs in microwave RF chips include power gain, operating frequency range, power-added efficiency (PAE), linearity, and noise figure. In GaAspHEMT applications, reducing various parasitic parameters has become essential for improving the device's high-frequency electrical properties. Among these, contact resistance (Rc), a parasitic resistance necessary for the device's current path, is becoming increasingly important for improving the pHEMT's high-frequency electrical properties.

[0003] Therefore, how to reduce the contact resistance to improve the high-frequency electrical properties of high electron mobility transistors is one of the technical difficulties that needs to be solved urgently. Summary of the Invention

[0004] Therefore, in order to overcome at least some of the defects and deficiencies in the prior art, embodiments of the present invention provide a high electron mobility transistor and an integrated HEMT device.

[0005] Specifically, on one hand, an embodiment of the present invention provides a high electron mobility transistor, the high electron mobility transistor includes a composite cap layer, the composite cap layer includes a plurality of composite structure layers stacked, the composite structure layer includes: a GaAs layer; an In x Ga 1-x As layer, provided on the upper surface of the GaAs layer; wherein the plurality of In x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

[0006] In a specific embodiment of the present invention, the surface layer of the In x Ga 1-x The In composition x of the As layer ranges from 0.35 to 0.40. x Ga 1-x The In composition x of the As layer is in the range of 0.20 to 0.25.

[0007] In a specific embodiment of the present invention, the composite cap layer includes a first GaAs layer, a first In layer, and a second GaAs layer. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, the third GaAs layer and the third In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer is in the range of 0.20 to 0.25. x Ga 1-x The In composition x in the As layer is in the range of 0.25 to 0.35. x Ga 1-x The In composition x in the As layer is in the range of 0.35 to 0.40.

[0008] In a specific embodiment of the present invention, the first In x Ga 1-x The In composition x in the As layer is 0.22, and the second In x Ga 1-x The In composition x in the As layer is 0.35, and the third In x Ga 1-x The In composition x in the As layer is 0.40.

[0009] In a specific embodiment of the present invention, the composite cap layer includes a first GaAs layer, a first In layer, and a second GaAs layer. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer and fourth In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer is in the range of 0.2 to 0.25. x Ga 1-x The In composition x in the As layer is in the range of 0.25 to 0.30. x Ga 1-x The In composition x in the As layer is in the range of 0.30 to 0.35. x Ga 1-xThe In composition x in the As layer is in the range of 0.35 to 0.40.

[0010] In a specific embodiment of the present invention, the composite cap layer includes a first GaAs layer, a first In layer, and a second GaAs layer. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer, fourth In x Ga 1-x As layer, fifth GaAs layer and fifth In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer ranges from 0.2 to 0.24. x Ga 1-x The In composition x in the As layer is in the range of 0.24 to 0.28. x Ga 1-x The In composition x in the As layer ranges from 0.28 to 0.32. x Ga 1-x The In composition x in the As layer is in the range of 0.32 to 0.36. x Ga 1-x The In composition x in the As layer is in the range of 0.36 to 0.40.

[0011] In a specific embodiment of the present invention, the thickness of the GaAs layer is in the range of 15 to 30 angstroms, and the In x Ga 1-x The thickness of the As layer ranges from 55 to 75 angstroms. x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms, and the In x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms, and the GaAs layer and the In x Ga 1- x The doping concentration of the As layer is in the range of 6E18~1E19 / cm -3 .

[0012] In a specific embodiment of the present invention, the high electron mobility transistor further includes a substrate, a buffer layer, a first doped layer, a first isolation layer, a channel layer, a second isolation layer, a second doped layer, a barrier layer, a first blocking layer, a GaAs cap layer, and a second blocking layer stacked in sequence, and the composite cap layer is provided on the second blocking layer.

[0013] In a specific embodiment of the present invention, the first barrier layer and the second barrier layer are InGaP barrier layers or AlAs barrier layers.

[0014] On the other hand, an embodiment of the present invention further provides an integrated HEMT device including: the high electron mobility transistor as described above; and a PIN structure.

[0015] As can be seen from the above, the embodiment of the present invention sets the cap layer of the high electron mobility transistor as a composite cap layer, which includes a plurality of composite structure layers stacked together, and the composite structure layer includes a GaAs layer and an In x Ga 1-x As layer, by setting the cap layer as GaAs layer and In x Ga 1-x As layer alternately stacked structure, and multiple In x Ga 1-x The In component of the As layer gradually increases along the direction of epitaxial growth. Since the composite cap layer has a structure similar to the superlattice period, it is conducive to electron tunneling and thus reduces resistance. x Ga 1-x The As layer uses a high-In content material as a semiconductor in contact with the ohmic metal, which can significantly reduce the contact resistance of the device and thus greatly improve the high-frequency electrical properties of the high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 Schematic diagram of the structure of a traditional high electron mobility transistor;

[0018] Figure 2 A schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0019] Figure 3 for Figure 2 Schematic diagram of the structure of the composite cap layer of the high electron mobility transistor;

[0020] Figure 4 Schematic diagram of the structure of another composite cap layer of the high electron mobility transistor of the present invention;

[0021] Figure 5 Schematic diagram of the structure of another composite cap layer of the high electron mobility transistor of the present invention;

[0022] Figures 6 to 10 for Figure 2 Schematic diagram of the structure of medium and high electron mobility transistors at various stages in the fabrication process;

[0023] Figure 11 A schematic structural diagram of an integrated HEMT device provided in an embodiment of the present invention.

[0024] Main component numbers:

[0025] 11. First AlAs barrier layer; 12. GaAs cap layer; 13. Second AlAs barrier layer; 14. GaAs contact layer;

[0026] 20. Substrate; 21. Buffer layer; 22. First isolation layer; 23. Channel layer; 24. Second isolation layer; 25. Barrier layer; 26. First blocking layer; 27. GaAs cap layer; 28. Second blocking layer;

[0027] 30. Composite cap layer; 31. First GaAs layer; 32. First In x Ga 1-x As layer; 33, second GaAs layer; 34, second In x Ga 1-x As layer; 35, third GaAs layer; 36, third In x Ga 1-x As layer; 37, fourth GaAs layer; 38, fourth In x Ga 1-x As layer; 39, fifth GaAs layer; 40, fifth In x Ga 1-x As layer; 41, source; 42, drain; 43, gate;

[0028] 50. PIN structure; 51. InGaP layer; 52. n + -GaAs layer; 52, InGaP layer; 53, IGaAs layer; 54, p + -GaAs layer; 55, first electrode; 56, second electrode; 101, isolation region. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments described in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work shall fall within the scope of protection of the present invention.

[0030] It should be noted that all directional indications (such as up, down, left, right, front, back, top, and bottom) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of the various components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the term "perpendicular" in the embodiments of the invention and the claims refers to the angle between two elements being 90° or a deviation of -5° to +5°, and the term "parallel" refers to the angle between two elements being 0° or a deviation of -5° to +5°.

[0031] In the embodiments of the present invention, references to "first," "second," and the like are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include at least one of these features.

[0032] See also Figure 1 and Figure 2 , Figure 1 Schematic diagram of the structure of a traditional high electron mobility transistor. Figure 2 A schematic diagram of the structure of a high electron mobility transistor provided by an embodiment of the present invention. An embodiment of the present invention provides a high electron mobility transistor, such as Figure 2 As shown, the high electron mobility transistor includes a composite cap layer 30, which includes a plurality of composite structure layers stacked together, the composite structure layer including a GaAs layer and an In x Ga 1-x As layer, In x Ga 1-x The As layer is provided on the upper surface of the GaAs layer. x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

[0033] like Figure 1As shown, a conventional high electron mobility transistor is provided with a first AlAs barrier layer 11, a GaAs cap layer 12, a second AlAs barrier layer 13 and a GaAs contact layer 14 on the barrier layer. In a conventional high electron mobility transistor, the cap layer is usually made of GaAs material as a contact layer, that is, the cap layer is set as the GaAs contact layer 14, and the AlAs material is formed as an etching barrier layer. Its ohmic contact resistance is generally in the range of 0.1Ω·mm to 0.2Ω·mm. When AlAs is used as an etching barrier layer, the contact resistance of the conventional cap layer has little effect on the device under low frequency conditions. However, with the gradual promotion of high-frequency applications, reducing the contact resistance is becoming increasingly important in improving the high-frequency electrical properties of high electron mobility transistors.

[0034] See also Figure 2 In the embodiment of the present invention, the traditional cap layer structure is modified into a composite cap layer 30. The composite cap layer 30 includes a plurality of composite structure layers stacked together, the composite structure layer including a GaAs layer and an In x Ga 1-x As layer, In x Ga 1-x The As layer is provided on the upper surface of the GaAs layer. That is, the composite cap layer 30 includes multiple GaAs layers and multiple In layers. x Ga 1-x As layers are alternately stacked, and multiple In x Ga 1-x The In component of the As layer gradually increases along the direction of epitaxial growth. The composite cap layer 30InGaAs / GaAs of the high electron mobility transistor has a nearly periodic stacking structure that facilitates the flow of electrons and reduces resistance, which is beneficial to improving device current density, transconductance and gain. At the same time, the surface In x Ga 1-x The In component of the As layer is relatively high. Due to its extremely low band gap, it is more conducive to electrons crossing the potential barrier in the ohmic contact than GaAs, thereby reducing the contact resistance. In addition, the gradual decrease of the In component from top to bottom can alleviate the impact of the lattice mismatch of the high In component material.

[0035] In the embodiment of the present invention, the cap layer of the high electron mobility transistor is set as a composite cap layer 30, which includes a plurality of composite structure layers stacked together, and the composite structure layer includes a GaAs layer and an In x Ga 1-x As layer, by setting the cap layer as GaAs layer and In x Ga 1-x As layer alternately stacked structure, and multiple In x Ga 1-xThe In component of the As layer gradually increases along the direction of epitaxial growth. Since the composite cap layer 30 has a structure similar to the superlattice period, it is conducive to electron tunneling and thus reduces resistance. x Ga 1-x The As layer uses a high In component material as a semiconductor in contact with the ohmic metal, which can significantly reduce the contact resistance Rc of the device, thereby greatly improving the high-frequency electrical properties of the high electron mobility transistor. x Ga 1- x The In component of the As layer decreases gradually from top to bottom, which relieves the stress caused by lattice mismatch and makes the In in direct contact with the metal x Ga 1-x The As layer can use a higher In component material to further reduce the ohmic contact resistance. By simulating the traditional high electron mobility transistor and the high electron mobility transistor of the present invention, it is found that compared with the traditional high electron mobility transistor, the cap layer resistance of the composite cap layer 30 of the high electron mobility transistor of the present invention is lower. In the simulation results of the device, the saturation current density of the high electron mobility transistor of the present invention is larger and the peak transconductance is higher, which means that the high electron mobility transistor of the present invention has a higher gain. By simulating the small signal of the device, the current gain of the high electron mobility transistor of the present invention is larger, the cutoff frequency is increased from 93GHz to 97GHz, and the high frequency characteristics are improved.

[0036] See also Figure 2 The high electron mobility transistor provided by the embodiment of the present invention further includes a substrate 20, a buffer layer 21, a first doping layer (not shown in the figure), a first isolation layer 22, a channel layer 23, a second isolation layer 24, a second doping layer (not shown in the figure), a barrier layer 25, a first blocking layer 26, a GaAs cap layer 27 and a second blocking layer 28 stacked in sequence, and the composite cap layer 30 is provided on the second blocking layer 28.

[0037] The substrate 20 may be, for example, a semi-insulating GaAs substrate, which serves as the basic support layer of the device and provides a crystal growth template; the material of the buffer layer 21 may include GaAs, and may, for example, adopt a multi-layer AlGaAs / GaAs superlattice structure, and the buffer layer 21 is used to transition the lattice mismatch and absorb the stress between the substrate and the upper layer material; the first doped layer may be, for example, silicon (Si) doped AlGaAs (n-type); the first isolation layer 22 may be, for example, undoped AlGaAs with a thickness of about 3-10 nm to isolate the doped layer from the channel layer 23 and optimize carrier distribution. cloth; the channel layer 23 can be made of indium gallium arsenide (InGaAs) or gallium arsenide (GaAs), for example; the second isolation layer 24 can be made of undoped AlGaAs, and its thickness is similar to that of the first isolation layer 22, so as to reduce the impact of defects in the barrier layer 25 on the channel layer 23; the second doped layer can be made of silicon (Si)-doped AlGaAs, and its doping concentration is lower than that of the first doped layer, so as to supplement the carrier concentration and enhance the conductivity; the material of the barrier layer 25 is aluminum gallium arsenide (AlGaAs), and the barrier layer 25 forms a heterojunction with the channel layer 23 to generate a strong interface electric field.

[0038] The first barrier layer 26 and the second barrier layer 28 primarily serve as etching barriers. In this embodiment, the first barrier layer 26 and the second barrier layer 28 may be, for example, an InGaP barrier layer or an AlAs barrier layer. That is, the material of the first barrier layer 26 and the second barrier layer 28 may include InGaP or AlAs. The high electron mobility transistor further includes a source 41, a drain 42, and a gate 43. The source 41 and the drain 42 are located on two different regions of the composite cap layer 30, respectively. The gate 40 is disposed on the barrier layer 25 where the first barrier layer 26 is exposed.

[0039] Furthermore, in this embodiment, the In x Ga 1-x The In composition x of the As layer may be in the range of 0.35 to 0.40, for example. x Ga 1-x The As layer is in contact with the metal, and the higher the In content, the lower the barrier height, and thus the lower the ohmic contact resistance. x Ga 1-x The In composition x of the As layer may be in the range of 0.20 to 0.25, for example. x Ga 1-x The As layer is closest to the underlying structure, so the In composition should not be too high to prevent large lattice adaptation.

[0040] Preferably, the composite cap layer 30 of the high electron mobility transistor provided in the embodiments of the present invention may include, for example, 3 to 5 stacked composite structural layers. Arranging the composite cap layer 30 as 3 to 5 stacked composite structural layers can significantly reduce the device's contact resistance Rc, greatly improving the high-frequency electrical properties of the high electron mobility transistor, while also reducing process difficulty and costs.

[0041] See also Figure 3 In one embodiment of the present invention, the composite cap layer 30 may include, for example, three composite structure layers stacked one on top of another. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In layer 32, and a second GaAs layer 33. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35 and third In x Ga 1-x As layer 36. Further, the first In x Ga 1-x The In composition x in the As layer 32 is in the range of 0.20 to 0.25. x Ga 1-x The In composition x in the As layer 32 is 0.22; the second In x Ga 1-x The In composition x in the As layer 34 is in the range of 0.25 to 0.35. x Ga 1-x The In composition x in the As layer 34 is 0.35; the third In x Ga 1-x The In composition x in the As layer 36 is in the range of 0.35 to 0.40. x Ga 1-x The In composition x in the As layer 36 is 0.40.

[0042] See also Figure 4 In one embodiment of the present invention, the composite cap layer 30 may include, for example, four composite structure layers stacked one on top of another. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In layer 32, and a second GaAs layer 33. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35, third In x Ga 1-x As layer 36, fourth GaAs layer 37 and fourth In x Ga 1-xAs layer 38. Further, the first In x Ga 1-x The In composition x in the As layer 32 is in the range of 0.2 to 0.25. Preferably, the first In x Ga 1-x The In composition x in the As layer 32 is 0.22; the second In x Ga 1-x The In composition x in the As layer 34 is in the range of 0.25 to 0.30. Preferably, the second In x Ga 1-x The In composition x in the As layer 34 is 0.28; the third In x Ga 1-x The In composition x in the As layer 36 is in the range of 0.30 to 0.35. x Ga 1-x The In composition x in the As layer 36 is 0.35; the fourth In x Ga 1-x The In composition x in the As layer 38 is in the range of 0.35 to 0.40. x Ga 1-x The In composition x in the As layer 38 is 0.40.

[0043] See also Figure 5 In one embodiment of the present invention, the composite cap layer 30 may include, for example, five composite structure layers stacked one on top of another. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In layer 32, and a second GaAs layer 33. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35, third In x Ga 1-x As layer 36, fourth GaAs layer 37, fourth In x Ga 1-x As layer 38, fifth GaAs layer 39 and fifth In x Ga 1-x As layer 40. Further, the first In x Ga 1-x The In composition x of the As layer 32 is in the range of 0.2 to 0.24. Preferably, the first In x Ga 1-x The In composition x in the As layer 32 is 0.22; the second In x Ga 1-x The In composition x in the As layer 34 is in the range of 0.24 to 0.28. x Ga1-x The In composition x in the As layer 34 is 0.26; the third In x Ga 1-x The In composition x in the As layer 36 is in the range of 0.28 to 0.32. x Ga 1-x The In composition x in the As layer 36 is 0.30; the fourth In x Ga 1-x The In composition x in the As layer 38 is in the range of 0.32 to 0.36. x Ga 1-x The In composition x in the As layer 38 is 0.35; the fifth In x Ga 1-x The In composition x in the As layer 40 is in the range of 0.36 to 0.40. x Ga 1-x The In composition x in the As layer 40 is 0.40.

[0044] In this embodiment, the thickness of the GaAs layer may be in the range of 15 to 30 angstroms. x Ga 1-x The As layer forms a superlattice-like structure to reduce the difficulty of electrons passing through the composite cap layer 30, thereby reducing the contact resistance. x Ga 1-x The thickness of the As layer may be in the range of 55 to 75 angstroms, for example. x Ga 1-x The growth of the As layer will not cause mismatch and can also reduce the ohmic contact resistance. x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms because the In x Ga 1-x The In content of the As layer gradually decreases, and its growth thickness can be slightly increased to reduce resistance. x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms. x Ga 1-x The In component of the As layer is the lowest, so the thickness can be set to 75 to 150 angstroms. x Ga 1-x The doping type of the As layer is N-type heavily doped, and the doping concentration range is 6E18~1E19 / cm -3 , setting such doping concentration can reduce contact resistance.

[0045] See also Figures 6 to 10 , Figures 6 to 10 Schematic diagram of the structure of each stage in the preparation process of the high electron mobility transistor of the present invention.

[0046] First, if Figure 6 As shown, a buffer layer 21, a first doping layer (not shown in the figure), a first isolation layer 22, a channel layer 23, a second isolation layer 24, a second doping layer (not shown in the figure) and a barrier layer 25 are sequentially stacked on the substrate 20. Figure 7 As shown in FIG, a first barrier layer 26, a GaAs cap layer 27, a second barrier layer 28 and a composite cap layer 30 are sequentially grown on the barrier layer 25 from bottom to top. Figure 8 As shown, a source electrode 41 and a drain electrode 42 are grown on the composite cap layer 30. Figure 9 As shown, the composite cap layer 30 and the second barrier layer 28 are etched to expose the GaAs cap layer 27. Figure 10 , the GaAs cap layer 27 and the first barrier layer 26 are etched to expose the barrier layer 25 , and a gate 53 is formed on the barrier layer 25 .

[0047] The above preparation steps are only used to illustrate one method of preparing the high electron mobility transistor device of the present invention, and the present invention is not limited thereto.

[0048] See also Figure 11 The embodiment of the present invention further provides an integrated HEMT device, which includes a high electron mobility transistor and a PIN structure 50. The high electron mobility transistor adopts the high electron mobility transistor described in the above embodiment. The PIN structure 50 may include an InGaP layer 51, an nGaP layer 52, and a plurality of layers stacked on the composite cap layer 30. + -GaAs layer 52, InGaP layer 53, IGaAs layer 54 and p + -GaAs layer 55. A first electrode 55 and a second electrode 56 are also provided on the PIN structure 50. The first electrode 55 is electrically connected to the n + -GaAs layer 52, the second electrode 56 is electrically connected to the p + -GaAs layer. The first electrode 55 and the second electrode 56 can be fabricated in the same process as the source 41, drain 42, and gate 43. The buffer layer 21 on the substrate 20 can also be formed with an isolation region 101 by ion implantation. The composite cap layer 30 can address the lattice mismatch between the PIN structure 50 and the composite cap layer 30. The PIN structure 50 can function as a diode.

[0049] In addition, it can be understood that the aforementioned embodiments are merely exemplary descriptions of the present invention. Under the premise that the technical features do not conflict, the structures do not contradict, and the purpose of the present invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used in combination.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A high electron mobility transistor, characterized in that The high electron mobility transistor includes a composite cap layer, wherein the composite cap layer includes a plurality of composite structure layers stacked together, and the composite structure layer includes: GaAs layer; In x Ga 1-x An As layer is provided on the upper surface of the GaAs layer; Among them, multiple In x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

2. The high electron mobility transistor according to claim 1, wherein The most superficial In x Ga 1-x The In composition x of the As layer ranges from 0.35 to 0.

40. x Ga 1-x The In composition x of the As layer is in the range of 0.20 to 0.

25.

3. The high electron mobility transistor according to claim 1, wherein The composite cap layer includes a first GaAs layer, a first In layer, and a x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, the third GaAs layer and the third In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer is in the range of 0.20 to 0.

25. x Ga 1-x The In composition x in the As layer is in the range of 0.25 to 0.

35. x Ga 1-x The In composition x in the As layer is in the range of 0.35 to 0.

40.

4. The high electron mobility transistor according to claim 3, wherein The first In x Ga 1-x The In composition x in the As layer is 0.22, and the second In x Ga 1-x The In composition x in the As layer is 0.35, and the third In x Ga 1-x The In composition x in the As layer is 0.

40.

5. The high electron mobility transistor according to claim 1, wherein The composite cap layer includes a first GaAs layer, a first In layer, and a x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer and fourth In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer is in the range of 0.2 to 0.

25. x Ga 1-x The In composition x in the As layer is in the range of 0.25 to 0.

30. x Ga 1-x The In composition x in the As layer is in the range of 0.30 to 0.

35. x Ga 1-x The In composition x in the As layer is in the range of 0.35 to 0.

40.

6. The high electron mobility transistor according to claim 1, wherein The composite cap layer includes a first GaAs layer, a first In layer, and a x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer, fourth In x Ga 1-x As layer, fifth GaAs layer and fifth In x Ga 1-x As layer; the first In x Ga 1-x The In composition x in the As layer ranges from 0.2 to 0.

24. x Ga 1-x The In composition x in the As layer is in the range of 0.24 to 0.

28. x Ga 1-x The In composition x in the As layer ranges from 0.28 to 0.

32. x Ga 1-x The In composition x in the As layer is in the range of 0.32 to 0.

36. x Ga 1-x The In composition x in the As layer is in the range of 0.36 to 0.

40.

7. The high electron mobility transistor according to claim 1, wherein The thickness of the GaAs layer ranges from 15 to 30 angstroms, and the In x Ga 1-x The thickness of the As layer ranges from 55 to 75 angstroms. x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms, and the In x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms, and the GaAs layer and the In x Ga 1-x The doping concentration of the As layer is in the range of 6E18~1E19 / cm -3 .

8. The high electron mobility transistor according to any one of claims 1 to 7, wherein: The high electron mobility transistor further includes a substrate, a buffer layer, a first doped layer, a first isolation layer, a channel layer, a second isolation layer, a second doped layer, a barrier layer, a first blocking layer, a GaAs cap layer, and a second blocking layer stacked in sequence, wherein the composite cap layer is provided on the second blocking layer.

9. The high electron mobility transistor according to claim 8, wherein The first barrier layer and the second barrier layer are InGaP barrier layers or AlAs barrier layers.

10. An integrated HEMT device, characterized in that: include: The high electron mobility transistor according to any one of claims 1 to 9; as well as A PIN structure is provided on the composite cap layer.

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