Reducing tensile film cracking

Abstract

Methods and structures for maintaining the integrity of a layer deposited on a semiconductor wafer are presented. Deposition of the multi-layer backside layer stack may reduce the occurrence of cracks in the backside layer. Each backside layer may be deposited by a backside deposition device. A method of substrate processing during manufacturing of an electronic device, the method comprising: depositing one or more front side layers on a front side of the substrate, where the one or more front side layers cause warpage in the substrate; depositing a first bulk backside layer on a backside of the substrate, wherein the first bulk backside layer reduces the warpage in the substrate; depositing a crack prevention backside layer over the first backside layer; and depositing a second body backside layer over the second backside layer, wherein the second body backside layer further reduces the warpage in the substrate.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit of or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] In semiconductor processing, it may be necessary for the wafer to remain substantially flat. However, during normal operation, the wafer may experience wafer warpage. Wafer warpage may result from, for example, incorrect clamping of the electrostatic chuck, the inability of the wafer handler to hold, and pattern transfer problems during photolithography. Processes have been developed to control wafer warpage by keeping the wafer flat within process tolerances. One process involves depositing a film on the backside of the wafer to offset any stress that may cause the wafer to warp. While this stress from the deposited backside film can keep the wafer substantially flat, if the backside film becomes too thick (which may be necessary for wafers with large warpage), the film may crack and may damage the wafer and / or the handling equipment.

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the Invention

[0004] This Summary is presented to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter.

[0005] Some aspects of the present disclosure relate to methods for processing substrates during electronic component manufacturing. Such methods may be characterized by the following operations: (a) depositing one or more front-side layers on the front side of the substrate, wherein the one or more front-side layers induce warpage in the substrate; (b) depositing a first bulk back-side layer on the back side of the substrate, wherein the first bulk back-side layer reduces the warpage in the substrate; (c) depositing a crack-stop back-side layer over the first bulk back-side layer; and (d) depositing a second bulk back-side layer over the second back-side layer, wherein the second bulk back-side layer further reduces the warpage in the substrate.

[0006] In some embodiments, the first bulk backside layer, the crack-stop backside layer, and the second bulk backside layer together constitute a backside stack, and wherein the backside stack has a thickness of about 2 μm to 15 μm. In some embodiments, the first bulk backside layer and the second bulk backside layer each have a thickness of about 3 μm or less.

[0007] In certain embodiments, the first bulk backside layer comprises silicon nitride. In some cases, the first bulk backside layer has an intrinsic internal stress magnitude of about 100 MPa to 1000 MPa.

[0008] In certain embodiments, the crack-stop backside layer comprises silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof. In some cases, the crack-stop backside layer has a density of about 2 g / cm2 to 3.5 g / cm2. In some cases, the crack-stop backside layer has a thickness of about 2 μm or less. In some implementations, the crack-stop backside layer has an elastic modulus of about 180 GPa to 250 GPa.

[0009] In certain embodiments, the warpage of the substrate is about 300 μm or greater. In certain embodiments, at least one of the one or more front side layers comprises a hard mask. In certain embodiments, the one or more front side layers comprise a stack of about 100 or more alternating layers. In some such cases, the stack comprises alternating oxide layers and nitride or polysilicon layers. In certain embodiments, the one or more front side layers have a first type of internal stress, and wherein the first bulk back side layer has the first type of internal stress.

[0010] Any combination of the above features may be implemented together in the method aspects of the present disclosure.

[0011] Certain aspects of the present disclosure relate to a semiconductor processing apparatus that may be characterized by the following features: (a) a processing chamber; (b) a substrate support within the processing chamber; (c) a showerhead; (d) a gas source fluidly connected to the showerhead; and (e) a controller configured to cause: (i) receiving a substrate comprising one or more front side layers that cause warpage in the substrate; (ii) depositing a first bulk back side layer on a back side of the substrate, wherein the first back side layer reduces warpage in the substrate; (iii) depositing a crack-stopping back side layer above the first back side layer; and (iv) depositing a second bulk back side layer above the second back side layer, wherein the second bulk back side layer further reduces the warpage in the substrate.

[0012] In certain embodiments, the warpage in the substrate is about 300 μm or greater. In certain embodiments, at least one of the one or more front side layers is a hard mask. In certain embodiments, the one or more front side layers comprise a stack having about 100 or more alternating layers.

[0013] In some implementations, the controller is configured to cause the first bulk backside layer, the crack-stop backside layer, and the second bulk backside layer (together forming a backside stack) to have a thickness of about 2 μm to 15 μm. In certain embodiments, the first bulk backside layer and the second bulk backside layer each have a thickness of about 3 μm or less.

[0014] In certain embodiments, the first body backside layer comprises silicon nitride.In certain embodiments, the first body backside layer has an intrinsic internal stress of about -500 MPa to 500 MPa.

[0015] In certain embodiments, the crack-stop backside layer has a density of about 2 g / cm2 to 3.5 g / cm2. In some cases, the crack-stop backside layer has a thickness of about 2 μm or less. In some implementations, the crack-stop backside layer has an elastic modulus of about 180 GPa to 250 GPa. In some implementations, the crack-stop backside layer comprises silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0016] Any combination of the above features may be implemented together in the device aspects of the present disclosure.

[0017] In the above aspects of the present disclosure, any combination of one or more of the dependent features may be implemented together or separately from each other when used with the main system or method aspects.Other aspects and features of the present disclosure will be presented below, sometimes with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A and 1B Examples of non-warped and warped semiconductor wafers on an electrostatic chuck are shown.

[0019] Figure 2A Example cross-sectional views showing the warpage of the wafer and the impact of the backside layers and the cracking that can result from high warpage conditions.

[0020] Figure 2B An exemplary cross-sectional view showing the warpage of a wafer is shown, similar to Figure 2A view in Figure 2, but the backside layer structure includes a crack stop layer to prevent Figure 2A Cracking shown in .

[0021] Figure 3is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0022] Figure 4 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0023] Figure 5 An exemplary cross-section of a semiconductor wafer during semiconductor processing is shown according to various embodiments.

[0024] Figure 6A and 6B A block diagram of an exemplary substrate processing system is shown.

[0025] Figure 7A An exemplary cross-section of the edge of the showerhead-base is shown.

[0026] Figure 7B A top view of an example carrier ring is shown.

[0027] Figure 8 A schematic diagram of an example processing system that may be used to perform the methods described herein is shown. DETAILED DESCRIPTION the term

[0028] The following terms are used throughout this specification:

[0029] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor equipment industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. The workpiece can have many shapes, sizes, and materials.

[0030] As used herein, a "semiconductor device manufacturing operation" is an operation performed during the manufacture of a semiconductor device. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own unique semiconductor manufacturing tool, such as a plasma reactor, an electroplating tank, a chemical mechanical planarization tool, a wet etching tool, and the like. Categories of semiconductor device manufacturing operations include subtractive processes, such as etching processes and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of an etching process, a substrate etching process includes a process for etching a mask layer, or more generally, a process for etching any layer of material previously deposited on a substrate surface and / or otherwise remaining on the substrate surface. Such an etching process can etch a stack of layers in a substrate.

[0031] "Fabrication equipment" refers to equipment in which a manufacturing process is performed. Fabrication equipment typically has a processing chamber in which a workpiece resides during processing. Typically, when in use, the fabrication equipment performs one or more semiconductor device fabrication operations. Examples of fabrication equipment used in semiconductor device fabrication include deposition reactors, such as plating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0032] As used herein, "wafer warpage" may refer to deformation of a wafer. The deformation may have radial and / or azimuthal components. Examples of types of wafer warpage include a dome shape, a disk shape, and a potato chip shape. Wafer warpage may occur during manufacturing, for example, due to stress on the wafer during deposition of material on the active surface of the wafer substrate. Wafer warpage may occur during various types of manufacturing, such as when depositing large amounts of stacking material. Wafer warpage may cause complications in subsequent processing steps. For example, if the amount of warpage is too great, the wafer may not be properly clamped. Additionally, if some processing steps (e.g., photolithography) are performed on an excessively warped wafer, poor results may be produced.

[0033] Wafer bow can be measured as the deviation of the average or median distance of the wafer surface from a reference plane. The mid-plane point of the wafer can be the center point (e.g., in the case of concave or dome-shaped warp), or the edge point of the wafer and / or the average edge point of the wafer (e.g., in the case of bow or convex warp). Warped wafer

[0034] Semiconductor device manufacturing typically involves depositing stacks of layers onto a wafer substrate. Typically, most deposition and other processing to form the device occurs on one side of the substrate, often referred to as the front side or front side of the wafer. As the deposited layers accumulate, they introduce stress into the wafer. High net tensile or compressive stress can cause wafer warpage, which is undesirable.

[0035] Warping is particularly likely to occur when depositing large amounts of stack material (such as in the context of 3D-NAND devices) or when depositing thick front-side layers. When warping is significant, it can adversely affect subsequent processing steps. For example, if the warping is too great, the wafer may not be properly clamped. Figure 1A and 1B A wafer on an electrostatic chuck is shown. Figure 1A Wafer 102 is shown on electrostatic chuck 110. When wafer 102 is substantially flat for the purposes of a particular process operation, for example, having a warp of approximately 100 μm or less, then the wafer can be properly clamped, thereby securing the wafer for subsequent processing steps. Figure 1B A warped wafer 104 is shown on an electrostatic chuck 110. When the warp is significant, the wafer may not be properly secured to the electrostatic chuck. Wafer warpage can cause other problems. For example, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat. This problem can manifest as defocusing the photolithography.

[0036] An exemplary stack that may cause these problems is one with alternating oxide and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example of a stack type that may cause warpage includes alternating oxide and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of potentially problematic stack materials include, but are not limited to, tungsten and titanium nitride.

[0037] The materials in the stack can be deposited by chemical vapor deposition (CVD) techniques, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD). These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or warpage is caused by the presence of material on the front side of the wafer.

[0038] The front-side stack can be deposited in any number of layers and thicknesses. In an example, the stack includes about 20 or more layers and has a total thickness of about 2 μm to about 4 μm. However, in some cases, the multilayer stack has about 100 or more layers. In some embodiments, the multilayer stack may have about 500 or more layers. In some embodiments, the multilayer stack may have about 1,000 or more layers. For example, such a stack may have a thickness of about 4 μm to 12 μm.

[0039] The stress induced in the wafer by the stack or other front-side deposits can be from about -500 MPa to about +500 MPa. In some embodiments, the resulting warp is about 150 μm or greater, for example, about 300 μm or greater, about 400 μm or greater, or about 200 μm to about 400 μm (for a 300 mm wafer).

[0040] Another cause of wafer warpage can be front-side processing using a thick hard mask with limited etch selectivity. In these embodiments, at least one of the one or more front-side layers is a hard mask. The thick hard mask may have internal stresses similar to those described above, for example, ranging from 0 MPa to about 500 MPa. The stresses induced by the hard mask can be tensile or compressive. The thick hard mask may cause the wafer to have significant wafer warpage, for example, about 150 μm or more.

[0041] Various techniques have been devised to combat warpage. When warpage is more severe, the deposition process can be adjusted to reduce or offset the internal stresses in the deposited layer. However, any such adjustments should not interfere with the process requirements of the manufacturing equipment. One commonly used technique to counteract warpage is to deposit films on the backside of the wafer.

[0042] Backside deposition can form a high stress film. If the backside layer has the same type of internal stress (tensile or compressive) as the internal stress generated on the front side and the magnitude is comparable, the backside film effectively counteracts and reduces warpage.

[0043] Examples of backside films used to counteract warpage include amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Current backside films have high internal stress and can alleviate the stress exerted on the wafer by the front-side layers, thereby reducing or eliminating wafer warpage. Generally speaking, the backside layer is made of a film with high stress.

[0044] Until relatively recently, the backside film thickness was relatively thin (e.g., <2 μm) because the warpage caused by depositing material on the front side was relatively moderate. Therefore, downstream processes at existing technology nodes generally do not encounter the problems that the embodiments herein are intended to solve. However, modern IC manufacturing technologies may produce substrates with frontside layers that warp more severely than existing nodes. For example, some modern processes have limited etch selectivity between the hard mask and the etched material but still use thick hard mask layers in operations that etch deep trenches or vias. In another example, the number of layers in the frontside stack has increased. For example, in existing nodes, the stack may be about 32 to about 72 layers. Today, the stack may have hundreds or even thousands of layers, thereby increasing the thickness and internal stress of the frontside layer. Typically, wafer warpage compensation is achieved by depositing a single backside layer. As the degree of wafer warpage continues to increase, thicker backside films must be deposited to compensate for the wafer warpage. This leads to certain problems. Due to the large internal stress that occurs in the thick backside layers, these layers may spontaneously form film cracks. For many film materials (e.g., tensile silicon nitride films), cracks are observed in films of thickness required to compensate for warpage values ​​exceeding a critical warpage limit. These warpage limits are often referred to as "warpage cracking limits" or "crack margins."

[0045] If cracks do form, they can create gaps large enough to provide a path for contaminants to directly contact the backside of the wafer, potentially damaging it. For example, chemical wet etchants commonly used to remove backside films can penetrate film cracks in the backside film, resulting in uneven etching or wafer etching, which can cause particle problems such as film peeling. Furthermore, these film cracks can be so severe that they cause the wafer itself to crack; in some cases, the crack depth is twice the film thickness.

[0046] To avoid backside film cracking, wafer warpage may be limited to an amount well below the film's warpage cracking limit. This means that some wafer integration processes are performed in stages, where operations normally performed in a single step are split into a series of steps, each introducing a relatively small amount of warpage that is compensated for by a correspondingly thin backside layer. This increases device manufacturing complexity and reduces overall throughput. Multi-layer backside warpage compensation

[0047] Disclosed herein are methods, systems, and techniques for maintaining the integrity of backside layers and wafers. This reduces the likelihood of wafer damage and reduces the risk of wafer handling issues during subsequent wafer processing.

[0048] In certain embodiments, the wafer may have a second backside layer sandwiched between two bulk backside layers. By selecting the properties of the second backside layer (e.g., mechanical toughness and / or other mechanical properties), the second backside layer can reduce the likelihood of cracks forming in the deposited layer. In this document, the second backside layer is sometimes referred to as a "crack stop layer." A crack stop layer is a backside layer that can be formed between two bulk backside layers. The bulk backside layer has the same type of internal stress as the net stress generated by the front side layer. In a stack including a crack stop layer between two bulk layers, the bulk layers can be primarily used to compensate for wafer warpage, while the crack stop layer provides mechanical strength to prevent cracking in one or both of these bulk layers. The crack stop layer thereby reduces the likelihood of cracking in the bulk layer.

[0049] Back stack structures can use multiple film layers to increase the warpage crack margin without sacrificing the cost-effectiveness or other beneficial properties of individual films. It has been found that crack-stop layers can extend the warpage crack limit of the bulk film. In various embodiments, the bulk films used for the top and bottom layers of the film stack comprise the majority of the stack thickness. The intermediate crack-stop layers may contribute only a small portion of the total stack thickness.

[0050] In some cases, the crack-stop layer is denser and / or tougher than one or more bulk layers, thus helping to strengthen the overall backside layer. By employing such a film, the warpage cracking limit can be extended without sacrificing the cost-effectiveness or other beneficial properties of the bulk film. By avoiding film cracking, the previously mentioned contamination and mechanical integrity issues can be avoided while effectively compensating for high wafer warpage values. Furthermore, because the backside stack can be deposited in a single, continuous operation, the overall processing scheme shortens the frontside integration steps and reduces the number of backside deposition operations.

[0051] In some cases, the backside layer includes multiple crack-stop layers, optionally with more bulk layers. Such a structure can allow the process to tolerate even higher total warpage than when only a single crack-stop layer is used.

[0052] The bulk layer and crack-stop layer can be deposited by any of a variety of techniques, including PECVD, PVD, CVD, ALD, epitaxial growth, and PEALD. Films produced by any of these techniques may spontaneously crack when their critical thickness is exceeded. The disclosed sandwich stack can help achieve higher warpage and thickness using films deposited by any of these and other techniques.

[0053] During wafer processing, the wafer may be subjected to thermal cycling. Thermal cycling subjects the wafer to elevated temperatures. This may be caused by any of a variety of process operations. Thermal cycling may cause a warpage shift in the wafer. Generally speaking, wafers with a large warpage may experience a relatively large warpage shift. A large warpage shift increases the probability of cracking in deposited layers (e.g., backside layers) on the wafer. An example of a thermal cycle is annealing of the wafer. Another example of a thermal cycle is depositing a material, such as a hard mask, on the front side of the wafer. For example, when deposition is performed at a temperature above about 650°C or above about 850°C, thermal cycling may result. In another example, thermal annealing may subject the wafer to thermal cycling, such as at a temperature up to about 1100°C. A backside film stack including a crack prevention layer as disclosed herein may reduce the likelihood of cracking during thermal cycling.

[0054] Figure 2A The problem of backside film cracking is schematically depicted. As shown in the top figure, wafer 201 with moderate warpage can be flattened using a single backside layer, while in the bottom figure, wafer 211 with relatively high warpage exhibits backside film cracking. More specifically, wafer 201 includes a silicon substrate portion 203 that includes one or more frontside warpage-inducing layers (not shown) and a backside warpage compensation layer 207. As shown in the top right figure, backside layer 207 can flatten wafer 201 without cracking. However, wafer 211, which includes a silicon substrate 205 with one or more frontside warpage-inducing layers (not shown) and a backside warpage compensation layer 209, exhibits significantly higher warpage and therefore requires a thicker backside layer. Therefore, while backside layer 209 can substantially flatten wafer 211, it does so at the risk of cracking, as shown in layer 209, as shown in the bottom right figure.

[0055] Figure 2B The invention describes how to improve or mitigate this cracking problem by using a crack-stop layer interposed between two bulk layers in the backside layer. As shown, wafer 221 includes a stack of silicon substrate 223 and backside layer 227 and has a relatively small warpage. In contrast, wafer 231 includes a stack of silicon substrate layer 225 and backside warpage compensation layer 229 and exhibits a significantly larger warpage. Generally speaking, wafers 221 and 231 correspond to Figure 2A 201 and 211. However, backside layer stacks 227 and 229 include an intermediate crack stop layer that is not present in backside layers 207 and 209. Thus, when a thick backside layer is deposited to flatten wafer 231, even wafer 231 exhibiting significant warpage will not exhibit cracks. Furthermore, while the crack stop layer may not be critical to the integrity of low-warpage wafers (e.g., wafer 221), it can be incorporated into the backside layer stack without introducing significant issues.

[0056] like Figure 2B As shown, wafer 221 includes a backside layer stack comprising bulk layers 227A and 227B sandwiching a crack stop layer 228. Similarly, wafer 231 includes a backside layer stack comprising chunky backside layers 229A and 229B sandwiching a crack stop layer 230.

[0057] Figure 3 A first exemplary process is shown which uses deposition of a backside layer structure comprising a crack stop layer and two or more bulk layers. Figure 3 The process begins by depositing one or more front-side layers having a first type of internal stress (tensile or compressive) on a wafer in operation 310. The internal stress from the front-side layers causes the wafer to warp. In some embodiments, the wafer warp is about 300 μm or greater, such as about 400 μm or greater.

[0058] Once the front-side layer is deposited onto the wafer, a first back-side layer having a first type of internal stress is deposited onto the wafer in operation 320. In other words, the internal stress of the back-side layer is the same type of internal stress as the front-side layer deposited in operation 310. For example, if the front-side layer deposited in operation 310 has a tensile internal stress, the deposited first back-side layer also has a tensile internal stress. In another example, if the front-side layer deposited in operation 310 has a compressive internal stress, the deposited first back-side layer also has a compressive internal stress. In some embodiments, the magnitude of the internal stress of the deposited first back-side layer may be less than the magnitude of the internal stress of the deposited front-side layer, i.e., the first back-side layer does not fully compensate for the warpage caused by one or more front-side layers. In some embodiments, the first back-side layer reduces the warpage of the wafer to about 200 μm or less. In some embodiments, the wafer may be substantially flat, i.e., the wafer has a warpage of about 150 μm or less. Because the wafer can be processed to form a backside layer stack, and because the first backside layer forms the portion of the stack closest to the substrate, the first backside layer is sometimes referred to as an "inner" backside layer. Furthermore, because the inner backside layer (optionally, along with subsequently deposited outer backside layers) determines most of the warp compensation and comprises most of the thickness of the backside layer stack, the inner and outer backside layers are sometimes referred to as "bulk" layers.

[0059] The first backside layer can be deposited using CVD, PECVD, ALD, epitaxy, PVD, or other deposition processes. The first backside layer can be deposited using a dedicated backside deposition apparatus. In some embodiments, the wafer switches chambers between operations 310 and 320. The backside deposition apparatus can be a different deposition apparatus than the apparatus used to deposit the one or more frontside layers.

[0060] In operation 330, a second backside layer or a crack-preventing backside layer is deposited on the first / inner backside layer. The second backside layer may have a type of internal stress that is neutral, the same as, or different from the first type of internal stress in the front side layer and the first backside layer. For example, if the first type of stress is tensile, the second type of stress is compressive. In one example, both the front side layer and the first backside layer have tensile internal stress, and the second backside layer has compressive internal stress. In another example, both the front side layer and the first and second backside layers have tensile stress. The amount of warpage compensated by the second backside layer may be less than the amount of warpage compensated by the first backside layer, for example, by about 50% or less, about 30% or less, about 20% or less, or about 10% or less.

[0061] The second (crack-stopping) backside layer formed in operation 330 may be deposited in the same apparatus used to deposit the first backside layer in operation 320 .

[0062] In operation 340, the process deposits a third backside layer on the second crack-stop backside layer. The third backside layer is sometimes referred to as an outer backside layer. In some embodiments, it has substantially the same physical properties as the first inner backside layer. In some cases, the outer backside layer has substantially the same thickness as the inner backside layer (e.g., to about 20%). Therefore, the outer backside layer is sometimes referred to as a bulk backside layer or a second bulk layer.

[0063] The warpage caused by the third, second, and first backside layers can be the sum of the warpage caused by each of the layers. In some embodiments, the combined warpage of the backside layers can be approximately the same as the warpage of the one or more frontside layers. In some embodiments, the warpage contributions of all frontside and backside layers can be combined so that the total warpage of the wafer is minimized (i.e., less than 100 μm). For example, the frontside layer may cause a tensile warpage of approximately 400 μm, while the first inner backside layer may cause a tensile warpage of approximately 200 μm, and the third outer backside layer may also cause a tensile warpage of approximately 100 μm. The warpage caused by the crack-stop layer can be relatively small or minimal.

[0064] Note that the warpage values ​​mentioned for each backside layer assume that the other layers do not compensate for the warpage. For example, when referring to the amount of warpage caused by the first backside layer, we assume that this is the warpage that would occur on the substrate if the other layers were not present (e.g., without the frontside layer). The amount of warpage caused by a layer depends on the internal stress of the material in that layer and the thickness of the layer.

[0065] Figure 4 A second exemplary process for forming a backside layer stack in a manner that reduces the risk of cracking is shown. Figure 4The process begins by depositing one or more front-side layers having a first type of intrinsic stress (tensile or compressive) on a wafer in operation 410. The intrinsic stress from the front-side layers causes the wafer to warp.

[0066] Once one or more front-side layers are deposited onto the wafer, a first back-side layer having a first type of internal stress is deposited onto the wafer in operation 420. The internal stress of the first back-side layer counteracts the internal stress from the front-side layer and may help reduce wafer warpage. The first back-side layer may be a bulk layer. The first back-side layer may be referred to as an inner back-side layer.

[0067] In operation 430, a second backside layer (which is a crack-stop layer) is deposited on the first backside layer. The second backside layer has an internal stress type that is neutral, or the same or opposite to the internal stress of the front-side layer and the first backside layer. As discussed above in the context of operation 630, the second backside layer can be used to reduce the likelihood of cracking in any backside layer. The second backside layer can minimize warping caused by one or more front-side layers.

[0068] In operation 440, a third backside layer (which may include a bulk material) is deposited onto the second backside layer. The third backside layer may have a first type of internal stress. In other words, the stress in the third backside layer is the same as the stress in the front-side layer and the first backside layer. Similar to the first backside layer, the internal stress in the third backside layer counteracts the stress introduced by the front-side layer.

[0069] After deposition of the third backside layer, this process can be Figure 3 However, in Figure 4 In the example shown in FIG4 , the process repeats the deposition of the second crack-stop layer and the third bulk backside layer, as shown in operation 450. This effectively increases the number of layers in the stack. This may be appropriate when the warpage caused by one or more front-side layers is so great that a single crack-stop layer may not be sufficient to prevent cracking. In some embodiments, the process is repeated to deposit more alternating layers of crack-stop and bulk layers. In other words, operation 450 is performed more than once.

[0070] The amount of warpage caused by each layer can be controlled to control the overall warpage of the substrate. For example, the stress magnitude from the sum of the deposited backside layers can be equal to the stress magnitude from the frontside layers. When the net difference in the amount of warpage from the frontside layers and the amount of warpage from the deposited backside layers is relatively low (e.g., a difference of approximately 0 to 30%), the overall warpage of the wafer may be minimal or acceptable for further processing.

[0071] In backside deposition operations 420-450, each deposition layer can be deposited by a backside deposition apparatus. In some embodiments, the wafer can remain in the same chamber for operations 420-450. In some embodiments, the wafer can switch chambers between operations 410 and 420. The backside deposition apparatus can be a different deposition apparatus than the apparatus used to deposit the one or more frontside layers. For example, in operation 410, the wafer can be located in a first chamber for deposition of the frontside layer, while in operations 420-450, the wafer can be moved to a second chamber for deposition of each backside layer.

[0072] Figure 5 Shows that in progress Figure 4 5. An exemplary cross-section of wafer 502 after exemplary processing in FIG. Wafer 502 has a main structure 503 (e.g., a single crystal silicon substrate). A front-side layer 501 is deposited on the front side of the main structure 503. Front-side layer 501 has a first type of internal stress, which can be tensile or compressive. A first back-side layer 504 is deposited on the back side of the main structure 503. First back-side layer 504 has a first type of internal stress, i.e., the same internal stress as the front-side layer. Layer 504 is a bulk back-side layer. A second back-side layer 506 is deposited on the first back-side layer 506. Second back-side layer 508 is a crack-stop layer. A third back-side layer 508 is deposited on the second back-side layer 506. Third back-side layer 508 has a first type of internal stress. It is a second bulk layer (in combination with bulk layer 504).

[0073] A fourth backside layer 516 is deposited on the third backside layer 506. The backside layer 516 is composed of a crack-stop material. Thus, in conjunction with the layer 506, the backside layer 516 can be considered a second crack-stop layer.

[0074] Finally, a fifth backside layer 518 is deposited on the fourth backside layer 516. The fifth backside layer is composed of a bulk material and has a first type of intrinsic stress.

[0075] The five backside layers on wafer 502 together form a stack that includes three bulk layers 504 , 508 , and 518 interposed with two crack stop layers 506 and 516 .

[0076] As described above, the internal stress of the front-side layer 501 may cause wafer warpage. The internal stress of the back-side layer may offset the internal stress of the front-side layer 501. To minimize wafer warpage, the net internal stress of the back-side layer may be approximately equal to the internal stress of the front-side layer 501. Therefore, if the front-side layer 501 has a tensile warpage of approximately 400 μm, the back-side layer may have a total tensile warpage of approximately 400 μm. Main layer

[0077] As described, the backside layer stack may include one or more bulk layers and one or more crack-stop layers. The one or more bulk layers may provide most or substantially all of the warpage compensation, while the crack-stop layers provide relatively little, if any, warpage compensation while protecting the bulk layer from cracking. These functions or capabilities may result from the different physical properties of the one or more bulk layers and the one or more crack-stop layers. This section describes the properties of the bulk layer.

[0078] Typically, in wafers having only a single backside layer, the backside layer thickness is approximately proportional to the wafer warpage. Larger values ​​of wafer warpage require a thicker backside compensation layer. Wafers having a wafer warpage of about 300 μm or greater (e.g., about 400 μm or greater) may require a backside film that is so thick that it may be susceptible to cracking. In the multi-layer backside layer stacks disclosed herein, similarly, the total thickness of the bulk layers may be roughly proportional to the wafer warpage caused by one or more frontside layers. This assumes that the crack stop layer (or multiple crack stop layers) does not contribute substantially to warpage compensation. While the total combined thickness of the backside bulk layers generally depends on factors such as the amount of warpage to be compensated and the inherent internal stress of the bulk layers, in some embodiments, the total thickness of all bulk layers (the sum of the thicknesses of all bulk layers on the wafer backside stack) is at least 1 μm, or about 1 to 10 μm.

[0079] As with the total thickness of the backside layers in the stack, the thickness of each bulk layer can vary depending on parameters such as the inherent internal stress of the layer, the crack margin of the bulk layer material, and the number of bulk layers in the backside stack. In many embodiments, each bulk layer is thicker than any crack-stop layer in the stack. In certain embodiments, the thickness of any single backside layer in the stack is no greater than about 3 μm, or about 0.1 to 3 μm. The thickness values ​​reported can apply to any one or more bulk backside layers in a multilayer backside stack. Any two bulk backside layers can have the same or different thicknesses.

[0080] In certain embodiments, the bulk backside layer comprises a material having an inherent internal stress having a magnitude of at least about 100 MPa, or between about 100 and 1000 MPa. These values ​​may be for tensile or compressive internal stress, as may be the case with the type of backside material required to offset warping caused by one or more frontside layers. In certain embodiments, the magnitude of the inherent internal stress of the bulk backside layer material is greater than the magnitude of the inherent internal stress of the crack-stop layer in the backside stack. The aforementioned internal stress values ​​may apply to any one or more bulk backside layers in a multilayer backside stack. Any two bulk backside layers may have the same or different internal stress values.

[0081] Exemplary materials for making a bulk backside layer with tensile internal stress include silicon nitride (SiN), silicon oxynitride, and polymer layers. As an example, CVD or PECVD techniques can be used to deposit the tensile film. In order to combat wafer warpage caused by a front side layer with compressive internal stress, a compressive film can be used for the bulk backside layer. Specific materials and / or processing conditions can be used to form the compressive film. Exemplary materials for making the compressive film include silicon oxide (SiO x ), silicon nitride, aluminum oxide, aluminum nitride, and polysilicon. CVD or PECVD techniques can be used to deposit the compressive film. The above materials and deposition techniques can be applied to any one or more bulk backside layers in a multilayer backside stack. Any two bulk backside layers can be formed using the same or different techniques.

[0082] In certain embodiments, the body backside layer comprises a density of about 1.5 to 3 g / cm 3 , or about 2.1 to 2.9 g / cm 3 In various embodiments, in a backside stack comprising a crack-stop layer and a bulk layer, the bulk backside layer material has a lower density than the crack-stop layer material. The above density characteristics may apply to any one or more bulk backside layers in a multilayer backside stack. Any two bulk backside layers may have the same or different densities. Crack-stop layer

[0083] This section describes the properties of a crack-stop layer according to certain embodiments.

[0084] The thickness of the crack-stop backside layer can vary depending on parameters such as the inherent density, stiffness, and / or toughness of the layer. In many embodiments, the crack-stop backside layer is thinner than any of the bulk backside layers in the backside stack. In certain embodiments, the thickness of the crack-stop backside layer within the stack is no greater than about 2 μm, or about 0.1 to 2 μm. In embodiments having multiple crack-stop backside layers, any two crack-stop backside layers can have the same or different thicknesses.

[0085] In certain embodiments, the crack-arresting backside layer comprises a material having an inherent internal stress having a magnitude of at least about 500 MPa. Both tensile and compressive stress-arresting layers may be used. In certain warpage applications, tensile stress may more easily achieve higher warpage compensation. Examples of internal stresses for the crack-arresting backside layer may range from about -500 MPa (compression) to about 800 MPa (tensile). In embodiments having multiple crack-arresting backside layers, any two crack-arresting backside layers may have the same or different internal stress values.

[0086] Examples of materials for the crack-stop backside layer include silicon nitride, silicon oxide, silicon oxynitride, and any combination thereof. Other materials, including materials that do not contain silicon, may be used. In embodiments having multiple crack-stop backside layers, any two crack-stop backside layers may comprise the same or different materials.

[0087] In certain embodiments, the crack-stop backside layer comprises a density of about 2 to 3.5 g / cm 3 or about 2.3 to 3.1 g / cm 3 In various embodiments, in a backside stack comprising a crack-stop layer and a bulk layer, the crack-stop backside layer material is denser than the bulk layer material. In embodiments having multiple crack-stop backside layers, any two crack-stop backside layers can have the same or different densities.

[0088] In certain embodiments, the crack-stop backside layer comprises a material having a fracture toughness greater than any bulk backside layer in the same stack as the crack-stop layer.

[0089] Fracture toughness is the critical stress intensity factor for sudden cracking, where the propagation of the crack suddenly becomes rapid and unrestrained. Fracture toughness is a quantitative measure of a material's resistance to crack propagation, and standard values ​​for given materials are generally available.

[0090] In certain embodiments, the crack-stop layer has an elastic modulus of about 50 GPa to 250 GPa, or about 180 GPa to 250 GPa.

[0091] The crack-stop backside layer can be deposited by any of the processes described herein for forming any backside layer, including the bulk backside layer. Those skilled in the art will understand how to determine, adjust, and / or adjust the deposition conditions to produce a crack-stop backside layer having the appropriate composition, density, thickness, internal stress, toughness, and / or any other physical or chemical properties to provide appropriate performance. Example

[0092] By depositing a relatively thin, dense, rigid, and highly fracture-tough crack-preventing film between two less dense, less fracture-tough bulk layers to create a sandwich structure, the crack margin of all films can be significantly improved. In one example, the sandwich stack exhibited a 12% to 46% improvement in warpage crack margin compared to a single film. In other words, the bulk film itself has a warpage crack margin of X. Using a multilayer stack, the stack can achieve a warpage crack margin of 1.12X to 1.46X.

[0093] In one example, a backside bulk film was found to have a crack margin warpage of 391 μm. Above this warpage, the backside film must be too thick and will crack. However, when the bulk film is deposited in a film stack with a crack-stop layer, it was found to remain crack-free at warpages up to 571 μm. This represents an improvement of almost 50% in warpage crack margin. This is because the inner film in this stack acts as a stop layer, separating the layers above and below it and preventing either layer from reaching a critical thickness, or critical warpage limit. Consequently, higher warpage can be tolerated without cracks forming in the backside layer. Device

[0094] Figure 6A 6 is a block diagram illustrating a substrate processing system 600 for performing processing on a wafer 602 (also referred to as a wafer) according to some embodiments. As shown, the substrate processing system can include a chamber 634. A central column can be configured to support a pedestal while the top surface of the wafer 602 is being processed (e.g., a film is being formed on the top surface of the wafer 602 or on the backside of the wafer 602). According to some embodiments disclosed herein, the pedestal can be referred to as a showerhead pedestal ("ShoPed") 606. A showerhead 636 can be disposed above the showerhead 606.

[0095] In some embodiments, the showerhead 636 can be electrically coupled to a power supply 638 via a matching network 640. The power supply 638 can be controlled by a control module 642, such as a controller. In some embodiments, power can be provided to the showerhead 606 rather than the showerhead 636. The control module 642 can be configured to operate the substrate processing system 632 by implementing process inputs and controls for a particular process recipe. Depending on whether the top surface of the wafer 602 is receiving a deposited layer or layer stack or whether the bottom surface of the wafer 602 is receiving a deposited layer or layer stack, the controller module 642 can set various operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the wafer 602, and / or the height of the wafer 602 relative to the showerhead 606.

[0096] In some embodiments, the center column may also include lift pins that are controlled by a lift pin controller. These lift pins may be used to lift the wafer 602 from the showerhead 606 to allow the end effector (not shown) to pick up the wafer and lower the wafer 602 after it has been placed by the end effector. The end effector may also position the wafer 602 over the spacer 644. As will be described below, the spacer 644 may be sized to provide a controlled separation of the wafer 602 between the top surface of the showerhead 636 (facing the wafer) and the top surface of the showerhead 606 (facing the wafer).

[0097] In some embodiments, the substrate processing system 632 can further include a first gas manifold 646 connected to a first gas source 648 (e.g., a gas chemical and / or an inert gas supplied from a facility). The control module 642 can control the delivery of the first gas source 648 through the first gas manifold 646, depending on the process being performed above the top surface of the wafer 602. The selected gas can then flow into the showerhead 636 and be distributed in the volume of space defined between the surfaces of the showerhead 636 facing the wafer 602 when the wafer is positioned above the susceptor.

[0098] In some embodiments, the substrate processing system 632 may further include a second gas manifold 650 connected to a second gas source 652 (e.g., a gas chemical and / or an inert gas supplied from a facility). Depending on the process being performed on the bottom surface of the wafer 602, the control module 642 may control the delivery of the second gas source 652 through the second gas manifold 650. The selected gas may then flow into the showerhead 636 and be distributed in the volume of space defined between the surfaces of the showerhead 606 facing the bottom surface or underside (backside) of the wafer 602 when the wafer is positioned above the spacer 644. The spacer 644 may provide separation that optimizes deposition on the bottom surface of the wafer 602 and reduces deposition on the top surface of the wafer 602. In some embodiments, when the deposition target is the bottom surface of the wafer 602, an inert gas may flow over the top surface of the wafer 602 via the showerhead 636, which may push the reactant gas away from the top surface and enable the reactant gas provided from the showerhead 606 to be directed to the bottom surface of the wafer 602.

[0099] Furthermore, the gases may be pre-mixed or not. Appropriate valves and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. The process gases may exit the chamber 634 via an outlet. A vacuum pump (e.g., a single-stage or two-stage mechanical dry pump and / or a turbomolecular pump) may be used to extract the process gases and maintain a suitable low pressure within the reactor through a closed-loop flow restriction device (e.g., a throttle valve or a pendulum valve).

[0100] In some embodiments, a carry ring 654 may surround an outer region of the showerhead 606. When the top surface of the wafer 602 is being processed, for example, when material is being deposited thereon, the carry ring 654 may be configured to be positioned above a carry ring support area that is stepped downward from the wafer support area in the center of the showerhead 606. The top surface of the carry ring 654 is substantially coplanar with the top surface of the wafer 602. The carry ring 654 may include an outer edge side (e.g., an outer radius) of its disk structure and a wafer edge side (e.g., an inner radius) of its disk structure that is closest to the location of the wafer 602. The carry ring 654 may be associated with an inner diameter (ID). The ID may extend to the inner periphery of the carry ring and generally surround the substrate (e.g., wafer 602) in the processing chamber. The wafer edge side of the carry ring 654 may also include a plurality of contact support structures or "tabs" that may be configured to elevate the wafer 602 when the carry ring 654 is held by the spacer 644. The carry ring 654 can include a plurality of tabs, the number of which is selected from a range that supports the wafer 602 during processing. Additional details regarding the tab embodiment are as follows.

[0101] Figure 6B FIG2 is a block diagram illustrating another substrate handling system 632 for performing processing on a wafer 602 according to some embodiments. In some embodiments, a spoke fork 656 can be used to elevate and maintain a carry ring 654 at its process height, for example, to allow deposition on the lower surface (backside) of the wafer 602. Thus, the carry ring 654 can be lifted along with the wafer 602. In some embodiments, the carry ring 654 can be rotated to another station, for example, in a multi-station system.

[0102] Broadly speaking, embodiments disclosed herein are systems for depositing PECVD films on selected sides (front and / or back) of a wafer using dynamic control. Some embodiments may include dual gas flow electrodes for defining a capacitively coupled PECVD system. The system may include a gas flow showerhead (e.g., showerhead 636) and a showerhead 66. In some embodiments, the gas flow base (i.e., showerhead) is a combination of a showerhead and a pedestal that enables deposition on the back side of the wafer. The electrode geometry incorporates features of the showerhead (e.g., gas mixing plenum, holes, hole pattern, anti-gas spray shield) and features of the pedestal. Examples of pedestal features include embedded controlled heaters, a wafer lift mechanism, the ability to hold a plasma suppression ring, and portability. This enables wafer transfer and gas handling with or without RF power from the pedestal.

[0103] In some embodiments, the system may have a wafer lift mechanism that tightly controls the parallelism of the substrate relative to the electrodes. In one example, this can be achieved by setting the lift mechanism (e.g., a spindle or lift pin mechanism) parallel to the two electrodes and controlling manufacturing tolerances. In another example, the lift can be achieved by raising the wafer lift component. This option may not allow for dynamic control of the side where deposition is performed.

[0104] In some configurations, the lift mechanism allows for dynamic control of substrate position during processing (before, during, and after plasma) to control the side of deposition, the profile of deposition, and the properties of the deposited film. The system can further allow for selective activation / deactivation of the side of reactant flow. Reactants can flow on one side, while an inert gas can flow on the other side to suppress deposition and plasma.

[0105] In some embodiments, the gap between the sides of the wafer where plasma / deposition is not desired can be tightly controlled. This distance can be controlled to suppress the plasma. If the distance is not controlled, the wafer may be susceptible to plasma damage. For example, the system may allow a minimum gap of about 2 mm to about 0.5 mm, and in another embodiment about 1 mm to about 0.05 mm (limited by wafer warpage), and such a gap can be controlled. The gap can be controlled based on process conditions.

[0106] In some embodiments, the gas flow base (i.e., showerhead) can achieve, but is not limited to: (a) thermal stabilization of the wafer to the processing temperature before processing; (b) selective design of the hole pattern on the showerhead to selectively deposit films on different areas of the backside of the wafer; (c) attachable replaceable rings to achieve appropriate plasma confinement and hole pattern; (d) stable wafer transfer mechanism within the chamber for transferring the wafer out to another chamber or wafer boat - such as lift pins, RF coupling features, minimum contact arrays; (e) implementation of gas mixing features such as internal plenums, baffles, and manifold line openings; and (f) provision of compartments in the gas flow base (i.e., showerhead) to enable selective gas flow to different areas of the backside of the wafer, with flow rate control by flow controllers and / or multiple plenums.

[0107] In another embodiment, dynamic gap control using a wafer lift mechanism is used to achieve: (a) control of the distance from the deposition or reactant flow electrode to the side or middle of the wafer where deposition is desired, allowing deposition on both sides; and (b) a lift mechanism that dynamically controls the distance during the process (before plasma, during plasma, after plasma) to control the side of deposition, the deposition profile, and the deposited film properties. In another embodiment, for deposition modes used to deposit on the back side of the wafer, film edge exclusion control is highly desirable to avoid overlay issues associated with lithography. The lift mechanism used in this system is accomplished by a carrier ring 654 that has design features for shielding deposition on the edge. This specifies edge exclusion control through the design and shape of the carrier ring.

[0108] Figure 7A A cross-sectional view of an edge region of the nozzle seat 606 is shown. This view provides a cross-sectional representation of the carrier ring 654, which has a carrier ring inner radius 654a and a carrier ring outer radius 654b. In some embodiments, the carrier ring 654 includes a support extension 654c that extends below the substantially flat surface of the carrier ring 654.

[0109] The support extensions 654c are configured to mate with and reside within support surfaces defined in the top surface of the spacers 644. The support surfaces provide complementary mating surfaces to the support extensions 654c, thereby preventing the carry ring 654 from sliding or moving when supported by the spacers 644. Although three spacers 644 are shown in FIG13B, it is contemplated that any number of spacers may be provided so long as the carry ring can be supported substantially parallel to the surface of the showerhead 606 and the spacers are defined to support the wafer 602 in a spaced relationship with the top surface of the pedestal 606.

[0110] It is further shown that the top surface of the nozzle holder 606 includes a hole pattern 606a distributed across the entire surface to provide uniform distribution and output of gas during operation. In one embodiment, the hole pattern 606a is distributed as a plurality of concentric rings that begin at the center of the top surface of the nozzle holder 606 and extend to the outer periphery of the nozzle holder 606. At least one hole pattern 606a is disposed at an edge hole region 607 of the hole pattern, and the orifices defined in the edge hole region 607 are preferably angled so as to provide gas non-perpendicularly to the nozzle holder 606 surface.

[0111] In one example, the angle or tilt of the orifices in the edge hole region 607 is defined to be tilted or angled away from the center of the showerhead 106. In one embodiment, the angle is approximately 45° from horizontal. In other embodiments, the angle can vary from 20° from horizontal to approximately 80° from horizontal. In one embodiment, by providing angled orifices in the edge hole region 607, additional distribution of process gases can be provided during deposition on the backside of the wafer 602. In one embodiment, the remaining orifices 606d of the hole pattern 606a are oriented substantially perpendicular to the surface of the showerhead 106 and directed toward the underside of the wafer 602.

[0112] 13B shows that when wafer 602 is held by carrier ring 654, the edge of wafer 602 will be located on an edge region closer to carrier ring inner radius 654a of carrier ring 654. When positioned using spacer 644, the surface of showerhead 636 facing the top surface of wafer 602 can be substantially close to prevent deposition during a mode in which deposition is performed on the back side of wafer 602.

[0113] For example, the distance between the top of the wafer 602 and the surface of the showerhead 636 is preferably between about 2 mm and about 0.5 mm, and in some embodiments, about 1 mm to about 0.5 mm, depending on the warpage of the wafer. That is, if the wafer is significantly warped, the spacing will be about 0.5 mm or greater. If the wafer has not yet significantly warped, the spacing may be less than about 0.5 mm. In one embodiment, it is preferred that the spacing be minimized to prevent deposition on the top side of the substrate when a material layer is being deposited on the back side of the substrate. In some embodiments, the showerhead 636 is configured to supply an inert gas flow over the top side of the wafer 602 during deposition on the back side of the substrate and supplying deposition gas through the showerhead 606.

[0114] Any suitable chamber may be used to implement the disclosed embodiments. Exemplary deposition apparatus include various systems, such as the and or any of a variety of other commercially available processing systems.

[0115] Figure 8Schematic diagram of a processing system suitable for performing a deposition process (e.g., a front-side deposition process) according to embodiments. System 800 includes a transfer module 803. Transfer module 803 provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between various reactor modules. Mounted on transfer module 803 is a multi-station reactor 809 capable of performing ALD, processing, and CVD according to various embodiments. Multi-station reactor 809 may include a plurality of stations 811, 813, 815, and 817, which may perform operations sequentially according to the disclosed embodiments. A station may include a heated pedestal or substrate support, one or more gas inlets or showerheads, or a distribution plate.

[0116] The transfer module 803 may also be mounted with one or more single-station or multi-station modules 807 capable of performing plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations. The modules may also be used for various processes, for example, to prepare substrates for deposition processes. The system 800 also includes one or more wafer source modules 801, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 819 may first move the wafers from the source module 801 to the load lock 821. The wafer transfer device (typically a robotic arm unit) in the transfer module 803 moves the wafers from the load lock 821 to the modules mounted on the transfer module 803 and moves the wafers between these modules.

[0117] In various embodiments, a system controller 842 is used to control process conditions during deposition. The controller 842 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0118] The controller 842 can control all activities of the deposition apparatus. The system controller 842 runs system control software, which includes an instruction set for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level, wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the controller 842 may be used.

[0119] The depicted embodiment includes a user interface associated with the controller 842. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, or the like.

[0120] The system control logic can be configured in any suitable manner. Generally, the logic can be designed or configured in hardware and / or software. The instructions for controlling the driver circuits can be hard-coded or provided as software. The instructions can be provided through "programming." Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application-specific integrated circuits, and other devices having specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general-purpose processor. The system control software can be encoded in any suitable computer-readable programming language.

[0121] The computer program code for controlling the germanium-containing reducing agent pulses, hydrogen gas flow, and tungsten-containing precursor pulses, as well as other processes in the process sequence, can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by a processor to perform the tasks identified in the program. As also indicated, the program code can be hard-coded.

[0122] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using a user interface.

[0123] Signals for monitoring the process may be provided via analog and / or digital input connections of the system controller 842. Signals for controlling the process may be output via analog and digital output connections of the apparatus 800.

[0124] The system software can be designed or configured in various ways. For example, a plurality of chamber component subroutines or control objects can be written to control the operation of the chamber components required to perform a deposition process according to the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0125] In some embodiments, the system controller 842 is part of a system that can be part of the above-described embodiments. Such a system includes a semiconductor processing apparatus that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices to control the operation of these systems before, during, or after processing of semiconductor wafers or substrates. The electronic devices can be referred to as "controllers" and can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 842 can be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, plasma pulse frequency settings, fluid delivery settings, position and operation settings, wafer entry and exit tools and other transport tools and / or transport of load locks connected to or interfaced with a particular system. System Controller

[0126] In a broad sense, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, can perform cleaning operations, can perform endpoint measurements, etc. Such a controller can be used in any device described herein or used together with it. The integrated circuit can include a chip, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software) in the form of firmware. The program instructions can be instructions delivered to the controller or system in the form of various settings (or program files), and different settings (or program files) define the operating parameters for performing a specific process on or for a semiconductor wafer. In some embodiments, the operating parameters can be a part of a recipe defined by a process engineer to complete one or more (seed) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips of a wafer.

[0127] The system controller can be part of or coupled to a computer that is integrated with, coupled to, or connected to the system via a network, or a combination thereof. For example, the system controller can be in the "cloud" or all or part of a main computer system in a wafer fab, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance metrics across multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some embodiments, a remote computer (e.g., a server) can provide process recipes to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that these parameters can be specific to the type of process to be performed and the type of tool the controller is configured to connect to or control. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work toward a common goal (e.g., the process and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits within the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the process within the chamber.

[0128] Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0129] As described above, depending on the process step or steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0130] The system controller may include different programs. A substrate positioning program may include program code for controlling chamber components used to load a substrate onto a pedestal or chuck and control the spacing between the substrate and other components of the chamber, such as a gas inlet and / or a target. A process gas control program may include code for controlling gas composition, flow rate, pulse timing, and optionally, for flowing gas into the chamber to stabilize the pressure in the chamber prior to deposition. A pressure control program may include code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in an exhaust system in the chamber. A heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to the wafer chuck.

[0131] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the susceptor or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired process conditions.

[0132] The foregoing describes implementations of the present invention as implemented in single- or multi-chamber semiconductor processing tools. The apparatus and processes described herein can be used in conjunction with photolithographic patterning tools or processes, for example, to prepare or manufacture semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following steps, each of which utilizes multiple available tools: (1) coating a workpiece, i.e., a substrate, with photoresist using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or UV curing tool; (3) exposing the photoresist to visible light or UV light or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet cleaning station; (5) transferring the resist pattern to an underlying film or workpiece using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. in conclusion

[0133] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the embodiments of the present invention. Therefore, the embodiments of the present invention are to be considered as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method for processing a substrate during electronic device manufacturing, the method comprising: (a) depositing one or more front-side layers on the front side of the substrate, wherein the one or more front-side layers induce warping in the substrate; (b) depositing a first bulk backside layer on the backside of the substrate, wherein the first bulk backside layer reduces the warpage in the substrate; (c) depositing a crack-stopping backside layer over the first backside layer; and (d) depositing a second bulk backside layer over the second backside layer, wherein the second bulk backside layer further reduces the warpage in the substrate. 2 . The method of claim 1 , wherein the first bulk backside layer, the crack-stop backside layer, and the second bulk backside layer together comprise a backside stack, and wherein the backside stack has a thickness of approximately 2 μm to 15 μm. 3 . The method of claim 1 , wherein the first body backside layer and the second body backside layer each have a thickness of about 3 μm or less. The method of claim 1 , wherein the first body backside layer comprises silicon nitride. The method of claim 1 , wherein the first body backside layer has an intrinsic internal stress magnitude of approximately 100 MPa to 1000 MPa. 6 . The method of claim 1 , wherein the crack-stop backside layer comprises silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

7. The method of claim 1, wherein the crack-stop backside layer has a density of about 2 g / cm2 to 3.5 g / cm2.

8. The method of claim 1, wherein the crack-stop backside layer has a thickness of about 2 μm or less.

9. The method of claim 1, wherein the crack-stop backside layer has an elastic modulus of about 50 GPa to 250 GPa.

10. The method of claim 1, wherein the warpage of the substrate is about 300 μm or more. The method of claim 1 , wherein at least one of the one or more front-side layers comprises a hard mask.

12. The method of claim 1, wherein the one or more front-side layers comprise a stack of about 100 or more alternating layers.

13. The method of claim 12, wherein the stack comprises alternating oxide and nitride or polysilicon layers.

14. The method of claim 1, wherein the one or more front-side layers have a first type of internal stress, and wherein the first bulk back-side layer has the first type of internal stress.

15. An apparatus for semiconductor processing, the apparatus comprising: processing room; a substrate support within the processing chamber; sprinkler; a gas source fluidly connected to the showerhead; as well as A controller configured to cause: (i) receiving a substrate comprising one or more front-side layers, the one or more front-side layers causing warpage in the substrate; (ii) depositing a first bulk backside layer on the backside of the substrate, the first backside layer reducing warpage in the substrate; (iii) depositing a crack-stopping backside layer over said first backside layer; as well as (iv) depositing a second bulk backside layer over the second backside layer, wherein the second backside layer further reduces the warpage in the substrate.

16. The apparatus of claim 15, wherein the warp in the substrate is about 300 μm or greater.

17. The device of claim 15, wherein at least one of the one or more front-side layers is a hard mask.

18. The device of claim 15, wherein the one or more front-side layers comprise a stack of about 100 or more alternating layers.

19. The device of claim 15, wherein the first bulk backside layer, the crack-stop backside layer, and the second bulk backside layer together comprise a backside stack, and wherein the backside stack has a thickness of approximately 2 μm to 15 μm.

20. The device of claim 15, wherein the first body backside layer and the second body backside layer each have a thickness of about 3 μm or less.

21. The device of claim 15, wherein the first body backside layer comprises silicon nitride.

22. The device of claim 15, wherein the first body backside layer has an intrinsic internal stress of about -500 MPa to 500 MPa.

23. The device of claim 15, wherein the crack-stop backside layer has a density of about 2 g / cm2 to 3.5 g / cm2.

24. The device of claim 15, wherein the crack-stop backside layer has a thickness of about 2 μm or less.

25. The device of claim 15, wherein the crack-stop backside layer has an elastic modulus of about 50 GPa to 250 GPa.

26. The device of claim 15, wherein the crack-stop backside layer comprises silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

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