Method for preparing half-bridge strain gauge by using (111) surface self-stopping wet etching process
Through the (111) surface self-stop wet etching process, the problem of thickness unevenness in the manufacture of silicon strain gauges was solved, high-yield and low-cost silicon strain gauge preparation was achieved, and the sensitivity of the sensor was improved.
Patent Information
- Application Number
- CN202510806491.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-09-19
AI Technical Summary
In existing silicon strain gauge manufacturing processes, thickness non-uniformity during back etching of the strain gauge is difficult to control, resulting in low yield, high cost, or reduced sensitivity.
A (111) surface self-stop wet etching process is adopted. Boron ion doping and oxide layer deposition are performed on the silicon wafer surface. In combination with photolithography, ICP etching and DRIE etching, the (111) surface at the bottom of the strain gauge is used to achieve self-stop etching and control the thickness uniformity of the strain gauge.
This improves the success rate of the strain gauge manufacturing process, ensures the uniformity of strain gauge thickness, reduces costs and improves sensitivity.
Smart Images
Figure CN120664498A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of micromechanical system (MEMS) processing in the field of semiconductor technology, and in particular to a method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process. Background Art
[0002] Strain gauges, sensitive components that convert strain signals into electrical signals, are widely used in sensors, such as multi-dimensional force / torque sensors and pressure sensors. Currently, there are two main types of strain gauges in use: metal strain gauges and semiconductor silicon strain gauges. Traditional metal strain gauges are the most widely used. Metal strain gauges have mature manufacturing processes and are relatively low in cost. However, due to the inherently low gauge factor (GF) of metal, metal strain gauge sensors are not very sensitive. Furthermore, their large size makes further miniaturization difficult. In contrast, silicon strain gauges, made of doped semiconductor silicon, have a higher gauge factor (GF), resulting in higher sensitivity. Furthermore, because silicon strain gauge manufacturing processes are compatible with micromechanical systems (MEMS) processing, silicon strain gauges can be 2-3 times smaller than metal strain gauges, offering great potential for application in a wide range of small sensors. However, due to the lack of mature manufacturing processes for silicon strain gauges combined with MEMS processing, their cost remains high. Currently, there are three main methods for manufacturing silicon strain gauges.
[0003] The first typical process is to manufacture on a (100) silicon wafer. First, ion implantation or diffusion process is performed on the silicon wafer to dope the semiconductor silicon. After doping, the structure of the silicon strain gauge is directly etched on the silicon wafer through the DRIE etching process. The thickness of the silicon strain gauge is defined by the depth of the etching. Then, a metal pad is formed at the corresponding position of the silicon strain gauge structure through the sputtering stripping process. Then, the back side is thinned by chemical mechanical polishing (CMP) to reduce the time of the subsequent wet etching process. Finally, the front side of the etched silicon strain gauge structure is coated with black wax for protection, and then the silicon wafer is placed in a KOH solution for wet etching. The purpose is to etch and thin the silicon wafer on the entire surface. When the silicon wafer is thinned to the corresponding thickness, the strain gauge structure is exposed on the back side, and the etching is stopped at this time. After washing off the black wax, the individual strain gauges are separated. The main problem with this manufacturing method is that when the back side of the strain gauge is etched, the uniformity of the strain gauge thickness is difficult to ensure, resulting in a low yield rate of the wafer. Specifically, during back-side etching and thinning, due to the height difference of the original silicon wafer and the unevenness of etching, some strain gauges on the same wafer have been corroded to the corresponding structural positions, while some strain gauges have not yet been corroded to the corresponding positions.
[0004] The second manufacturing method is to manufacture on an SOI wafer with a (100) surface as the device layer. The main improvement of this manufacturing process is to use the buried oxide layer of the SOI wafer to improve the backside etching process. The buried oxide layer can achieve self-stopping during etching, thereby improving the thickness unevenness problem when etching the back side of the strain gauge. However, the disadvantage of this method is that the cost of the SOI wafer is relatively high, making it difficult to achieve the effect of reducing the cost of the strain gauge.
[0005] The third typical manufacturing method is to apply the bonding process to the manufacture of silicon strain gauges. The specific process is to first bond the (100) silicon wafer to the alkali-free glass, and then thin the front silicon wafer to 5~10μm for the subsequent formation of the strain gauge structure. Then, after the front silicon is doped on the entire surface, the strain gauge structure is etched out on the front silicon by deep reactive ion etching (DRIE). After the metal pad is made on the corresponding structure, the back glass is thinned by CMP. After thinning to 20~50μm, the individual strain gauges are separated by dicing. This method avoids the back corrosion process, thereby improving the yield to a certain extent. However, due to the existence of the entire glass substrate on the back of the individual strain gauges, the sensitivity of the strain gauge is greatly affected. Summary of the Invention
[0006] The purpose of the present invention is to solve the above-mentioned problems in the prior art and provide a method for manufacturing a silicon strain gauge using a (111) silicon wafer and controlling the thickness uniformity of the silicon strain gauge during wet etching by using the (111) surface self-stop etching mechanism.
[0007] In order to achieve the above object, the present invention adopts the following technical solutions:
[0008] A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process comprises the following steps:
[0009] (a) Boron ion doping is performed on the surface of a silicon wafer with a (111) crystal orientation to form a semiconductor doped layer;
[0010] (b) depositing a first oxide layer on the front side of the silicon wafer;
[0011] (c) The pad area is defined by photolithography, the first oxide layer in the pad area is removed by ICP etching, and metal is sputtered and stripped to form a metal pad;
[0012] (d) depositing a second oxide layer on the front side of the silicon wafer;
[0013] (e) The strain gauge structure area is defined by photolithography, and the first and second oxide layers in the non-strain gauge structure area are removed by ICP etching to expose the underlying silicon;
[0014] (f) DRIE deep silicon etching is performed on the exposed silicon area to define the strain gauge thickness;
[0015] (g) After removing the photoresist, a third oxide layer is deposited to cover the front side of the silicon wafer;
[0016] (h) ICP etching removes the third oxide layer in the non-strain gauge area, while retaining the third oxide layer on the sidewall of the strain gauge.
[0017] (i) DRIE deep silicon etching of the silicon in the non-strain gauge structure area, with the etching depth satisfying: etching depth × tan19.47° > the longitudinal spacing distance of the strain gauge piezoresistive strips;
[0018] (j) ICP etching removes the second oxide layer on the pad surface to expose the metal pad;
[0019] (k) The silicon wafer is wet-etched in an alkaline anisotropic etching solution. The silicon underneath the strain gauge is hollowed out by lateral etching to achieve separation. The (111) crystal plane at the bottom of the strain gauge is used to achieve self-stopping etching and control thickness uniformity.
[0020] The doping process in step (a) is diffusion or ion implantation.
[0021] The first oxide layer, the second oxide layer and the third oxide layer are all deposited by LPCVD.
[0022] The first oxide layer has a thickness of 0.2 to 0.5 μm; the second oxide layer has a thickness of 0.5 to 1.5 μm; and the third oxide layer has a thickness of 0.2 to 0.4 μm.
[0023] In step (f), the etching depth is 10 to 50 μm.
[0024] The metal pad is made of aluminum or gold.
[0025] The alkaline anisotropic etching solution in step (k) is KOH or TMAH solution.
[0026] In the present invention, the strain gauge piezoresistive strips are arranged along the (110) crystal orientation of the silicon wafer, and the longitudinal sidewalls exposed during wet etching are parallel to the (211) crystal plane.
[0027] A half-bridge strain gauge prepared by the above method.
[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0029] The present invention realizes self-stopping corrosion through the silicon (111) surface and protects the strain gauge structure area by depositing an oxide layer. When etching is performed in an alkaline anisotropic etching solution such as KOH, the bottom of the strain gauge is parallel to the (111) surface, thereby achieving the effect of self-stopping corrosion. The process flow of the present invention can ensure the uniformity of the overall thickness of the strain gauge, thereby improving the success rate of the strain gauge manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a schematic diagram of the cross-section and three-dimensional structure of the silicon wafer after the silicon wafer surface is doped and oxidized to form the first oxide layer.
[0031] Figure 2 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after ICP etching the pad structure on the silicon wafer surface and sputtering the metal pad.
[0032] Figure 3 This is a schematic cross-sectional view and a schematic three-dimensional structure view of a silicon wafer after the second oxide layer is deposited on its surface.
[0033] Figure 4 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after photolithography of the strain gauge structure area and ICP removal of silicon oxide in the non-strain gauge structure area on the front of the silicon wafer.
[0034] Figure 5 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after DRIE etching of doped silicon and silicon in the non-strain gauge structure area on the front side of the silicon wafer.
[0035] Figure 6 This is a schematic diagram of the cross-section and three-dimensional structure of the silicon wafer after the DRIE process and the cleaning of the residual photoresist.
[0036] Figure 7 This is a schematic diagram of the cross-section and three-dimensional structure of the silicon wafer after the third oxide layer is deposited on the front side of the silicon wafer.
[0037] Figure 8 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after the entire front surface of the silicon wafer is ICP etched.
[0038] Figure 9 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after front-side DRIE etching.
[0039] Figure 10 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after the second oxide layer is etched on the entire front surface of the silicon wafer by ICP.
[0040] Figure 11 Schematic diagram of the cross section and three-dimensional structure of the silicon wafer after wet etching.
[0041] Figure 12 This is a three-dimensional structural diagram and bottom schematic diagram of the silicon wafer after wet etching. DETAILED DESCRIPTION
[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.
[0043] The process of the present invention primarily involves: after boron ion diffusion forms a semiconductor doping layer, an oxide layer is deposited on the front surface of the silicon wafer to protect the strain gauge structure during subsequent etching processes. Then, photolithography of the pad structure is performed, and the oxide layer in the pad structure portion is etched away. Metal is then sputtered and stripped to form the pad. Another oxide layer is deposited on the silicon wafer surface, also used to protect the strain gauge structure area. Photolithography of the strain gauge structure area is then continued, and ICP etching is performed on the front surface to remove the oxide layer in the strain gauge structure area. DRIE deep silicon etching is then performed to define the overall thickness of the strain gauge. After debonding, an oxide layer is deposited on the surface of the silicon wafer. This oxide layer protects the side of the strain gauge in the subsequent etching process. The entire silicon wafer is then subjected to ICP to remove the oxide layer in the non-strain gauge structure area. The entire surface is then DRIE deep silicon etched for subsequent strain gauge corrosion separation. The entire front surface is then subjected to ICP to remove the oxide layer on the pad surface. The silicon wafer is then placed in the etching solution for corrosion separation. The thickness of the silicon strain gauge is controlled by the self-stopping etching of the (111) surface at the bottom of the strain gauge.
[0044] The silicon wafer 100 used in this embodiment is a (111) crystal orientation silicon wafer. After cleaning it, the following operations are performed:
[0045] Step 1: First, boron ion doping is performed on the surface of the silicon wafer 100. The doping process is full-surface diffusion or ion implantation to form a silicon doping layer 101. After doping on the front side, the first oxide layer 1031 is deposited on the front side by LPCVD with a thickness of 0.2~0.5μm. This oxide layer is used to protect the strain gauge structure area in the future. The silicon wafer structure after this process is completed is as follows Figure 1 shown.
[0046] Step 2: The strain gauge pad structure is photolithographically processed on the front of the silicon wafer 100. After photolithography, ICP removes the oxide layer on the surface of the pad structure, and performs metal sputtering and stripping to form a metal pad 102. The sputtered metal can be aluminum or gold. The silicon wafer structure after this process is completed is as follows: Figure 2 shown.
[0047] Step 3: LPCVD deposits a second oxide layer 1032 on the front of the silicon wafer 100. The thickness of the second oxide layer is 0.5~1.5μm. This oxide layer is also used to protect the front structure of the strain gauge in subsequent processes. The silicon wafer structure after this process is completed is as follows: Figure 3 shown.
[0048] Step 4: After the strain gauge structure area is photolithographically processed on the front side of the silicon wafer 100, the photoresist 104 protects the strain gauge structure area. The ICP removes the silicon oxide (first oxide layer and second oxide layer) in the non-strain gauge structure area, exposing the silicon in the non-strain gauge structure area. The silicon wafer structure after this process is completed is as follows: Figure 4 shown.
[0049] Step 5: DRIE deep silicon etching is performed on the front side of the silicon wafer 100 to remove the silicon in the non-strain gauge structure area to define the thickness of the strain gauge. The etching depth is 10~50μm. The silicon wafer structure after this process is completed is as follows: Figure 5 shown.
[0050] Step 6: Clean the photoresist on the surface of the silicon wafer 100. The structure of the silicon wafer after this process is completed is as follows: Figure 6 shown.
[0051] Step 7: LPCVD a third oxide layer 1033 on the front of the silicon wafer 100. At this point, the front of the silicon wafer is completely covered by the third oxide layer 1033. This oxide layer is used to protect the sidewalls of the strain gauge structure area during the subsequent etching process. The thickness of the oxide layer is 0.2~0.4μm. The silicon wafer structure after this process is completed is as follows: Figure 7 shown.
[0052] Step 8: ICP etching is performed on the entire front surface of the silicon wafer 100 to remove the third oxide layer 1033 in the non-strain gauge structure area, exposing the silicon in the non-strain gauge structure area on the silicon wafer while retaining the third oxide layer 1033 on the sidewall of the strain gauge. Since the second oxide layer 1032 has been deposited on the front surface of the strain gauge structure area in the previous process, the second oxide layer 1032 is still present on the surface of the strain gauge structure area after ICP etching. The structure of the silicon wafer after this process is completed is as follows: Figure 8 shown.
[0053] Step 9: DRIE deep silicon etching is performed on the front side of the silicon wafer 100 to etch the silicon in the non-strain gauge structure area. The etching depth must meet the following requirements: etching depth × tan19.47° > the longitudinal spacing distance of the strain gauge piezoresistive strips, so as to achieve separation during subsequent strain gauge etching. The silicon wafer structure after this process is completed is as follows: Figure 9 shown.
[0054] Step 10: Perform an ICP process on the front side of the silicon wafer 100 to completely etch away the second oxide layer 1032 on the pad surface to expose the pad. Since the first oxide layer 1031 was deposited on the strain gauge surface in the previous process, the strain gauge structure area still has an oxide layer protection, which is used to protect the strain gauge structure in the subsequent etching process. The silicon wafer structure after this process is completed is as follows: Figure 10 shown.
[0055] Step 11: Place the entire wafer in an alkaline anisotropic etching solution such as KOH for etching. The longitudinal sidewalls of the strain gauge structure are parallel to the (211) plane, so the sidewalls not protected by silicon oxide will be corroded. According to the wet etching theory and the crystal phase distribution of single crystal silicon, on the (111) silicon wafer, when the piezoresistive strip is extended laterally, <110> When the piezoresistive strips are arranged in the same direction, after DRIE etching of the non-strain gauge structure area is completed, the longitudinal side surface of the strain gauge not protected by the oxide layer is parallel to the (211) surface. At this time, the side surface not protected by the oxide layer will be corroded until it reaches the (111) surface intersecting the (211) surface. At this time, according to the crystal orientation relationship between the (211) surface and the (111) surface, when the etching depth × tan19.47° > the longitudinal spacing distance of the piezoresistive strips in the strain gauge structure is satisfied, the silicon at the bottom of the strain gauge structure protected by the deposited oxide layer will be hollowed out, thereby achieving the separation of the strain gauge; at the same time, since the bottom of the strain gauge structure protected by the oxide layer is parallel to the (111) surface, the bottom of the strain gauge structure will achieve self-stop corrosion, thereby ensuring the control of the thickness uniformity of the strain gauge. The silicon wafer structure after this process is completed is as follows: Figure 11 and Figure 12 shown.
[0056] The present invention realizes self-stopping corrosion through the silicon (111) surface and protects the strain gauge structure by depositing an oxide layer. When etching is performed in an alkaline anisotropic etching solution such as KOH, the bottom of the strain gauge is parallel to the (111) surface, thereby achieving a self-stopping corrosion effect. The process flow of the present invention can ensure the uniformity of the overall thickness of the strain gauge, thereby improving the success rate of the strain gauge manufacturing process.
[0057] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.
Claims
1. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process, characterized in that: The following steps are involved: (a) Boron ion doping is performed on the surface of a silicon wafer with a (111) crystal orientation to form a semiconductor doped layer; (b) depositing a first oxide layer on the front side of the silicon wafer; (c) The pad area is defined by photolithography, the first oxide layer in the pad area is removed by ICP etching, and metal is sputtered and stripped to form a metal pad; (d) depositing a second oxide layer on the front side of the silicon wafer; (e) The strain gauge structure area is defined by photolithography, and the first and second oxide layers in the non-strain gauge structure area are removed by ICP etching to expose the underlying silicon; (f) DRIE deep silicon etching is performed on the exposed silicon area to define the strain gauge thickness; (g) After removing the photoresist, a third oxide layer is deposited to cover the front side of the silicon wafer; (h) ICP etching removes the third oxide layer in the non-strain gauge area, while retaining the third oxide layer on the sidewall of the strain gauge. (i) DRIE deep silicon etching of the silicon in the non-strain gauge structure area, with the etching depth satisfying: etching depth × tan19.47° > the longitudinal spacing distance of the strain gauge piezoresistive strips; (j) ICP etching removes the second oxide layer on the pad surface to expose the metal pad; (k) The silicon wafer is wet-etched in an alkaline anisotropic etching solution. The silicon underneath the strain gauge is hollowed out by lateral etching to achieve separation. The (111) crystal plane at the bottom of the strain gauge is used to achieve self-stopping etching and control thickness uniformity.
2. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The doping process in step (a) is diffusion or ion implantation.
3. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The first oxide layer, the second oxide layer and the third oxide layer are all deposited by LPCVD.
4. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The first oxide layer has a thickness of 0.2 to 0.5 μm; the second oxide layer has a thickness of 0.5 to 1.5 μm; and the third oxide layer has a thickness of 0.2 to 0.4 μm.
5. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: In step (f), the etching depth is 10 to 50 μm.
6. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The metal pad is made of aluminum or gold.
7. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The alkaline anisotropic etching solution in step (k) is KOH or TMAH solution.
8. A method for preparing a half-bridge strain gauge using a (111) surface self-stop wet etching process as claimed in claim 1, characterized in that: The piezoresistive strips of the strain gauge are arranged along the (110) crystal direction of the silicon wafer, and the longitudinal sidewalls exposed during wet etching are parallel to the (211) crystal plane.
9. A half-bridge strain gauge prepared by the method according to any one of claims 1 to 8.