Preparation method and application of mixed InP / Si optical chip

Abstract

The invention provides a preparation method and application of a mixed InP / Si optical chip. A P-type InGaAs layer is arranged on the mixed InP / Si optical chip. According to the mixed InP / Si optical chip, the P-type InGaAs layer is subjected to primary epitaxial growth and then is subjected to doping diffusion to improve the doping concentration of the P-type InGaAs layer, so that the doping concentration of the P-type InGaAs layer is greater than or equal to 2 * 10 < 20 > / cm < 3 >, the surface roughness of the P-type InGaAs layer can be effectively controlled, the contact resistance of the P-type InGaAs layer 445 can be effectively reduced, and the bandwidth of the mixed InP / Si optical chip can be remarkably improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to a preparation method and application of a hybrid InP / Si optical chip. Background Art

[0002] With the development of new services and applications such as cloud computing, mobile internet, and video, advances in optical communication technology are becoming increasingly important. As a key component in optical communication equipment, optical modules enable photoelectric signal conversion. As optical communication technology evolves, the data transmission rate of these modules continues to increase. Summary of the Invention

[0003] The present disclosure provides a preparation method and application of a hybrid InP / Si optical chip, which meets the high bandwidth requirements of optical modules.

[0004] In a first aspect, the present disclosure provides a method for preparing a hybrid InP / Si optical chip, wherein the hybrid InP / Si optical chip is used to modulate and generate an optical signal, the preparation method comprising:

[0005] forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer;

[0006] forming a Si waveguide layer above the BOX layer, and etching the Si waveguide layer to form an input Si waveguide and an output Si waveguide, with a gap between the input Si waveguide and the output Si waveguide;

[0007] forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area of ​​the Si waveguide layer;

[0008] An InP bare chip is arranged above the first SiO2 layer, the InP bare chip including a second substrate, a P-type InGaAs layer, a p-InP layer, an i-InP layer, a quantum dot layer and an n-InP layer stacked in sequence, and the first SiO2 layer is bonded to the n-InP layer;

[0009] removing the second substrate and etching the InP die to form an InP waveguide;

[0010] forming a second SiO2 layer on a side of the InP waveguide, wherein the second SiO2 layer wraps the InP waveguide;

[0011] A window is formed on the second SiO2 layer, wherein the bottom of the window extends to the P-type InGaAs layer;

[0012] The P-type InGaAs layer exposed in the window is doped and diffused, and the doping concentration of the P-type InGaAs layer after doping and diffusion is greater than or equal to 2×10 20 / cm 3 ;

[0013] An electrode layer is formed on the doped and diffused P-type InGaAs layer.

[0014] In a second aspect, the present disclosure provides a hybrid InP / Si optical chip, comprising:

[0015] a first substrate, comprising a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer;

[0016] a first SiO2 layer located above the first substrate; a Si waveguide is provided in the first SiO2 layer;

[0017] An InP waveguide is provided above the first SiO2 layer; wherein the InP waveguide includes an n-InP layer, a quantum hydrazine layer, an i-InP layer, a p-InP layer, and a p-type InGaAs layer stacked in sequence, the n-InP layer is bonded to the first SiO2 layer, and the p-type InGaAs layer is doped and diffused;

[0018] A second SiO2 layer is provided to wrap around the side of the InP waveguide;

[0019] An electrode layer is disposed on top of the InP waveguide.

[0020] In a third aspect, the present disclosure provides an optical module, comprising:

[0021] circuit boards;

[0022] a light source, electrically connected to the circuit board, for emitting light that does not carry a signal;

[0023] a hybrid InP / Si optical chip, electrically connected to the circuit board, for modulating light that does not carry a signal to generate an optical signal;

[0024] Wherein, the hybrid InP / Si optical chip is the hybrid InP / Si optical chip prepared by the preparation method described in the first aspect or the hybrid InP / Si optical chip described in the second aspect.

[0025] In the hybrid InP / Si optical chip, the method for preparing the hybrid InP / Si optical chip, and the optical module provided by the present disclosure, the hybrid InP / Si optical chip includes a P-type InGaAs layer. After the P-type InGaAs layer is epitaxially grown once, doping diffusion is performed to increase the doping concentration of the P-type InGaAs layer 445, so that the doping concentration of the P-type InGaAs layer 445 is greater than or equal to 2×1020 / cm 3 , which can effectively control the surface roughness of the P-type InGaAs layer 445 and effectively reduce the contact resistance of the P-type InGaAs layer 445 . BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions of the present disclosure, the following briefly describes the drawings used in some embodiments of the present disclosure. Obviously, the drawings described below are merely illustrations of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0027] Figure 1 A partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure;

[0028] Figure 2 A partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0029] Figure 3 A structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0030] Figure 4 An exploded view of an optical module provided according to some embodiments of the present disclosure;

[0031] Figure 5 A schematic diagram of the internal structure of an optical module provided according to some embodiments of the present disclosure;

[0032] Figure 6 A schematic diagram of the layout of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure;

[0033] Figure 7 is a cross-sectional view of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure;

[0034] Figure 8 A schematic diagram of energy bands after an electrode is in contact with a P-type InGaAs layer according to some embodiments of the present disclosure;

[0035] Figure 9 is a relationship diagram between contact resistivity and doping concentration in a P-type InGaAs layer according to some embodiments of the present disclosure;

[0036] Figure 10 A schematic diagram of a method for preparing a hybrid / Si optical chip according to some embodiments of the present disclosure Figure 1 ;

[0037] Figure 11 A schematic diagram of a method for preparing a hybrid / Si optical chip according to some embodiments of the present disclosure Figure 2 ;

[0038] Figure 12 A schematic diagram of a method for preparing a hybrid / Si optical chip according to some embodiments of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0039] In optical communication technology, to establish information transmission between information processing devices, it is necessary to load the information onto light and use the propagation of light to achieve information transmission. Here, the light loaded with information is an optical signal. When transmitting optical signals in information transmission equipment, they can reduce the loss of optical power, thereby achieving high-speed, long-distance, and low-cost information transmission. The signals that information processing equipment can recognize and process are electrical signals. Information processing equipment typically includes optical network terminals (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., and information transmission equipment typically includes optical fibers and third-party coupling waveguides.

[0040] Optical modules can convert optical signals into electrical signals between information processing devices and information transmission devices. For example, at least one of the optical signal input or output ends of an optical module is connected to an optical fiber, and at least one of the electrical signal input or output ends of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber. Because multiple information processing devices can transmit information via electrical signals, at least one of the multiple information processing devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is referred to as the optical module's host computer. Furthermore, the optical signal input or output end of the optical module can be referred to as an optical port, and the electrical signal input or output end of the optical module can be referred to as an electrical port.

[0041] Figure 1 FIG. 1 is a partial structural diagram of an optical communication system provided according to some embodiments of the present disclosure. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 and a network cable 103 .

[0042] One end of optical fiber 101 extends toward remote information processing device 1000, and the other end of optical fiber 101 is connected to optical module 200 through the optical port of optical module 200. Optical signals can be totally reflected in optical fiber 101, and the propagation of the optical signal in the direction of total reflection can almost maintain the original optical power. The optical signal undergoes multiple total reflections in optical fiber 101 to transmit the optical signal from remote information processing device 1000 to optical module 200, and vice versa, thereby achieving long-distance, low-power information transmission.

[0043] The optical communication system may include one or more optical fibers 101, and the optical fibers 101 may be detachably connected or fixedly connected to the optical module 200. The host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0044] The host computer 100 includes a substantially rectangular housing and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to connect to the optical module 200 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0045] The host computer 100 also includes an external electrical interface that can access an electrical signal network. For example, the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to access a network cable 103 so that the host computer 100 establishes a unidirectional or bidirectional electrical signal connection with the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so that an electrical signal connection is established between the local information processing device 2000 and the host computer 100 via the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 via the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is then transmitted to the remote information processing device 1000 via the optical fiber 101. For example, a first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101. The first optical signal from the optical fiber 101 is transmitted to the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal to the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to the local information processing device 2000. It should be noted that optical modules are tools for converting optical signals into electrical signals. During this conversion process, the information does not change, but the encoding and decoding methods of the information can change.

[0046] In addition to the optical network terminal, the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT), or a data center server.

[0047] Figure 2 This is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. Figure 2 As shown, the host computer 100 further includes a PCB 105 disposed within the housing, a cage 106 disposed on the surface of the PCB 105, a heat sink 107 disposed on the cage 106, and an electrical connector disposed within the cage 106. The electrical connector is configured to connect to the electrical port of the optical module 200; the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.

[0048] The optical module 200 is inserted into the cage 106 of the host computer 100. The cage 106 secures the optical module 200. Heat generated by the optical module 200 is transferred to the cage 106 and then dissipated through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 connects with the electrical connector inside the cage 106, thereby establishing a bidirectional electrical signal connection between the optical module 200 and the host computer 100. Furthermore, the optical port of the optical module 200 connects to the optical fiber 101, thereby establishing a bidirectional optical signal connection between the optical module 200 and the optical fiber 101.

[0049] Figure 3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure, Figure 4 FIG1 is an exploded view of an optical module provided according to some embodiments of the present disclosure. Figure 3 and Figure 4 As shown, the optical module 200 includes a housing, a circuit board 300 disposed within the housing, an optical chip 400, and a light source 500. Exemplarily, the optical chip 400 and the light source 500 are electrically connected to the circuit board 300, and the light output end of the light source 500 is optically coupled to the optical chip 400. In some embodiments, the light output end of the light source 500 is coupled to the optical chip 400 via an optical fiber.

[0050] The housing includes an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square.

[0051] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0052] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.

[0053] The direction of the line connecting the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or may be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 ( Figure 3 The opening 205 is also located at the end of the optical module 200 ( Figure 3 Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200. Opening 204 is an electrical port, through which the gold finger 301 of circuit board 300 extends and is inserted into the electrical connector of host computer 100. Opening 205 is an optical port, configured to receive an external optical fiber 101, thereby connecting optical fiber 101 to optical chip 400 in optical module 200.

[0054] The combined assembly of the upper housing 201 and the lower housing 202 facilitates installation of the circuit board 300, optical modulation chip 900, and light source 1100 within the housing. The upper housing 201 and the lower housing 202 provide encapsulation and protection for these components. Furthermore, during assembly of the circuit board 300, optical chip 400, and light source 500, positioning components, heat dissipation components, and electromagnetic shielding components are easily positioned, facilitating automated production.

[0055] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0056] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0057] For example, the unlocking component 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes a snap-fit ​​component that mates with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 secures the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection between the snap-fit ​​component and the host computer, thereby releasing the optical module 200 from the cage 106 and allowing the optical module 200 to be removed from the cage 106.

[0058] The circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0059] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0060] The circuit board 300 further includes a gold finger 301 formed on the end surface thereof. The gold finger 301 is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106. The gold finger 301 can be provided on only one side of the circuit board 300 (e.g. Figure 4 The top surface shown in FIG300 can also be located on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thus adapting to applications requiring a large number of pins. Gold fingers 301 are configured to establish an electrical connection with a host computer to facilitate power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, and more. Of course, some optical modules also use flexible circuit boards. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement them.

[0061] Figure 5 Schematic diagram of the internal structure of an optical module provided according to some embodiments of the present disclosure. Figure 5As shown, in some embodiments, a light source 500 is disposed on the side of the optical chip 400. Light from the light source 500 is emitted from the side and coupled into the optical chip 400. The light source 500 serves as an external light source for the optical chip 400, and the light emitted by the light source 500 enters the optical chip 400. The light source 500 can optionally be a laser box, which houses a laser. The laser emits light to generate a laser beam. The light source 500 is used to provide the emitted laser light to the optical chip 400. Lasers, with their excellent single-wavelength characteristics and wavelength tuning properties, have become the preferred light source for optical modules and even optical fiber transmission. Other types of light, such as LED light, are generally not used in common optical communication systems. Even if such light sources are used in special optical communication systems, the characteristics of the light source and the chip components differ significantly from those of lasers. This results in significant technical differences between optical modules using lasers and those using other light sources. Those skilled in the art generally do not believe that these two types of optical modules can provide technical inspiration for each other.

[0062] The light emitted by the light source 500 is light that does not carry data and enters the optical chip 400. The optical chip 400 performs phase modulation on it to load the electrical signal into the light to obtain light that carries data, that is, to generate an optical transmission signal, thereby realizing the transmission of the optical signal.

[0063] In some embodiments, the optical chip 400 may be a silicon photonic chip, i.e., the optical chip 400 is formed by packaging silicon materials. The silicon photonic chip includes a Mach-Zehnder modulator (MZM), which integrates a silicon photonic phase modulator (SiPM) for modulating and demodulating optical signals.

[0064] In some embodiments, optical chip 400 may be a hybrid InP / Si optical chip, i.e., a hybrid InP / Si optical chip is formed by combining InP and Si materials in a mixed package. This hybrid InP / Si optical chip combines the performance of InP and Si materials, resulting in superior performance and increased bandwidth for optical chip 400.

[0065] Figure 6 Schematic diagram of the layout of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure. Figure 6As shown, the hybrid InP / Si optical chip includes multiple channels, each of which includes an InP phase modulator 401, a thermal phase adjuster 402, etc. The InP phase modulator 401 is formed by packaging InP materials, and the thermal phase adjuster 402, etc. are formed by packaging silicon materials. The InP phase modulator 401, the thermal phase adjuster 402, etc. are connected to each other via silicon waveguides to form a high-traveling-wave MZM. The hybrid InP / Si optical chip provided by the embodiment of the present disclosure realizes the hybrid integration of Si and InP materials, utilizing InP materials to provide high-speed modulation and Si materials to provide highly integrated silicon optical circuits, enabling the optical chip 400 to combine the high-speed modulation characteristics of InP materials, so that the optical chip 400 can meet the requirements of high baud rate modulation.

[0066] In some embodiments, a hybrid InP / Si optical chip is formed by bonding an InP bare chip formed of InP material to a Si platform formed of Si material, forming an InP phase modulator on the bonded InP bare chip, and forming a silicon optical circuit on the bonded Si platform.

[0067] Figure 7 1 is a cross-sectional view of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure. Figure 7 As shown, the hybrid InP / Si optical chip includes a first substrate 410; a first SiO2 layer 420 is arranged above the first substrate 410, and a Si waveguide layer 430 is arranged in the first SiO2 layer 420; an InP waveguide 440 is arranged above the first SiO2 layer 420; the side of the InP waveguide 440 is wrapped with a second SiO2 layer 450; an electrode layer 460 is arranged on the second SiO2 layer, and the electrode layer 460 extends to the top of the InP waveguide 440 and is electrically connected to the InP waveguide 440.

[0068] In some embodiments, the first substrate 410 includes a substrate layer 411 and a BOX layer 412 . The BOX layer 412 is located above the substrate layer 411 . The BOX layer 412 is connected to the first SiO 2 layer 420 .

[0069] In some embodiments, the substrate layer 411 is made of Si material, and the BOX layer 412 is made of SiO 2 .

[0070] In some embodiments, the first SiO2 layer 420 wraps the Si waveguide layer 430, and the Si waveguide layer 430 includes an input Si waveguide and an output Si waveguide. The input Si waveguide is used to input light to transmit the light to the InP waveguide 440; the output Si waveguide is used to output light to transmit the light output by the InP waveguide 440.

[0071] In some embodiments, the input Si waveguide and the output Si waveguide are spaced apart, with an InP waveguide 440 disposed above the space. The input Si waveguide and the output Si waveguide have a convex cross-section with the top smaller than the bottom, which can be formed by secondary etching.

[0072] In some embodiments, the InP waveguide 440 includes an n-InP layer 441, a quantum dopant layer 442, an i-InP layer 443, a p-InP layer 444, and a p-type InGaAs layer 445. The n-InP layer 441 is bonded to the first SiO2 layer 420, and the quantum dopant layer 442, the i-InP layer 443, the p-InP layer 444, and the p-type InGaAs layer 445 are sequentially disposed above the n-InP layer 441. The p-type InGaAs layer 445 serves as an ohmic contact layer and is electrically connected to the electrode layer 460.

[0073] In some embodiments, the doping concentration of the P-type InGaAs layer 445 is greater than or equal to 2×10 20 / cm 3 The P-type InGaAs layer 445 is doped and diffused. Before the doping diffusion, the P-type InGaAs layer 445 is undoped or the doping concentration of the P-type InGaAs layer 445 is less than 5×10 17 / cm 3 The doping concentration of the P-type InGaAs layer 445 after doping diffusion is greater than 8×10 19 / cm 3 The P-type InGaAs layer 445 is doped with Zn, B, In and other materials to increase the hole concentration of the P-type InGaAs layer. For example, the doping concentration of the P-type InGaAs layer 445 before doping is 0.1×10 17 / cm 3 -5×10 17 / cm 3 The doping concentration of the P-type InGaAs layer 445 after doping diffusion is 2×10 20 / cm 3 -5×10 20 / cm 3 .

[0074] In some embodiments, the width of the quantum dot layer 442 is smaller than the width of the n-InP layer 441 .

[0075] In some embodiments, the i-InP layer 443 includes a first i-InP layer 443a and a second i-InP layer 443b, the p-InP layer 444 includes a first p-InP layer 444a and a second p-InP layer 444b, and the P-type InGaAs layer 445a includes a first P-type InGaAs layer 445a and a second P-type InGaAs layer 445b.

[0076] In some embodiments, a first InP waveguide protrusion 440a and a second InP waveguide protrusion 440b are disposed above the quantum hydrazine layer 442, with a gap between the first InP waveguide protrusion 440a and the second InP waveguide protrusion 440b. The first InP waveguide protrusion 440a includes a first p-type InGaAs layer 445a, a first p-InP layer 444a, and a first i-InP layer 443a stacked in sequence; the second InP waveguide protrusion 440b includes a second p-type InGaAs layer 445b, a second p-InP layer 444b, and a second i-InP layer 443b stacked in sequence.

[0077] In some embodiments, the first P-type InGaAs layer 445a and the second P-type InGaAs layer 445b are doped and diffused respectively. After doping, the doping concentration of the first P-type InGaAs layer 445a and the doping concentration of the second P-type InGaAs layer 445b are both greater than 2×10 20 / cm 3 .

[0078] In some embodiments, the second SiO2 layer 450 is further disposed between the first InP waveguide protrusion 440a and the second InP waveguide protrusion 440b, and the second SiO2 layer 450 wraps around the raised edges of the first InP waveguide protrusion 440a and the raised edges of the second InP waveguide protrusion 440b. During the doping and diffusion process of the first P-type InGaAs layer 445a and the second P-type InGaAs layer 445b, the width of the window opened in the second SiO2 layer 450 is smaller than the width of the first P-type InGaAs layer 445a and also smaller than the width of the second P-type InGaAs layer 445b.

[0079] In some embodiments, the electrode layer 460 includes a first electrode 461 and a second electrode 462, the first electrode 461 is bonded to the top of the first InP waveguide protrusion 440a, the second electrode 462 is bonded to the top of the second InP waveguide protrusion 440b, and the bottom edge of the first electrode 461 and the bottom edge of the second electrode 462 are respectively wrapped by the second SiO2 layer 450.

[0080] Wafer bonding is one of the primary methods for achieving the integration of InP chips and silicon-on-insulator (SOI). Therefore, the quality and roughness of the bonding surface are key factors affecting the packaging and performance of hybrid InP / Si optical chips. The P-type InGaAs layer 445 serves as the P++-InGaAs ohmic contact layer, and the contact resistance of the P-type InGaAs layer 445 limits the bandwidth of the hybrid InP / Si optical chip. The doping concentration of the P-type InGaAs layer 445 directly affects the metal contact resistance: the higher the doping concentration of the P-type InGaAs layer 445, the lower the contact resistance of the P-type InGaAs layer 445. However, the P-type InGaAs layer 445 is typically formed via P-type InGaAs epitaxial growth. As the concentration of the P-type InGaAs increases, the P-type InGaAs epitaxial growth concentration increases, and this increases the surface roughness of the P-type InGaAs layer 445. To ensure the bonding quality of the InP chip, the surface roughness of the P-type InGaAs layer 445 should be less than 1 nm.

[0081] In the embodiment of the present application, after the P-type InGaAs layer 445 is epitaxially grown once, doping diffusion is performed to increase the doping concentration of the P-type InGaAs layer 445, so that the doping concentration of the P-type InGaAs layer 445 is greater than or equal to 2×10 20 / cm 3 , which can effectively control the surface roughness of the P-type InGaAs layer 445 and effectively reduce the contact resistance of the P-type InGaAs layer 445. Furthermore, during the initial growth of the P-type InGaAs layer 445, the doping concentration of the InGaAs epitaxial layer can be kept as low as possible, or the InGaAs epitaxial layer can be left undoped, thereby achieving high-quality growth of the InGaAs epitaxial layer. The doping diffusion treatment performed on the P-type InGaAs layer 445 is a post-growth diffusion treatment of the InGaAs epitaxial layer and does not affect the quality of the quantum dopant layer 442, and thus does not affect other performance and quality of the hybrid InP / Si optical chip, such as the reliability and lifespan of the hybrid InP / Si optical chip.

[0082] Figure 8 Schematic diagram of energy bands after an electrode is in contact with a P-type InGaAs layer according to some embodiments of the present disclosure. Figure 8 As shown in the figure, due to the heavily doped energy level in InGaAs, the Fermi level is close to the valence band of InGaAs. The high free carrier concentration, extremely thin depletion region width, and low surface potential barrier make it easier for electrons to pass through the barrier. The electron passing through the barrier can be expressed by the following formula:

[0083]

[0084] in: J is the current from p-InGaAs to metal; q is the electron charge, N a is the acceptor concentration of InGaAs, in cm -3 υ thx is the thermal velocity of the well; k is the Boltzmann constant; T is the temperature; ε s is the dielectric constant of InGaAs; Φ Bp is the potential barrier between the electrode and the P-type InGaAs layer; m h is the effective mass of the hole, including heavy holes and light holes; h is Planck's constant.

[0085] The contact resistivity (Ω.cm) between the electrode and the P-type InGaAs layer 455 is derived by formula (1): 2 )

[0086]

[0087]

[0088] Combining formula (2) can obtain the relationship between contact resistance and doping concentration in the P-type InGaAs layer. Figure 9 FIG1 is a graph showing the relationship between contact resistivity and doping concentration in a P-type InGaAs layer according to some embodiments of the present disclosure. Figure 9 As shown, when the doping concentration of the P-type InGaAs layer 455 is 2×10 19 / cm 3 When the contact resistance between the electrode and the P-type InGaAs layer 455 is 6×10 -6 Ω.cm 2 When the doping concentration of the P-type InGaAs layer 455 reaches 8×10 19 / cm 3 When the contact resistance between the electrode and the P-type InGaAs layer 455 is 6.2×10 -8 Ω.cm 2 , the contact resistivity between the electrode and the P-type InGaAs layer 455 is two orders of magnitude smaller; when the doping concentration of the P-type InGaAs layer 455 reaches 2×10 20 / cm 3 When the contact resistance between the electrode and the P-type InGaAs layer 455 is 2×10 -8 Ω.cm 2 Therefore, when the doping concentration of the P-type InGaAs layer 455 reaches 8×10 19 / cm 3 , the contact resistivity between the electrode and the P-type InGaAs layer 455 can be ignored, which will significantly improve the bandwidth of the hybrid InP / Si optical chip.

[0089] Based on the hybrid InP / Si optical chip provided in the embodiment of the present disclosure, the embodiment of the present disclosure also provides a method for preparing the hybrid InP / Si optical chip. The method for preparing the hybrid InP / Si optical chip provided in the embodiment of the present disclosure is used to facilitate the preparation of the hybrid InP / Si optical chip provided in the above embodiment. Figure 10 A schematic diagram of a method for preparing a hybrid InP / Si optical chip according to some embodiments of the present disclosure Figure 1 , Figure 11 A schematic diagram of a method for preparing a hybrid InP / Si optical chip according to some embodiments of the present disclosure Figure 2 , Figure 10 and 11 The cross-sectional structures of a hybrid InP / Si optical chip are shown in FIG. Figure 10 and Figure 11 As shown, the present disclosure provides a method for preparing a hybrid InP / Si optical chip, which includes:

[0090] S100: forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer.

[0091] A substrate layer 411 is epitaxially grown, and a BOX layer 412 is grown on the substrate layer 411. The substrate layer 411 is epitaxially grown using Si material, and the BOX layer 412 is epitaxially grown using SiO2 material.

[0092] S200: forming a Si waveguide layer above the BOX layer, and etching the Si waveguide layer to form an input Si waveguide and an output Si waveguide, with a gap between the input Si waveguide and the output Si waveguide.

[0093] A Si waveguide layer 420 is epitaxially grown on the BOX layer 412. A Si waveguide pattern is formed on the Si waveguide layer 420 using a mask, and the Si waveguide is then etched to form the Si waveguide. In some embodiments, the Si waveguide includes an input Si waveguide and an output Si waveguide, with a gap between the input and output Si waveguides. An InP waveguide 440 is positioned above the Si waveguide, spanning the gap between the input and output Si waveguides. The input Si waveguide is used to input light and transmit it to the InP waveguide 440. The output Si waveguide is used to output light and transmit the light output from the InP waveguide 440.

[0094] In some embodiments, the cross-section of the input Si waveguide and the output Si waveguide is a "convex" structure, where the size of the top is smaller than the size of the bottom, and can be formed by secondary etching.

[0095] S300: forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area of ​​the Si waveguide layer.

[0096] The first SiO 2 layer 430 is epitaxially grown so that the first SiO 2 layer 430 wraps around the side of the Si waveguide layer 420 , and the Si waveguide layer 420 is located inside the first SiO 2 layer 430 .

[0097] S400: An InP bare chip is arranged above the first SiO2 layer, the InP bare chip includes a second substrate, a P-type InGaAs layer, a p-InP layer, an i-InP layer, a quantum hydrazine layer and an n-InP layer stacked in sequence, and the first SiO2 layer is bonded to the n-InP layer.

[0098] The InP die is flip-chipped and placed on the first SiO 2 layer 430 , that is, the InP die is flipped upside down on the first SiO 2 layer, so that the n-InP layer 441 on the top of the InP die is bonded to the first SiO 2 layer 430 .

[0099] The InP bare chip includes a second substrate 4401, a P-type InGaAs layer 445, a p-InP layer 444, an i-InP layer 443, a quantum dot layer 442, and an n-InP layer 441 stacked in sequence. The second substrate 4401 is a sample InP substrate.

[0100] S500: removing the second substrate and etching the InP die to form an InP waveguide.

[0101] The second substrate 4401 on the InP die is removed, and the InP die is etched to form the InP waveguide 440 according to the predetermined shape of the InP waveguide 440. In some embodiments, the InP die is etched down to the quantum hydrazine layer 442.

[0102] In some embodiments, etching is performed from the edge of the InP die to the top of the n-InP layer 441 and from the middle of the InP die to the quantum dot layer 442 to form a first InP waveguide protrusion 440a and a second InP waveguide protrusion 440b, with a gap between the first InP waveguide protrusion 440a and the second InP waveguide protrusion 440b. The first InP waveguide protrusion 440a includes a first p-type InGaAs layer 445a, a first p-InP layer 444a, and a first i-InP layer 443a stacked in sequence. The second InP waveguide protrusion 440b includes a second p-type InGaAs layer 445b, a second p-InP layer 444b, and a second i-InP layer 443b stacked in sequence.

[0103] S600: forming a second SiO 2 layer on a side of the InP waveguide, wherein the second SiO 2 layer wraps the InP waveguide.

[0104] A second SiO 2 layer 450 is epitaxially grown on the side of the InP waveguide 440 formed by etching, so that the second SiO 2 layer 450 wraps the InP waveguide 440 . The second SiO 2 layer 450 can protect the InP waveguide 440 .

[0105] In some embodiments, a second SiO 2 layer 450 is epitaxially grown between the first InP waveguide protrusion 440 a and the second InP waveguide protrusion 440 b .

[0106] S700: Opening a window on the second SiO2 layer, wherein the bottom of the window extends to the P-type InGaAs layer.

[0107] A window is opened on the second SiO 2 layer 450 . The window is located above the InP waveguide 440 , and the bottom of the window extends to the P-type InGaAs layer 445 on the InP waveguide 440 .

[0108] In some embodiments, the width of the window is smaller than the width of the P-type InGaAs layer 445 on the InP waveguide 440, so that the edge of the window is located above the P-type InGaAs layer 445, and the InP waveguide 440 is protected by the second SiO2 layer 450 to ensure the performance of the InP waveguide 440.

[0109] In some embodiments, a first window is defined in the second SiO2 layer 450. The first window is located above the first InP waveguide protrusion 440a and extends to the first P-type InGaAs layer 445a. The width of the first window is smaller than the width of the first InP waveguide protrusion 440a, so that the edge of the first window is located above the first P-type InGaAs layer 445a.

[0110] In some embodiments, a second window is defined in the second SiO2 layer 450. The second window is located above the second InP waveguide protrusion 440b and extends to the second P-type InGaAs layer 445b. The width of the second window is smaller than the width of the second InP waveguide protrusion 440b, so that the edge of the second window is located above the second P-type InGaAs layer 445b.

[0111] S800: performing doping diffusion on the P-type InGaAs layer exposed in the window, wherein the doping concentration of the P-type InGaAs layer after doping diffusion is greater than or equal to 2×10 20 / cm 3 .

[0112] The P-type InGaAs layer 450 is doped and diffused through the window to further increase the doping concentration of the P-type InGaAs layer 450 after the P-type InGaAs layer 450 is once grown. In some embodiments, the P-type InGaAs layer 450 is diffused with Zn or the like.

[0113] In some embodiments, the doping concentration of the P-type InGaAs layer after doping diffusion is greater than or equal to 2×10 19 / cm 3 , if the doping concentration of the P-type InGaAs layer after doping diffusion is greater than 8×10 19 / cm 3 , or the doping concentration of the P-type InGaAs layer after doping diffusion is greater than or equal to 2×10 20 / cm 3 .

[0114] In some embodiments, the first P-type InGaAs layer 445a is doped with Zn through the first window, and the doping concentration of the first P-type InGaAs layer 445a after doping is greater than 2×10 20 / cm 3 , for example, the doping concentration of the first P-type InGaAs layer 445a after doping diffusion is 3×10 20 / cm 3 , 5×10 20 / cm 3 wait.

[0115] In some embodiments, the second P-type InGaAs layer 445b is doped with Zn through the second window, and the doping concentration of the second P-type InGaAs layer 445b after doping is greater than 2×10 20 / cm 3 , such as the doping concentration of the second P-type InGaAs layer 445b is 3×10 20 / cm 3 , 5×10 20 / cm 3 wait.

[0116] In some embodiments, before a window is formed in the second SiO2 layer 430, a Si3N4 layer 470 is formed on the second SiO2 layer 430. A window pattern is formed on the Si3N4 layer 470. The window pattern is used to assist in opening the window in the second SiO2 layer 430 and to protect the second SiO2 layer 430 during dopant diffusion. After the dopant diffusion, but before forming the electrode layer 460, the Si3N4 layer 470 is removed.

[0117] S900: forming an electrode layer on the doped and diffused P-type InGaAs layer.

[0118] In some embodiments, the electrode layer 460 is formed by electroplating on the doped and diffused P-type InGaAs layer 450 . The electrodes in the electrode layer 460 are bonded to the P-type InGaAs layer 450 .

[0119] In some embodiments, a first electrode 461 is formed on the first P-type InGaAs layer 445 a after doping diffusion, and a second electrode 462 is formed on the second P-type InGaAs layer 445 b after doping diffusion.

[0120] In some embodiments, the thickness of the first electrode 461 is greater than the height of the second SiO 2 layer 430 extending beyond the top of the first P-type InGaAs layer 445 a , such that the second SiO 2 layer 430 wraps around the bottom edge of the first electrode 461 .

[0121] In some embodiments, the thickness of the second electrode 462 is greater than the height of the second SiO 2 layer 430 extending beyond the top of the second P-type InGaAs layer 445 b , such that the second SiO 2 layer 430 wraps around the bottom edge of the second electrode 462 .

[0122] Figure 12 A schematic diagram of a method for preparing a hybrid / Si optical chip according to some embodiments of the present disclosure Figure 3 , Figure 12 A preparation process of InP bare wafer is shown in FIG. Figure 12 As shown, a p-type InGaAs layer 445 , a p-InP layer 444 , an i-InP layer 443 , a quantum dot layer 442 and an n-InP layer 441 are epitaxially grown in sequence on the second substrate 4401 .

[0123] In some embodiments, the doping concentration of the P-type InGaAs layer 445 on the second substrate 4401 is less than 5×10 17 / cm 3 Or no doping. For example, the doping concentration of the P-type InGaAs layer 445 on the second substrate 4401 is 0.1×10 17 / cm 3 -5×10 17 / cm 3 .

[0124] The specific form of the hybrid InP / Si optical chip prepared by the method for preparing the hybrid InP / Si optical chip provided by the embodiment of the present disclosure can refer to the structure of the hybrid InP / Si optical chip provided by the above embodiment of the present disclosure.

[0125] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a hybrid InP / Si optical chip, characterized in that: The hybrid InP / Si optical chip is used for modulating and generating optical signals, and the preparation method includes: forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer; forming a Si waveguide layer above the BOX layer, and etching the Si waveguide layer to form an input Si waveguide and an output Si waveguide, with a gap between the input Si waveguide and the output Si waveguide; forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area of ​​the Si waveguide layer; An InP bare chip is arranged above the first SiO2 layer, the InP bare chip including a second substrate, a P-type InGaAs layer, a p-InP layer, an i-InP layer, a quantum dot layer and an n-InP layer stacked in sequence, and the first SiO2 layer is bonded to the n-InP layer; removing the second substrate and etching the InP die to form an InP waveguide; forming a second SiO2 layer on a side of the InP waveguide, wherein the second SiO2 layer wraps the InP waveguide; A window is formed on the second SiO2 layer, wherein the bottom of the window extends to the P-type InGaAs layer; The P-type InGaAs layer exposed in the window is doped and diffused, and the doping concentration of the P-type InGaAs layer after doping and diffusion is greater than or equal to 2×10 20 / cm 3 ; An electrode layer is formed on the doped and diffused P-type InGaAs layer.

2. The preparation method according to claim 1, characterized in that The preparation method further comprises: A p-type InGaAs layer, a p-InP layer, an i-InP layer, a quantum doping layer, and an n-InP layer are sequentially grown on the second substrate to form an InP bare chip, wherein the doping concentration of the p-type InGaAs layer is less than 5×10 17 / cm 3 .

3. The preparation method according to claim 1, characterized in that Etching the InP bare chip to form an InP waveguide, comprising: Etching into the quantum hydrazine layer and forming a first InP waveguide protrusion and a second InP waveguide protrusion on the quantum hydrazine layer, with a gap between the first InP waveguide protrusion and the second InP waveguide protrusion; wherein the first InP waveguide protrusion includes a first P-type InGaAs layer, a first p-InP layer and a first i-InP layer; and the second InP waveguide protrusion includes a second P-type InGaAs layer, a second p-InP layer and a second i-InP layer.

4. The preparation method according to claim 3, characterized in that Opening a window on the second SiO2 layer, comprising: A first window is formed on the top of the first InP waveguide protrusion; The width of the first window is smaller than the width of the first InP waveguide protrusion, so that the second SiO2 layer wraps the edge of the top of the first InP waveguide protrusion.

5. The preparation method according to claim 1, characterized in that Before opening a window on the second SiO2 layer, the method further comprises: A Si 3 N 4 layer is formed on the second SiO 2 layer. A window pattern is provided on the Si 3 N 4 layer. The window pattern is used to assist in forming a window on the second SiO 2 layer.

6. A hybrid InP / Si optical chip, characterized in that: include: a first substrate, comprising a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer; a first SiO2 layer located above the first substrate; a Si waveguide is provided in the first SiO2 layer; An InP waveguide is provided above the first SiO2 layer; wherein the InP waveguide includes an n-InP layer, a quantum hydrazine layer, an i-InP layer, a p-InP layer, and a p-type InGaAs layer stacked in sequence, the n-InP layer is bonded to the first SiO2 layer, and the p-type InGaAs layer is doped and diffused; A second SiO2 layer is provided to wrap around the side of the InP waveguide; An electrode layer is disposed on top of the InP waveguide.

7. The hybrid InP / Si optical chip according to claim 6, characterized in that: A first InP waveguide protrusion and a second InP waveguide protrusion are arranged above the quantum hydrazine layer, and there is a gap between the first InP waveguide protrusion and the second InP waveguide protrusion; wherein, the first InP waveguide protrusion includes a first P-type InGaAs layer, a first p-InP layer and a first i-InP layer; the second InP waveguide protrusion includes a second P-type InGaAs layer, a second p-InP layer and a second i-InP layer.

8. The hybrid InP / Si optical chip according to claim 6, characterized in that: Before doping diffusion, the doping concentration of the P-type InGaAs layer is less than 5×10 17 / cm 3 ; After doping diffusion, the doping concentration of the P-type InGaAs layer is greater than or equal to 2×10 20 / cm 3 .

9. The hybrid InP / Si optical chip according to claim 7, characterized in that: The second SiO2 layer wraps the edge of the top of the first InP waveguide protrusion.

10. An optical module, characterized in that: include: circuit boards; a light source, electrically connected to the circuit board, for emitting light that does not carry a signal; a hybrid InP / Si optical chip, electrically connected to the circuit board, for modulating light that does not carry a signal to generate an optical signal; Wherein, the hybrid InP / Si optical chip is a hybrid InP / Si optical chip prepared by the preparation method according to any one of claims 1 to 5 or a hybrid InP / Si optical chip according to any one of claims 6 to 9.

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