Semiconductor memory device, memory system and method

Abstract

Provided are a semiconductor memory device, a memory system, and a method capable of appropriately storing parameter data in a feature register group provided in an interface chip. The semiconductor memory device includes a terminal group, a first device, and a second device. The first device includes a first register group to which a first address space is mapped, and a memory cell array. The second device is disposed between the terminal group and the first device. The second device includes a second register group including a plurality of pages to which a common second address space exclusive of the first address space is mapped. When the second device receives the instruction sequence of the setting instruction and an address included in the instruction sequence of the setting instruction is a first value, the second device determines a page of a storage destination of the parameter data among the plurality of pages based on the instruction sequence of the setting instruction.

Description

Technical Field

[0001] The present embodiment relates to a semiconductor memory device, a memory system, and a method. Background Art

[0002] A semiconductor memory device includes a semiconductor integrated circuit (IC) called an interface chip, which is placed between multiple memory chips and a group of external terminals connected to an external controller (hereinafter referred to as a memory controller). In this semiconductor memory device, data is transferred between the memory controller and the multiple memory chips via the interface chip. By distributing the load on the transmission lines using the interface chip, the memory system can operate at high speeds even when multiple memory chips are installed.

[0003] Like the memory chip, the interface chip has a feature register set used for function settings. Parameter data for each of the feature register sets in the memory chip and the interface chip is stored using a common, specific command. Summary of the Invention

[0004] Problems to be solved by the invention

[0005] An object of one embodiment is to provide a semiconductor memory device, a memory system, and a method capable of appropriately storing parameter data in a feature register group included in an interface chip.

[0006] According to one embodiment, a semiconductor memory device includes a terminal group, a first device, and a second device. A command sequence including a command setting command for an address is input to the terminal group. The first device includes a first register group mapped with a first address space, and a memory cell array. The first device stores parameter data in the first register group when the address is included in the first address space. The first device does not store parameter data in the first register group when the address is not included in the first address space. The second device is configured between the terminal group and the first device. The second device includes a second register group including a plurality of pages mapped with a common second address space exclusive to the first address space. The second device is configured to determine, based on the command sequence, a page of a storage destination for the parameter data among the plurality of pages when the address is a first value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1This is a schematic diagram showing an example of the configuration of the memory system according to the first embodiment.

[0008] Figure 2 This is a schematic diagram for explaining a more detailed connection relationship between the interface chip and each memory chip in the first embodiment.

[0009] Figure 3 This is a diagram for explaining an example of the configuration of the interface chip and each memory chip according to the first embodiment.

[0010] Figure 4 This is a diagram showing the structure of a command sequence for transmitting a SetFeature command according to the first embodiment.

[0011] Figure 5 This is a diagram for explaining a method of setting parameter data in the first embodiment using the first sequence.

[0012] Figure 6 This is a flowchart showing an example of the operation of the interface chip according to the first embodiment.

[0013] Figure 7 This is a flowchart showing an example of the operation of the memory chip according to the first embodiment.

[0014] Figure 8 This is a diagram showing the structure of the second sequence which is another command sequence for transmitting the SetFeature command in the first embodiment.

[0015] Figure 9 This is a diagram for explaining an example of the configuration of the interface chip and each memory chip according to the second embodiment.

[0016] Figure 10 It is a diagram showing the configuration of the second sequence of the second embodiment.

[0017] Figure 11 This is a diagram for explaining a method of setting parameter data in the second embodiment using the second sequence.

[0018] Figure 12 This is a flowchart showing an example of the operation of the interface chip according to the second embodiment.

[0019] Figure 13 This is a flowchart showing an example of the operation of the memory chip according to the second embodiment.

[0020] Figure 14 It is a diagram showing the configuration of the second sequence of the third embodiment.

[0021] Figure 15 This is a diagram for explaining an example of the configuration of the interface chip and each memory chip according to the third embodiment.

[0022] Figure 16 This is a diagram showing an example of the configuration of a conversion table according to the third embodiment.

[0023] Figure 17 This is a flowchart showing an example of the operation of the interface chip according to the third embodiment.

[0024] Figure 18 This is a flowchart showing an example of the operation of the memory chip according to the third embodiment.

[0025] Figure 19 This is a diagram for explaining an example of the configuration of the interface chip and each memory chip according to the fourth embodiment.

[0026] Figure 20 This is a diagram showing an example of the configuration of a conversion table according to the fourth embodiment.

[0027] Figure 21 This is a diagram for explaining a method of setting parameter data in the fourth embodiment using the first sequence.

[0028] Figure 22 This is a flowchart showing an example of the operation of the interface chip according to the fourth embodiment.

[0029] Figure 23 This is a flowchart showing an example of the operation of the memory chip according to the fourth embodiment.

[0030] Figure 24 This is a diagram for explaining an example of the configuration of the interface chip and each memory chip according to the fifth embodiment.

[0031] Figure 25 This is a diagram showing an example of the configuration of a conversion table according to the fifth embodiment.

[0032] Figure 26 It is a diagram showing the configuration of the first sequence of the fifth embodiment.

[0033] Figure 27 It is a diagram for explaining a method of setting parameter data in the fifth embodiment using the first sequence.

[0034] Figure 28 This is another diagram for explaining the parameter data setting method of the fifth embodiment using the first sequence.

[0035] Figure 29 This is a flowchart showing an example of the operation of the interface chip according to the fifth embodiment.

[0036] Figure 30 This is a flowchart showing an example of the operation of the memory chip according to the fifth embodiment.

[0037] Description of Reference Numerals

[0038] 1. Semiconductor memory device; 101. Host interface; 102. 102-0. 102-1. 201. Memory interface; 103. Controller; 111. 111a. 111b. 111c. 111d. Instruction decoder; 112. 112b. 112c. 112d. 203. 203b. 203c. 203d. Feature register group; 113. 113c. 113d. Memory; 120. 120c. 120d. Conversion table; 202. 202a. 202b. 202c. 202d. Access circuit; 204. Memory cell array; IFC interface chip; CP memory chip; SYS memory system; T terminal group. DETAILED DESCRIPTION

[0039] Hereinafter, a semiconductor memory device, a memory system, and a method according to the embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0040] (First embodiment)

[0041] Figure 1 It is a schematic diagram showing an example of the configuration of the memory system SYS according to the first embodiment.

[0042] The memory system SYS is connectable to a host HS. The communication path connecting the host HS and the memory system SYS, and the standards used for communication via this communication path, are not limited to specific standards. The host HS is, for example, a personal computer, a portable information terminal, or a server. When accessing the memory system SYS, the host HS sends an access command to the memory system SYS. The access command includes a write command or a read command.

[0043] The memory system SYS includes a semiconductor memory device 1 , a memory controller MC, and a RAM (Random Access Memory) 2 .

[0044] The memory controller MC is a control device that controls the semiconductor memory device 1. As part of the control of the semiconductor memory device 1, the memory controller MC executes data transfer between the host HS and the semiconductor memory device 1 in response to an access command from the host HS.

[0045] RAM2 provides the memory controller MC with functions such as a buffer area, a high-speed cache area, and a program loading area. For example, the memory controller MC can cache the data transmitted between the host HS and the semiconductor storage device 1 in RAM2. In addition, the memory controller MC loads the firmware program into RAM2 for use, or caches or high-speed caches various management data into RAM2. In addition, Figure 1 In the example shown, the RAM 2 is arranged outside the memory controller MC. However, the RAM 2 may be built into the memory controller MC.

[0046] The semiconductor storage device 1 includes a terminal group T, an interface chip IFC, and a plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3. The interface chip IFC is arranged between the terminal group T and the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3.

[0047] The plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 are each a nonvolatile memory chip such as a NAND flash memory.

[0048] Semiconductor memory device 1 can be implemented as an MCP (Multi Chip Package) in which memory chips CP0-0 to CP0-3 and memory chips CP1-0 to CP1-3 are stacked. When semiconductor memory device 1 is implemented as an MCP, the interface chip IFC and the peripheries of the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 in semiconductor memory device 1 can also be sealed with a mold resin.

[0049] The semiconductor memory device 1 includes a plurality of channels connecting the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 to the interface chip IFC. The plurality of channels are referred to as memory channels MCH, meaning channels connecting NAND flash memories.

[0050] exist Figure 1 In the example shown in FIG, semiconductor memory device 1 includes memory channels MCH0 and MCH1 as a plurality of memory channels MCH. Four memory chips CP0-0 to CP0-3 are connected to interface chip IFC via memory channel MCH0, and four memory chips CP1-0 to CP1-3 are connected to interface chip IFC via memory channel MCH1.

[0051] Each memory channel MCH is configured based on a predetermined standard. When each memory chip CP0-0 to CP0-3 and CP1-0 to CP1-3 is a NAND flash memory, the predetermined standard is, for example, a trigger DDR standard.

[0052] Furthermore, the number of memory chips CP included in the semiconductor memory device 1 is not limited to 8. Furthermore, the number of memory channels MCH connecting the interface chip IFC and the plurality of memory chips CP is not limited to two.

[0053] Memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 are examples of first devices, respectively, and interface chip IFC is an example of second devices.

[0054] Hereinafter, the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be referred to as memory chips CP, respectively.

[0055] The semiconductor memory device 1 is connected to the memory controller MC via one channel. When viewed from the interface chip IFC, this one channel is referred to as a host channel HCH in the sense of a channel on the host side.

[0056] The host channel HCH is configured based on a predetermined standard. When each memory chip CP is a NAND flash memory, the predetermined standard is, for example, a trigger DDR standard.

[0057] The host channel HCH includes a signal line for transmitting the chip enable signal CEn, a signal line for transmitting the command latch enable signal CLE, a signal line for transmitting the address latch enable signal ALE, a signal line for transmitting the write enable signal WEn, a signal line for transmitting the read enable signal RE / REn, a signal line for transmitting the data select signal DQS / DQSn, a signal line for transmitting the data signal DQ[7:0] having a specified bit width (here, as an example, a width of 8 bits), a signal line for transmitting the ready / busy signal R / Bn_1, and a signal line for transmitting the ready / busy signal R / Bn_2. In addition, the "n" recorded at the end of the symbol representing the signal indicates that the signal operates in negative logic. It is possible to arbitrarily design each signal to operate in negative logic or positive logic.

[0058] The chip enable signal CEn is a signal used to enable the memory chip CP being accessed. The data strobe signals DQS / DQSn are signals that instruct the other device to retrieve the data transmitted by the data signals DQ[7:0]. The data strobe signals DQS / DQSn are differential signals composed of the data strobe signal DQS and the data strobe signal DQSn. The command latch enable signal CLE is a signal that indicates that the data signals DQ[7:0] are commands. The address latch enable signal ALE is a signal that indicates that the data signals DQ[7:0] are addresses. The write enable signal WEn is a signal that instructs the other device to retrieve the command or address transmitted by the data signals DQ[7:0]. The read enable signals RE / REn are signals that instruct the other device to output the data signals DQ[7:0]. The read enable signals RE / REn are differential signals composed of the read enable signal RE and the read enable signal REn. Ready / busy signals R / Bn_1 and R / Bn_2 indicate whether the host channel is in the ready state (waiting for command reception) or in the busy state (unable to execute a command even if received). The configuration of the signal line for transmitting the ready / busy signal R / Bn included in the host channel HCH is not limited to the example described above. For example, the host channel HCH may include a single signal line for transmitting a single ready / busy signal R / Bn, where the ready / busy signal R / Bn is generated by a wired-OR connection, for example, between the ready / busy signal R / Bn applied to the memory channel MCH0 and the ready / busy signal R / Bn applied to the memory channel MCH1.

[0059] Memory channels MCH0 and MCH1 can each transmit and receive the same signal groups as the host channel HCH. Specifically, each memory channel MCH0 and MCH1 includes a signal line for transmitting the chip enable signal CEn, a signal line for transmitting the command latch enable signal CLE, a signal line for transmitting the address latch enable signal ALE, a signal line for transmitting the write enable signal WEn, a signal line for transmitting the read enable signals RE / REn, a signal line for transmitting the data strobe signals DQS / DQSn, a signal line for transmitting the data signal DQ[7:0], and a signal line for transmitting the ready / busy signal R / Bn.

[0060] Figure 2 This is a schematic diagram for explaining a more detailed connection relationship between the interface chip IFC and each memory chip CP according to the first embodiment.

[0061] like Figure 2 As shown, four memory chips CP0-0 to CP0-3 are commonly connected to the memory channel MCH0. Similarly, four memory chips CP1-0 to CP1-3 are commonly connected to the memory channel MCH1.

[0062] Furthermore, the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 do not need to be connected in common to all signal lines constituting the corresponding memory channel MCH. The memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be configured so that several signal lines, excluding the signal lines transmitting the data signals DQ[7:0], among the signal lines constituting the corresponding memory channel MCH, connect the interface chip IFC and the individual memory chips CP on a one-to-one basis.

[0063] The interface chip IFC can independently execute data transfers via memory channel MCH0 and memory channel MCH1. Furthermore, the host channel HCH, which connects the memory controller MC and the interface chip IFC, also controls data transfers via memory channel MCH0 and memory channel MCH1 in parallel, preventing data from being held up within the interface chip IFC. Consequently, the host channel HCH can transmit data at a transmission rate equal to the sum of the transmission rates of memory channel MCH0 and memory channel MCH1. In other words, the host channel HCH can transmit data at twice the transmission rate of the memory channel MCH.

[0064] Each memory chip CP is assigned a unique identification number, namely a LUN (Logical Unit Number) within the semiconductor memory device 1. The memory controller MC stores in advance the relationship between the LUN provided to each memory chip CP and the memory channel MCH to which the memory chip CP is connected. Figure 2 In the example shown, the memory controller MC pre-stores LUN0 for memory chip CP0-0, LUN1 for memory chip CP0-1, LUN2 for memory chip CP0-2, LUN3 for memory chip CP0-3, LUN4 for memory chip CP1-0, LUN5 for memory chip CP1-1, LUN6 for memory chip CP1-2, and LUN7 for memory chip CP1-3.

[0065] Figure 3 This diagram illustrates an example of the configuration of the interface chip IFC and each memory chip CP according to the first embodiment. Memory chips CP0-0 through CP0-3 and CP1-0 through CP1-3 share a common configuration. This diagram shows the configuration of memory chips CP0-0 and CP1-0 as representatives of the memory chips CP0-0 through CP0-3 and CP1-0 through CP1-3, omitting illustration of the configurations of the other memory chips CP.

[0066] The interface chip IFC includes a host interface 101 , two memory interfaces 102 , and a controller 103 .

[0067] The host interface 101 is a PHY circuit that transmits and receives electrical signals to and from the host HA via the host channel HCH.

[0068] Of the two memory interfaces 102, memory interface 102-0 is a PHY circuit that transmits and receives electrical signals to and from the four memory chips CP0-1 to CP0-3 via memory channel MCH0. Memory interface 102-1 is a PHY circuit that transmits and receives electrical signals to and from the four memory chips CP1-0 to CPU1-3 via memory channel MCH1.

[0069] The controller 103 is disposed between the host interface 101 and the two memory interfaces 102 . The controller 103 controls transmission and reception of signals between the host interface 101 and the two memory interfaces 102 .

[0070] The controller 103 includes an instruction decoder 111 and a feature register group 112 .

[0071] The command decoder 111 analyzes signals such as commands received from the host HA via the host channel HCH. Based on the analysis results, the command decoder 111 transmits signals to the memory chip CP. If the command is an instruction to the interface chip IFC to operate, the command decoder 111 operates according to the command.

[0072] The feature register set 112 is a set of registers used for setting functions of the interface chip IFC. The feature register set 112 stores parameter data for one or more functions of the interface chip IFC.

[0073] Each memory chip CP includes a memory interface 201 , an access circuit 202 , a feature register group 203 , and a memory cell array 204 .

[0074] The memory interface 201 is a PHY circuit that transmits and receives electrical signals to and from the interface chip IFC via the memory channel MCH.

[0075] The memory cell array 204 includes a plurality of memory cell transistors. Each memory cell transistor is associated with a row and a column. The memory cell array 204 stores data instructed by a write command from the memory controller MC via the interface chip IFC.

[0076] The feature register group 203 is a register used for setting the functions of the memory chip CP. The feature register group 203 stores parameter data for one or more functions included in the memory chip CP.

[0077] The access circuit 202 includes, for example, a signal processing circuit, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. Based on instructions received from the memory controller MC via the interface chip IFC, the access circuit 202 accesses the memory cell array 204 and stores parameter data in the feature register group 203.

[0078] The characteristic register set 203 is an example of a first register set, and the characteristic register set 112 is an example of a second register set.

[0079] The memory controller MC uses a common setting command to store parameter data for the feature register set 112 included in the interface chip IFC and to store parameter data for the feature register set 203 included in each memory chip CP. This setting command is called a SetFeature command.

[0080] The size of the address space (referred to as the feature register space) that can be specified as the storage destination for parameter data using the SetFeature command is defined by the standard. For example, for semiconductor memory devices using NAND flash memory, the Joint Electron Device Engineering Councils (JEDEC) defines a feature register space consisting of 256 addresses. Each memory vendor can assign the required functions to the feature register space.

[0081] The semiconductor memory device 1 includes feature register groups 112 and 203. Therefore, the feature register groups 112 and 203 need to share a limited feature register space.

[0082] As an example of a technology for sharing a signature register space, a technology compared with the embodiment will be described. This technology will be referred to as a comparative example. According to the comparative example, a portion of the signature register space is mapped to the signature register group of each memory chip, while another portion is mapped to the signature register group of the interface chip. In other words, the signature register space is simply divided into a subspace for each memory chip and a subspace for the interface chip.

[0083] In recent years, demand for faster interface chips has continued to increase. Consequently, interface chips need to have numerous registers capable of configuring various communication-related functions, such as training and equalizer functions. This has led to an increasing amount of parameter data required to configure interface chips (and memory chips).

[0084] In contrast, the comparative example simply divides the feature register space into subspaces for each memory chip and a subspace for the interface chip. Therefore, it is difficult to create a large space in the subspace for the interface chip, and the subspace for the interface chip may be insufficient for the increased amount of parameter data.

[0085] In the first embodiment, the feature register set 112 has multiple pages, and these pages are mapped to a common subspace. Furthermore, the interface chip IFC is configured to interpret the SetFeature instruction sequence as a page-specific instruction when the address included in the instruction sequence is a specific value. This expands the subspace used by the interface chip IFC without reducing the subspace used by each memory chip CP.

[0086] exist Figure 3 In the example shown, the signature register set 203 of each memory chip CP includes 240 storage areas assigned different addresses in the range 00h to EFh. That is, the signature register set 203 maps the signature register space in the range 00h to EFh. Each of the 240 storage areas has a storage capacity of 32 bits.

[0087] The feature register set 112 included in the interface chip IFC includes multiple sets of 16 storage areas, each assigned a different address in the range of F0h to FFh. Each set of 16 storage areas is considered a different page. In other words, a feature register space in the range of F0h to FFh is mapped to each of the multiple pages included in the feature register set 112. Each page is associated with a unique value as an identification number. The value associated with each page is referred to as the page number. Each of the 16 storage areas in each page has a storage capacity of 32 bits.

[0088] The address of the characteristic register group 203 provided to the memory chip CP (in Figure 1 In the example shown, addresses 00h to EFh are recorded as memory feature addresses. The address of the feature register group 112 provided to the interface chip IFC (in Figure 1 In the example shown, addresses F0h to FFh are respectively recorded as interface characteristic addresses. In addition, addresses included in the characteristic register space may be recorded as characteristic addresses.

[0089] The command decoder 111 is configured to interpret the address F0h in the interface feature address as a command for specifying a page (referred to as a page specifying identifier).

[0090] The SetFeature command is transmitted in a command sequence of a specified format. The command sequence for transmitting the SetFeature command includes an address field and a data field, and the page-specifying identifier is transmitted using the address field.

[0091] Figure 4 This is a diagram showing the structure of a command sequence for transmitting a SetFeature command according to the first embodiment.

[0092] The SetFeature command includes a first SetFeature command and a second SetFeature command. The first SetFeature command is used to set parameter data for multiple memory chips CP in common. The second SetFeature command is used to specify one memory chip CP using a LUN and set parameter data for the specified memory chip CP. Figure 4 The structure of the command sequence for transmitting the first SetFeature command is shown in FIG. Hereinafter, the command sequence for transmitting the first SetFeature command is referred to as the first sequence.

[0093] The first sequence is configured to sequentially transmit the first SetFeature command C1, the first address, and the set data. The first SetFeature command C1, the first address, and the set data are transmitted via the signal line group that transmits the data signal DQ[7:0]. The first SetFeature command C1 is transmitted in one command transmission cycle. The first address is transmitted in one address transmission cycle. The set data is transmitted in four data transmission cycles. The command transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as a command using the command latch enable signal CLE. The address transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as an address using the address latch enable signal ALE. The data transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as data.

[0094] The data signal DQ[7:0] is transmitted with a width of 8 bits. Since the first address is transmitted in one address transmission cycle, an address in the range of 00h to FFh, that is, an address in the range of the characteristic register space, can be transmitted as the first address.

[0095] The setting data is transmitted in 4 data transmission cycles. Therefore, in one first sequence, 32 bits (=8 bits×4) of setting data can be transmitted.

[0096] In the first embodiment, the first sequence is configured to be able to transmit, as the first address, any one of an address conforming to the memory characteristic address, an address conforming to the interface characteristic address, and an address conforming to the page designation identifier.

[0097] Furthermore, the first sequence is configured to transmit not only parameter data but also information specifying a page (hereinafter referred to as a page specification) as setting data. When transmitting a page specification as setting data, the memory controller MC can specify any of the multiple pages included in the feature register set 112 by transmitting the page number as the setting data.

[0098] Figure 5 This is a diagram for explaining a method of setting parameter data in the first embodiment using the first sequence.

[0099] exist Figure 5 In the example shown, the memory controller MC sequentially transmits a first sequence SQ1 , a first sequence SQ2 , a first sequence SQ3 , and a first sequence SQ4 to the semiconductor memory device 1 .

[0100] The first sequence SQ1 includes the page-specifying identifier (address F0h) as the first address and the page-specifying value 01h as the setting data specifying page #1. When the interface chip IFC receives the first sequence SQ1, the command decoder 111 recognizes that the first sequence SQ1 is a page-specifying command sequence because it includes the page-specifying identifier. Since the value 01h is included as the setting data in the first sequence SQ1, the command decoder 111 recognizes that the command sequence specifies page #1.

[0101] The first sequence SQ2 includes an address F1h that corresponds to the interface feature address as a first address and parameter data as setting data. When the interface chip IFC receives the first sequence SQ2 following the first sequence SQ1, the command decoder 111 stores the parameter data included in the first sequence SQ2 in the location indicated by address F1h of the designated page, i.e., page #1, within the feature register set 112.

[0102] The first sequence SQ3 includes address F0h, a page-specifying identifier, as the first address, and value 02h, a page-specifying value specifying page #2, as setting data. When the interface chip IFC receives the first sequence SQ3, the command decoder 111 recognizes that the first sequence SQ3 is a page-specifying command sequence because it includes the page-specifying identifier. Since the first sequence SQ3 includes value 02h as setting data, the command decoder 111 recognizes that page #2 is specified.

[0103] The first sequence SQ4 includes an address FFh that corresponds to the interface feature address as a first address and parameter data as setting data. When the interface chip IFC receives the first sequence SQ4 following the first sequence SQ3, the instruction decoder 111 stores the parameter data included in the first sequence SQ4 at the location indicated by address FFh in page #2 of the feature register set 112.

[0104] Thus, the feature register set 112 of the interface chip IFC includes multiple pages, each assigned addresses F0h to FFh, totaling 16 addresses. The first sequence is configured so that the storage destination of parameter data can be switched from one of the multiple pages. Therefore, the address space available for setting parameter data for the interface chip IFC expands according to the number of pages included in the feature register set 112. Consequently, the capacity of the feature register set 112 of the interface chip IFC that can store parameter data can be increased. In other words, the amount of parameter data that can be stored in the feature register set 112 can be increased compared to the comparative example.

[0105] Figure 6 This is a flowchart showing an example of the operation of the interface chip IFC according to the first embodiment.

[0106] When the interface chip IFC receives a first sequence from the memory controller MC via the terminal group T ( S101 ), the controller 103 transmits the received first sequence to the memory chip group CP ( S102 ).

[0107] The command decoder 111 determines whether the first address included in the received first sequence matches the page designation identifier (S103). Figure 3 and Figure 5 In the example shown, address F0h corresponds to the page designation identifier.

[0108] If the first address matches the page designation identifier (S103: Yes), the command decoder 111 determines the designated page based on the setting data included in the first sequence. Then, the command decoder 111 stores the designated page (S104).

[0109] When the first address does not correspond to the page designation identifier ( S103 : No), the instruction decoder 111 determines whether the first address corresponds to the interface characteristic address ( S105 ).

[0110] according to Figure 3 and Figure 5 In the example shown, addresses F0h to FFh correspond to the interface signature address. Furthermore, address F0h is used as a page designator. Therefore, in S105 , if the first address is any of addresses F1h to FFh, the instruction decoder 111 determines that the first address corresponds to the interface signature address.

[0111] If the first address matches the interface feature address ( S105 : Yes), the command decoder 111 stores the parameter data included as setting data in the first sequence at the location indicated by the first address of the designated page in the feature register group 112 ( S106 ).

[0112] When the first address does not match the interface feature address (S105: No), or after S104, or after S106, the interface chip IFC ends the operation.

[0113] The interface chip IFC executes the actions of S102 to S106 every time it receives the first sequence. Figure 5 The action shown.

[0114] Figure 7 This is a flowchart showing an example of the operation of the memory chip CP according to the first embodiment. Note that all memory chips CP included in the semiconductor memory device 1 perform common operations. Here, the operation of one memory chip CP will be described as a representative of all memory chips CP.

[0115] When the memory chip CP receives a first sequence via the interface chip IFC ( S201 ), the access circuit 202 determines whether a first address included in the received first sequence matches a memory characteristic address ( S202 ).

[0116] according to Figure 3 and Figure 5 In the example shown, addresses 00h to EFh correspond to the memory signature address. Therefore, in S202, if the first address is any of addresses 00h to EFh, the access circuit 202 determines that the first address corresponds to the memory signature address.

[0117] When the first address matches the memory signature address ( S202 : YES), the access circuit 202 stores the parameter data included as setting data in the first sequence at the location indicated by the first address in the signature register group 203 ( S203 ).

[0118] When the first address does not match the memory characteristic address (S202: No), or after S203, the memory chip CP ends the operation.

[0119] In addition, the above description has been given of an example of using the first sequence as an instruction sequence for transmitting the SetFeature instruction. Even when the semiconductor memory device 1 receives an instruction sequence for transmitting the second SetFeature instruction (referred to as the second sequence), it can still perform the same operation as when it receives the first sequence (for example, Figure 5 and Figure 6 action shown).

[0120] Figure 8 This is a diagram showing the structure of the second sequence which is another command sequence for transmitting the SetFeature command in the first embodiment.

[0121] The second sequence consists of sequentially transmitting the second SetFeature command C2, the second address, the first address, and the setting data. The second SetFeature command C2 is transmitted in one command transmission cycle. The first address and the second address are each transmitted in one address transmission cycle. The setting data is transmitted in four data transmission cycles.

[0122] The second address is an address that can specify a LUN.

[0123] In the interface chip IFC, the instruction decoder 111 executes the instruction based on the first address and the setting data regardless of the second address. Figure 6 A series of actions shown.

[0124] When the second address matches the LUN assigned to the memory chip CP, the access circuit 202 of each memory chip CP executes Figure 7 A series of actions shown.

[0125] As described above, according to the first embodiment, a command sequence including a SetFeature command at a first address is input to the terminal group T. The memory chip CP includes a feature register group 203 and a memory cell array 204. The feature register group 203 is mapped to a subspace of the feature register space (e.g., a space in the range of 00h to EFh). If the first address is included in the subspace mapped to the feature register group 203, the memory chip CP stores parameter data in the feature register group 203. If the first address is not included in the subspace mapped to the feature register group 203, the memory chip CP does not store parameter data in the feature register group 203. The interface chip IFC includes a feature register group 112. The feature register group 112 includes multiple pages mapped to a common subspace (e.g., a space in the range of F0h to FFh) that is exclusive to the subspace mapped to the feature register group 203. When the first address included in the received command sequence matches the page designation identifier, the interface chip IFC determines the page to which the parameter data is to be stored based on the setting data included in the command sequence.

[0126] Therefore, the subspace available for setting parameter data for the interface chip IFC expands according to the number of pages included in the feature register set 112. This increases the capacity of the feature register set 112 of the interface chip IFC that can store parameter data. Compared to the comparative example, the amount of parameter data that can be stored in the feature register set 112 can be increased. In other words, parameter data can be appropriately stored in the feature register set 112 included in the interface chip IFC.

[0127] Furthermore, according to the first embodiment, when the interface chip IFC receives a command sequence including, as a first address, a value that matches the page-specifying identifier, it specifies one of the multiple pages included in the feature register set 112 based on the setting data included in the command sequence. Then, when the interface chip IFC receives a command sequence including, as a first address, an interface feature address that does not match the page-specifying identifier, it stores the parameter data included as setting data in the command sequence in the specified one of the multiple pages included in the feature register set 112.

[0128] Therefore, compared with the comparative example, the amount of parameter data that can be stored in the feature register group 112 can be increased. In other words, the parameter data can be appropriately stored in the feature register group 112 included in the interface chip IFC.

[0129] (Second embodiment)

[0130] In the second embodiment, matters different from the first embodiment will be described, while matters similar to the first embodiment will be omitted or briefly described.

[0131] Figure 9 This is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the second embodiment.

[0132] In the second embodiment, the controller 103 of the interface chip IFC includes a command decoder 111a in place of the command decoder 111. The command decoder 111a is configured to be able to specify a page based on the second sequence.

[0133] Each memory chip CP includes an access circuit 202 a instead of the access circuit 202 .

[0134] Figure 10 It is a diagram showing the configuration of the second sequence of the second embodiment.

[0135] The second sequence is configured to sequentially transmit the second SetFeature command C2 , the second address, the first address, and the setting data.

[0136] The second sequence is configured so that either an address that conforms to the memory signature address or an address that conforms to the interface signature address can be transmitted as the first address. In other words, the first address includes either a subspace of the signature register space mapped to the signature register set 203 (here, the space in the range of 00h to EFh) or a subspace mapped to the signature register set 112 (for example, the space in the range of F0h to FFh).

[0137] The second sequence is configured to be able to transmit either a LUN or a page specification as the second address. More specifically, if the first address is included in the interface feature address, ie, the subspace mapped to the feature register set 112, the command decoder 111a interprets the second address as a page specification.

[0138] according to Figure 2 and Figure 9 In the example shown, the semiconductor storage device 1 includes eight memory chips CP assigned LUN0 to LUN7. Therefore, the memory controller MC can specify one LUN among the eight memory chips CP by transmitting a value in the range of 00h to 07h as the second address.

[0139] Furthermore, when transmitting a page designation as the second address, the memory controller MC can designate an arbitrary page by transmitting a page number as the second address.

[0140] The second sequence is configured to be able to transmit parameter data as setting data.

[0141] Figure 11 This is a diagram for explaining a method of setting parameter data in the second embodiment using the second sequence.

[0142] exist Figure 11 In the example shown, the memory controller MC sequentially transmits the second sequence SQ11 and the second sequence SQ21 to the semiconductor memory device 1 .

[0143] The second sequence SQ11 includes an address F1h that matches the interface feature address and a value of 01h as the second address. When the interface chip IFC receives the second sequence SQ11, since the first address matches the interface feature address, the instruction decoder 111a recognizes that the second sequence SQ11 is an instruction sequence of the SetFeature instruction targeting the interface chip IFC. For the second sequence targeting the interface chip IFC, the instruction decoder 111a interprets the second address as a page designation. Figure 11 In the example shown, since the second sequence SQ11 includes the value 01h as the second address, the instruction decoder 111a recognizes that page #1 is specified. Therefore, the instruction decoder 111a stores the parameter data included as setting data in the second sequence SQ11 at the location indicated by address F1h of page #1 within the feature register set 112.

[0144] The second sequence SQ21 includes an address FFh that matches the interface feature address and a value 02h as the second address. Since the first address matches the interface feature address, the instruction decoder 111a recognizes that the second sequence SQ21 is an instruction sequence of the SetFeature instruction targeting the interface chip IFC and interprets the second address as a page designation. Figure 11 In the example shown, since the second sequence SQ21 includes the value 02h as the second address, the instruction decoder 111a recognizes that page #2 is specified. Therefore, the instruction decoder 111a stores the parameter data included as setting data in the second sequence SQ21 at the location indicated by address FFh of page #2 within the feature register set 112.

[0145] Figure 12 This is a flowchart showing an example of the operation of the interface chip IFC according to the second embodiment.

[0146] When the interface chip IFC receives the second sequence from the memory controller MC ( S301 ), the controller 103 transmits the received second sequence to the memory chip group CP ( S302 ).

[0147] The command decoder 111 a determines whether the first address included in the received second sequence matches the interface characteristic address ( S303 ).

[0148] In addition, according to Figure 9 and Figure 11 In the example shown, addresses F0h to FFh correspond to the interface characteristic addresses.

[0149] If the first address matches the interface feature address (S303: Yes), the instruction decoder 111a determines the designated page based on the value included as the second address in the second sequence (S304). The instruction decoder 111a then stores the parameter data included as the setting data in the second sequence at the location indicated by the first address of the designated page within the feature register group 112 (S305).

[0150] When the first address does not conform to the interface feature address (S303: No), or after S305, the interface chip IFC ends the operation.

[0151] The interface chip IFC executes the actions of S302 to S305 every time it receives the second sequence. Figure 11 The action shown.

[0152] Figure 13This is a flowchart showing an example of the operation of the memory chip CP according to the second embodiment. As in the first embodiment, all memory chips CP included in the semiconductor storage device 1 perform common operations. Here, the operation of one memory chip CP is described as a representative of all memory chips CP.

[0153] When the memory chip CP receives the second sequence via the interface chip IFC ( S401 ), the access circuit 202 determines whether the second address included in the received second sequence matches the LUN assigned to the memory chip CP ( S402 ).

[0154] When the second address matches the LUN assigned to the memory chip CP having the access circuit 202 (S402: Yes), the access circuit 202 determines whether the second address included in the received second sequence matches the memory characteristic address (S403).

[0155] according to Figure 9 and Figure 11 In the example shown, addresses 00h to EFh correspond to the memory signature address. Therefore, in S403, if the first address is any of addresses 00h to EFh, the access circuit 202 determines that the first address corresponds to the memory signature address.

[0156] When the first address matches the memory signature address ( S403 : Yes), the access circuit 202 stores the parameter data included as setting data in the first sequence at the location indicated by the first address in the signature register group 203 ( S404 ).

[0157] When the second address does not match the LUN assigned to the memory chip CP having its own access circuit 202 (S402: No), or when the first address does not match the memory characteristic address (S403: No), or after S404, the memory chip CP ends the action.

[0158] Thus, according to the second embodiment, the second sequence is configured to transmit a LUN or page number as the second address. When the first address is included in the subspace mapped to the feature register set 112, the interface chip IFC interprets the second address as a page designation, i.e., a page number. The interface chip IFC then stores the parameter data at the location indicated by the first address of one of the multiple pages included in the feature register set 112 that corresponds to the page number.

[0159] Since the page can be specified using the second address of the second sequence, the memory controller MC can instruct both the specification of the page and the storage of the parameter data using one second sequence.

[0160] (Third embodiment)

[0161] In the third embodiment, matters different from the second embodiment will be described, and matters similar to the second embodiment will be omitted or briefly described.

[0162] In the third embodiment, similarly to the second embodiment, the memory controller MC can use the second sequence to store parameter data in the feature register group included in the interface chip IFC. However, the method of specifying a page is different from the second embodiment.

[0163] The second address is transmitted in one address transmission cycle of 8 bits wide, so 256 values ​​can be transmitted as the second address. However, when the number of memory chips CP included in the semiconductor memory device 1 is less than 256, 256 values ​​are not required for specifying the LUN. For example, according to Figure 1 In the example shown, the number of memory chips CP included in the semiconductor storage device 1 is eight, and therefore eight values ​​are sufficient for specifying a LUN.

[0164] In the third embodiment, a plurality of values ​​that are not used for specifying a LUN among the 256 values ​​that can be transmitted as the second address are used for page specification.

[0165] Figure 14 It is a diagram showing the configuration of the second sequence of the third embodiment.

[0166] The second sequence is configured to sequentially transmit the second SetFeature command C2 , the second address, the first address, and the setting data.

[0167] The second sequence is configured to be able to transmit either LUN or page designation as the second address. Of the 256 values ​​that can be transmitted as the second address, at least the number of memory chips CP included in the semiconductor memory device 1 is used to designate the LUN, and the remaining number of values ​​is used to designate the page. Figure 14 In the example shown, values ​​ranging from 00h to 0Fh are used to specify a LUN, and values ​​ranging from 10h to FFh are used to specify a page.

[0168] When the second address is any value in the range of 00h to 0Fh (case 1), the interface chip IFC interprets the first address as conforming to the memory characteristic address. When the second address is any value in the range of 10h to FFh (case 2), the interface chip IFC interprets the first address as conforming to the interface characteristic address.

[0169] Figure 15 This is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the third embodiment.

[0170] In the third embodiment, the controller 103 of the interface chip IFC includes an instruction decoder 111b instead of the instruction decoder 111a. The controller 103 also includes a feature register set 112b instead of the feature register set 112. The controller 103 also includes a memory 113.

[0171] The signature register set 112b includes multiple groups of 256 storage areas, each assigned a different address in the range of 00h to FFh. Each group of 256 storage areas is considered a different page and is assigned a unique page number. Each of the 256 storage areas in each group has a storage capacity of 32 bits.

[0172] Memory 113 is a nonvolatile memory that stores conversion table 120. Memory 113 is, for example, an eFuse or a ROM (Read Only Memory). Conversion table 120 is stored in memory 113 when semiconductor memory device 1 is manufactured. The type of memory 113 and the timing of storing conversion table 120 are not limited thereto.

[0173] Each memory chip CP includes a signature register set 203b instead of the signature register set 203. The signature register set 203b includes 256 storage areas assigned different addresses in the range of 00h to FFh. Each of the 256 storage areas in the signature register set 203 has a storage capacity of 32 bits.

[0174] Each memory chip CP includes an access circuit 202 b instead of the access circuit 202 .

[0175] Figure 16 This is a diagram showing an example of the configuration of the conversion table 120 according to the third embodiment.

[0176] In the conversion table 120, for each page number, the correspondence between a value for specifying a page that can be transferred as a second address and the page number is recorded. Figure 14 In the example shown, the page-specifying value that can be transmitted as the second address is in the range of 10h to FFh. In the third embodiment, a LUN can be transmitted as the second address, so the page number cannot be used directly as the second address. The conversion table 120 associates values ​​that are exclusive to LUN values ​​with the page number, allowing values ​​in a range not used as LUNs to be used as page specifications.

[0177] from Figure 16 As can be seen from the example of the conversion table 120 shown, the value 10h transmitted as the second address corresponds to page number 1, and the value 11h transmitted as the second address corresponds to page number 2.

[0178] The command decoder 111 b can identify the designated page based on the page designation transferred as the second address by referring to the conversion table 120 .

[0179] Figure 17 This is a flowchart showing an example of the operation of the interface chip IFC according to the third embodiment.

[0180] When the interface chip IFC receives the second sequence from the memory controller MC ( S501 ), the controller 103 transmits the received second sequence to the memory chip group CP ( S502 ).

[0181] The command decoder 111 b determines whether the second address included in the received second sequence corresponds to the page designation ( S503 ).

[0182] according to Figure 14 In the example shown, a value in the range of addresses 10h to FFh is used as a page specification. The command decoder 111b determines whether the second address corresponds to a page specification based on whether the second address is a value in the range of addresses 10h to FFh.

[0183] The method for determining whether the second address matches the page designation is not limited to this. For example, the instruction decoder 111b may also determine whether the second address matches the page designation by referring to the conversion table 120. The page designation value is associated with a given page number via the conversion table 120. The instruction decoder 111b may also determine whether the second address matches the page designation based on whether the second address matches the given page number via the conversion table 120.

[0184] If the second address corresponds to a page designation (S503: YES), the instruction decoder 111b determines the designated page (S504) based on the second address and the conversion table 120. The instruction decoder 111b obtains the page number corresponding to the second address from the conversion table 120, thereby determining the designated page.

[0185] The instruction decoder 111 b stores the parameter data included as the setting data in the second sequence at the location indicated by the first address of the designated page in the feature register group 112 ( S505 ).

[0186] When the second address does not conform to the page designation ( S503 : No), or after S505 , the interface chip IFC ends the operation.

[0187] Figure 18 1 is a flowchart showing an example of the operation of the memory chip CP according to the third embodiment. In this figure, the operation of one memory chip CP is also described as a representative of all the memory chips CP.

[0188] When the memory chip CP receives the second sequence via the interface chip IFC ( S601 ), the access circuit 202 b determines whether the second address included in the received second sequence matches the LUN assigned to the memory chip CP ( S602 ).

[0189] When the second address matches the LUN assigned to the memory chip CP (S602: YES), the access circuit 202b stores the parameter data included as setting data in the second sequence at the location indicated by the first address in the feature register group 203b (S603).

[0190] When the second address does not correspond to the LUN assigned to the memory chip CP having its own access circuit 202b (S602: No), or after S603, the memory chip CP ends the operation.

[0191] As described above, according to the third embodiment, the second sequence is configured to transmit, as the second address, values ​​corresponding to each of the multiple pages included in the feature register group 112b that can be used as a LUN value (in the above example, values ​​associated with page numbers in the range from 10h to FFh). When the second address is a value corresponding to any page, the interface chip IFC stores parameter data at the location indicated by the first address of the page corresponding to the second address.

[0192] In the first and second embodiments, the SetFeature instruction sequence is configured to determine whether the target of the SetFeature instruction is the interface chip IFC or each memory chip CP based on whether the first address corresponds to the interface feature address or the memory feature address. Therefore, duplication of the interface feature address and the memory feature address is prohibited.

[0193] In contrast, in the third embodiment, the second sequence is configured to determine whether the target is the interface chip IFC or each memory chip CP based on the second address, thereby allowing the interface feature address and the memory feature address to overlap. Consequently, a common address space (in the example above, the space between 00h and FFh) can be mapped to each page of feature register set 112b and feature register set 203b. This increases the capacity of feature register set 112b of the interface chip IFC that can store parameter data, and allows the full-size feature register space defined by the standard to be mapped to feature register set 203b.

[0194] (Fourth embodiment)

[0195] The memory vendor does not necessarily assign functions of the memory chip CP to all 256 addresses included in the feature register space. The 256 addresses included in the feature register space include addresses to which functions of the memory chip CP are not assigned, that is, addresses not used by the memory chip CP.

[0196] In the fourth embodiment, addresses not used in the memory chip CP among the 256 addresses included in the feature register space are used in the interface chip IFC.

[0197] The fourth embodiment will be described below. In the fourth embodiment, matters different from the first embodiment will be described. Matters similar to the first embodiment will be omitted or briefly described.

[0198] Figure 19 This is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the fourth embodiment.

[0199] The controller 103 of the interface chip IFC includes an instruction decoder 111 c in place of the instruction decoder 111 . Furthermore, the controller 103 includes a feature register set 112 c in place of the feature register set 112 .

[0200] The signature register set 112c includes 32 storage areas assigned different addresses in the range of 00h to 1Fh. Each of the 32 storage areas has a storage capacity of 32 bits. In the fourth embodiment, the 32 addresses in the range of 00h to 1Fh assigned to the signature register set 112c are referred to as interface signature addresses.

[0201] Controller 103 further includes memory 113c. Memory 113c is a nonvolatile memory that stores conversion table 120c. Memory 113c is, for example, an eFuse or ROM (Read Only Memory). Conversion table 120c is stored in memory 113c during the manufacture of semiconductor memory device 1. The type of memory 113c and the timing of storing conversion table 120c are not limited to these.

[0202] Each memory chip CP includes an access circuit 202 c in place of the access circuit 202. Furthermore, each memory chip CP includes a feature register group 203 c in place of the feature register group 203.

[0203] The signature register set 203c includes 256 storage areas, each assigned a different address in the range of 00h to FFh. Each of the 256 storage areas in the signature register set 203c has a 32-bit storage capacity. Furthermore, in the signature register set 203c, 32 addresses in the range of 00h to FFh are not assigned any function. In other words, these 32 addresses in the signature register space are not used by the memory chip CP.

[0204] The 32 addresses in the feature register space not used by the memory chip CP are associated with the 32 storage areas of the feature register set 112c of the interface chip IFC. The conversion table 120c records the association between the 32 addresses not used by the memory chip CP and the 32 storage areas of the feature register set 112c.

[0205] Figure 20 This is a diagram showing an example of the configuration of the conversion table 120 c according to the fourth embodiment.

[0206] The conversion table 120 c records the correspondence between addresses not used in the memory chip CP and the interface characteristic addresses among the 256 addresses that can be transmitted as the first address.

[0207] exist Figure 20 In the example shown, it can be seen from the conversion table 120c that the value 80h transmitted as the first address corresponds to the interface characteristic address 00h, the value A2h transmitted as the first address corresponds to the interface characteristic address 01h, and so on.

[0208] This configuration allows for the following considerations. Specifically, the signature register space (an example of the first access space) includes a space for accessing signature register set 203c (an example of the first space) and a space for accessing signature register set 112c (an example of the second space). The space for accessing signature register set 203c and the space for accessing signature register set 112c are mutually exclusive. The translation table 120c records the correspondence between the address groups included in the space for accessing signature register set 112c and signature register set 112c.

[0209] Figure 21 This is a diagram for explaining a method of setting parameter data in the fourth embodiment using the first sequence.

[0210] exist Figure 21 In the illustrated example, the memory controller MC sequentially transmits the first sequence SQ31 and the first sequence SQ32 to the semiconductor memory device 1 .

[0211] The first sequence SQ31 includes an address 80h which is not used in the memory chip CP as a first address. When the interface chip IFC receives the first sequence SQ31, the command decoder 111c determines whether the first address corresponds to any interface feature address by referring to the conversion table 120c. Figure 20 In the example shown, address 80h is associated with interface signature address 00h. Therefore, the instruction decoder 111c stores the parameter data included in the first sequence SQ31 at the location indicated by interface signature address 00h in the signature register set 112c.

[0212] The first sequence SQ32 includes the address A2h which is not used in the memory chip CP as the first address. When the interface chip IFC receives the first sequence SQ31, the command decoder 111c determines whether the first address corresponds to any interface feature address by referring to the conversion table 120c. Figure 20 In the example shown, address A2h is associated with interface signature address 01h. Therefore, the instruction decoder 111c stores the parameter data included in the first sequence SQ32 at the location indicated by interface signature address 01h in the signature register set 112c.

[0213] Figure 22 This is a flowchart showing an example of the operation of the interface chip IFC according to the fourth embodiment.

[0214] When the interface chip IFC receives a first sequence from the memory controller MC ( S701 ), the controller 103 transmits the received first sequence to the memory chip group CP ( S702 ).

[0215] The command decoder 111 c determines whether the first address included in the received first sequence is associated with the interface characteristic address through the conversion table 120 c ( S703 ).

[0216] If the first address corresponds to the interface feature address (S703: Yes), the instruction decoder 111c converts the first address to the interface feature address (S704). In S704, the instruction decoder 111c determines the interface feature address corresponding to the first address by referring to the conversion table 120c.

[0217] The instruction decoder 111c stores the parameter data included as setting data in the first sequence at the location indicated by the interface feature address obtained through conversion within the feature register group 112c (S705). The instruction decoder 111c stores the parameter data in the storage area indicated by the interface feature address obtained through conversion among the 32 storage areas included in the feature register group 112c.

[0218] When the first address is not associated with the interface feature address (S703: No), or after S705, the interface chip IFC ends the operation.

[0219] Figure 23 4 is a flowchart showing an example of the operation of the memory chip CP according to the fourth embodiment. In this figure, the operation of one memory chip CP is also described as a representative of all the memory chips CP.

[0220] When the memory chip CP receives the first sequence via the interface chip IFC ( S801 ), the access circuit 202 c determines whether the first address included in the received first sequence corresponds to an unused address ( S802 ).

[0221] When the first address does not correspond to an unused address (S802: No), the access circuit 202c stores the parameter data included as setting data in the first sequence at the location indicated by the first address in the feature register group 203c (S803).

[0222] When the first address corresponds to an unused address (S802: Yes), or after S803, the memory chip CP ends the operation.

[0223] In the description of the fourth embodiment, the first sequence is used as an example of a command sequence for transmitting the SetFeature command. Even when the semiconductor memory device 1 receives the second sequence, it can perform the same operation as when it receives the first sequence (for example, Figure 22 action shown).

[0224] As described above, according to the fourth embodiment, the first address included in the instruction sequence of the SetFeature instruction is included in either the space for accessing the feature register set 203c (referred to as the first space) or the space for accessing the feature register set 112c that is exclusive to the first space (referred to as the second space). The correspondence between the address group included in the second space and the feature register set 112c is recorded in the translation table 120c. If the first address is included in the first space, the memory chip CP stores the parameter data included in the instruction sequence in the feature register set 203c. If the first address is not included in the first space, the memory chip CP does not store the parameter data in the feature register set 203c. If the first address is included in the second space, the interface chip IFC stores the parameter data included in the instruction sequence in the feature register set 112c. If the first address is not included in the second space, the interface chip IFC does not store the parameter data in the feature register set 112c.

[0225] Because the interface chip IFC can use addresses in the feature register space that are not used by the memory chip CP, the number of addresses for the interface chip IFC can be maximized without reducing the number of addresses used by the memory chip CP. In other words, parameter data can be appropriately stored in the feature register group 112c included in the interface chip IFC.

[0226] In addition, according to the fourth embodiment, the feature register group 112c includes a plurality of storage areas (in Figure 19 In the example shown, there are 32 storage areas), the second space contains multiple addresses (in Figure 19 In the example shown, there are 32 addresses. The translation table 120c records the correspondence between the multiple addresses contained in the second space and the multiple storage areas contained in the feature register set 112c. When a first address is contained in the second space, the interface chip IFC stores the parameter data contained in the instruction sequence in the multiple storage areas of the feature register set 112c in the storage area corresponding to the first address via the translation table 120c.

[0227] Therefore, addresses in the feature register space that are not used in the memory chip CP can be used in the interface chip IFC.

[0228] (Fifth embodiment)

[0229] In the instruction sequence of the SetFeature instruction, the setting data is transmitted in four data transfer cycles. That is, the instruction sequence of the SetFeature instruction has four 8-bit data transfer fields (data transfer fields B0 to B3 described later), and the memory controller MC can transmit parameter data in units of 8 bits (= 1 byte) for each address. The multiple storage areas with a storage capacity of 32 bits (= 4 bytes) each provided by the feature register group of the memory chip CP can be considered to each have four byte areas, each of which can store 1 byte of parameter data transmitted in one data transfer field. Furthermore, the 256 addresses contained in the feature register space can be considered to each include four segments corresponding to the four byte areas.

[0230] The plurality of storage areas included in the characteristic register group of the memory chip CP may include a storage area including an unused byte area.

[0231] In the fifth embodiment, the space corresponding to the unused byte area in the feature register space can be used in the interface chip IFC. That is, among the 1024 segments (=256 addresses × 4 segments) included in the feature register space, a group of segments not used in the memory chip CP can be used in the interface chip IFC.

[0232] The fifth embodiment will be described below. In the fifth embodiment, the matters that are different from the fourth embodiment will be described. The matters that are the same as the fourth embodiment will be omitted or briefly described.

[0233] Figure 24 This is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the fifth embodiment.

[0234] The controller 103 of the interface chip IFC includes an instruction decoder 111d instead of the instruction decoder 111c. In addition, the controller 103 includes a feature register set 112d instead of the feature register set 112c.

[0235] The signature register set 112d includes 32 storage areas assigned different addresses in the range of 00h to 1Fh. Each of the 32 storage areas has a storage capacity of 32 bits (= 4 bytes). In the fifth embodiment, the 32 addresses in the range of 00h to 1Fh assigned to the signature register set 112d are referred to as interface signature addresses.

[0236] Controller 103 further includes memory 113d. Memory 113d is a nonvolatile memory that stores conversion table 120d. Memory 113d is, for example, an eFuse or ROM. Conversion table 120d is stored in memory 113d during the manufacture of semiconductor memory device 1. The type of memory 113d and the timing of storing conversion table 120d are not limited thereto.

[0237] Each memory chip CP includes an access circuit 202d instead of the access circuit 202c. In addition, each memory chip CP includes a feature register group 203d instead of the feature register group 203c.

[0238] The signature register set 203d includes 256 storage areas each assigned a different address in the range of 00h to FFh. Each of the 256 storage areas included in the signature register set 203d has a storage capacity of 32 bits (= 4 bytes).

[0239] exist Figure 24 In the example shown, 32 of the 256 storage areas included in the signature register set 203d each include one or more unused byte areas. The total capacity of the unused byte areas included in the signature register set 203d is 64 bytes.

[0240] The 32 addresses allocated to the 32 storage areas, including one or more unused byte areas, are associated with the 32 storage areas in the feature register group 112d of the interface chip IFC via the translation table 120d. The location of each unused byte area is also recorded in the translation table 120d.

[0241] Figure 25 This is a diagram showing an example of the configuration of the conversion table 120d according to the fifth embodiment.

[0242] The conversion table 120d records the correspondence between the address assigned to the memory area including the unused byte area among the 256 addresses that can be transmitted as the first address and the interface characteristic address.

[0243] Furthermore, in the conversion table 120d, the position of the unused byte area is recorded for each address allocated to the storage area including the unused byte area among the 256 addresses that can be transmitted as the first address.

[0244] As mentioned above, the instruction sequence of the SetFeature instruction contains four data transmission fields B0 to B3 that transmit 1 byte of parameter data. Figure 25 In the 32-bit memory area, the position of the unused byte area is represented by a flag in data transfer field units. The flag value "1" indicates an unused byte area, and the flag value "0" indicates a used byte area.

[0245] exist Figure 25 In the example shown, address 80h is associated with interface feature address 00h, and the flags for data transfer fields B2 and B3 of data transfer fields B0 to B3 are set to "1." This means that of the four-byte areas in the storage area assigned to address 80h in feature register set 203d, the third and fourth byte areas are unused.

[0246] Furthermore, address A2h is associated with interface feature address 01h, and a flag is set to "1" for data transfer field B1 of data transfer fields B0 to B3. This means that the first byte of the four-byte area in the memory area allocated to address A2h in feature register set 203d is unused.

[0247] Thus, the conversion table 120d records the correspondence between the unused space in the memory chip CP in the feature register space and the feature register group 112d in units of byte regions, in other words, in units of segments, which are address spaces corresponding to byte regions.

[0248] Figure 26 It is a diagram showing the configuration of the first sequence of the fifth embodiment.

[0249] The first sequence is composed of sequentially transmitting the first SetFeature command C1, the first address, and the setting data. The first sequence includes data transmission fields B0 to B3, and the setting data is transmitted in 1-byte units through the data transmission fields B0 to B3.

[0250] Any address that matches the characteristic address and the field setting identifier can be transmitted as the first address. The field setting identifier is a specific address among the 256 characteristic addresses. The command decoder 111d interprets the field setting identifier as a command for setting the destination of the 4-byte parameter data transmitted via the data transfer fields B0 to B3.

[0251] As setting data, in addition to parameter data, field setting values ​​can be transmitted for each data transmission field. The field setting value indicates the destination of the parameter data and whether the parameter data is valid or invalid.

[0252] exist Figure 26 In the example shown, the field setting values ​​can be 00h, 01h, 10h, and 11h.

[0253] The field setting value 00h is invalid data for the memory chip CP. If the field setting value 00h is transmitted in a data transmission field, parameter data subsequently transmitted in the data transmission field is parameter data for the memory chip CP and is invalid data.

[0254] The field setting value 01h is valid data for the memory chip CP. If the field setting value 01h is transmitted in a data transmission field, parameter data subsequently transmitted in the data transmission field is parameter data for the memory chip CP and is valid data.

[0255] The field setting value 10h is invalid data for the interface chip IFC. If the field setting value 10h is transmitted in a data transmission field, the parameter data subsequently transmitted in the data transmission field is parameter data for the interface chip IFC and is invalid data.

[0256] The field setting value 11h is valid data for the interface chip IFC. If the field setting value 11h is transmitted in a data transmission field, the parameter data subsequently transmitted in the data transmission field is parameter data for the interface chip IFC and is valid data.

[0257] Figure 27 and Figure 28 It is a diagram for explaining a method of setting parameter data in the fifth embodiment using the first sequence.

[0258] exist Figure 27In the example shown, the memory controller MC transfers data to the semiconductor memory device 1 in the order of the first sequence SQ41 and the first sequence SQ42.

[0259] The first sequence SQ41 includes a field setting identifier as the first address. In this example, address 55h is used as the field setting identifier. When the interface chip IFC and each memory chip CP receive the first sequence SQ41, since the field setting identifier is included in the first sequence SQ41, they recognize that the field setting values ​​are being transmitted in each of the data transmission fields B0 to B3.

[0260] In the first sequence SQ41, the field setting value 00h is transmitted through the data transmission fields B0 and B1. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transmitted through the data transmission fields B0 and B1 is parameter data destined for the memory chip CP and is invalid data.

[0261] Furthermore, in the first sequence SQ41, the field setting value 11h is transmitted in each of the data transmission fields B2 and B3. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transmitted in the data transmission fields B2 and B3 is parameter data destined for the interface chip IFC and is valid data.

[0262] The first sequence SQ42 includes the signature address 80h as the first address. In the interface chip IFC and each memory chip CP, the following actions are performed based on the field settings contained in the previously transmitted first sequence SQ41. Specifically, the parameter data transmitted in the data transfer fields B0 and B1 contained in the first sequence SQ42 is not stored in the signature register groups 112d and 203d in the interface chip IFC and each memory chip CP. Furthermore, the parameter data transmitted in the data transfer fields B2 and B3 contained in the first sequence SQ42 is stored in the signature register group 112d in the interface chip IFC. Furthermore, the signature address 80h is associated with the interface signature address 00h via the conversion table 120d. Therefore, the parameter data transmitted in the data transfer fields B2 and B3 contained in the first sequence SQ42 is stored in the storage area within the signature register group 112d assigned the interface signature address 00h. In each memory chip CP, the parameter data transferred in the data transfer fields B2 and B3 included in the first sequence SQ42 is not stored in the feature register group 203d.

[0263] exist Figure 28 In the example shown, the memory controller MC transfers data to the semiconductor memory device 1 in the order of the first sequence SQ51 and the first sequence SQ52.

[0264] The first sequence SQ51 includes a field setting identifier as a first address. When the interface chip IFC and each memory chip CP receive the first sequence SQ51, they recognize that field setting values ​​are being transmitted in each of the data transmission fields B0 to B3 because the first sequence SQ51 includes the field setting identifier.

[0265] In each data transmission field B0, B1 of the first sequence SQ51, the transmission field is set to 01h. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transmitted in the data transmission field B0, B1 is parameter data destined for the memory chip CP and is valid data.

[0266] In the data transmission fields B2 and B3 of the first sequence SQ51, the field setting value 10h is transmitted. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transmitted in the data transmission fields B2 and B3 is parameter data destined for the interface chip IFC and is invalid data.

[0267] The first sequence SQ52 includes the signature address 80h as its first address. The interface chip IFC and each memory chip CP perform the following operations based on the field settings contained in the previously transmitted first sequence SQ51. Specifically, the interface chip IFC does not store the parameter data transmitted in the data transfer fields B0 and B1 contained in the first sequence SQ52 in the signature register group 112d. In each memory chip CP, the parameter data transmitted in fields B0 and B1 is stored in the storage area assigned to the signature address 80h within the signature register group 203d. Furthermore, the interface chip IFC and each memory chip CP do not store the parameter data transmitted in the data transfer fields B2 and B3 contained in the first sequence SQ52 in the signature register groups 112d and 203d.

[0268] Figure 29 This is a flowchart showing an example of the operation of the interface chip IFC according to the fifth embodiment.

[0269] When the interface chip IFC receives a first sequence from the memory controller MC ( S901 ), the controller 103 transmits the received first sequence to the memory chip group CP ( S902 ).

[0270] The command decoder 111d determines whether the first address included in the received first sequence matches the field setting identifier (S903). If the first address matches the field setting identifier (S903: Yes), the command decoder 111d stores the field setting values ​​of the data transfer fields B0 to B3 included in the received first sequence (S904).

[0271] When the first address included in the received first sequence does not match the field setting identifier (S903: No), the command decoder 111d determines whether there is a data transfer field having a stored field setting value of "11h" among the data transfer fields B0-B3 (S905).

[0272] If there is a data transfer field with a field setting value of "11h" (S905: Yes), the command decoder 111d converts the first address into an interface signature (S906). The command decoder 111d determines the interface signature address corresponding to the first address by referring to the conversion table 120d.

[0273] The instruction decoder 111d stores the data of the data transfer field having the stored field setting value "11h" at the location indicated by the interface feature address obtained by conversion within the feature register group 112d (S907).

[0274] After S904, or when there is no data transmission field with a field setting value of "11h" (S905: No), or after S907, the interface chip IFC ends the operation.

[0275] Figure 30 1 is a flowchart showing an example of the operation of the memory chip CP according to the fifth embodiment. In this figure, the operation of one memory chip CP is also described as a representative of all the memory chips CP.

[0276] When the memory chip CP receives a first sequence via the interface chip IFC (S1001), the access circuit 202d determines whether the first address included in the received first sequence matches the field setting identifier (S1002). If the first address matches the field setting identifier (S1002: Yes), the access circuit 202d stores the field setting values ​​of the data transmission fields B0 to B3 included in the received first sequence (S1003).

[0277] If the first address included in the received first sequence does not match the field setting identifier (S1002: No), the access circuit 202d determines whether there is a data transfer field having a stored field setting value of "01h" among the data transfer fields B0 to B3 (S1004).

[0278] If a data transfer field having a field setting value of "01h" exists (S1004: Yes), the access circuit 202d stores the data of the data transfer field having the stored field setting value "01h" in the location indicated by the first address in the feature register group 203d (S1005).

[0279] After S1003, or when there is no data transfer field with a field setting value of "01h" (S1004: No), or after S1005, the memory chip CP ends the operation.

[0280] In the above description, the field setting values ​​and parameter data are transmitted using the first sequence. The fifth embodiment can also be implemented using the second sequence instead of or in addition to the first sequence.

[0281] The semiconductor memory device 1 is configured to set whether the data transferred in each data transfer field is destined for the interface chip IFC or each memory chip CP using a field setting value.

[0282] For example, the memory controller MC may use the GetFeature instruction to read parameter data in units of 32-bit storage areas, and then use the SetFeature instruction to transfer the parameter data in a read-modify-write format.

[0283] As described above, according to the fifth embodiment, each feature address includes multiple segments (four segments in the above example), and the interface chip IFC can use unused space in the memory chip CP on a segment basis. In other words, the interface chip IFC uses a group of segments that is exclusive to the group of segments used in the memory chip CP.

[0284] Segments of the feature register space not used by the memory chip CP can be used in the interface chip IFC. This allows for maximum space available for the interface chip IFC without reducing the space available for the memory chip CP in the feature register space. In other words, parameter data can be appropriately stored in the feature register group 112d included in the interface chip IFC.

[0285] Furthermore, the fourth embodiment and the fifth embodiment can be applied together with the first embodiment or the second embodiment.

[0286] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the gist of the invention. These embodiments and their variations are intended to be included within the scope and gist of the invention, and are intended to be included within the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: A terminal group to which a command sequence including an address setting command is input; a first device including a first register group mapped with a first address space and a memory cell array, wherein parameter data is stored in the first register group when the address is included in the first address space, and parameter data is not stored in the first register group when the address is not included in the first address space; and The second device is configured between the terminal group and the first device, and has a second register group, wherein the second register group includes multiple pages mapped to a common second address space that is exclusive to the first address space, and when the address is a first value, the page of the storage destination of the parameter data in the multiple pages is determined based on the instruction sequence.

2. The semiconductor memory device according to claim 1, wherein The instruction sequence of the setting instruction also includes data in addition to the address. The first value is contained in the second address space, the second device, When a first command sequence, which is a command sequence including the setting command for the address of the first value, is received via the terminal group, one of the plurality of pages is determined based on data included in the first command sequence. When an instruction sequence, i.e., a second instruction sequence, of the setting instruction including an address of a second value contained in the second address space different from the first value after the first instruction sequence is received via the terminal group, the data contained in the second instruction sequence is stored as parameter data at a position represented by the second value within the determined 1 page.

3. The semiconductor memory device according to claim 1, wherein The first device is assigned a logical unit number, namely a LUN. The instruction sequence of the setting instruction also contains parameter data in addition to the address. The address includes a first address included in any one of the first address space and the second address space and a second address capable of specifying the LUN. The first value is any one of a group of values ​​associated with different pages of the plurality of pages. When the first address is included in the second address space, the second device interprets the second address as the first value and stores the parameter data at a location indicated by the first address in one of the plurality of pages corresponding to the first value.

4. The semiconductor memory device according to claim 1, wherein The first device is assigned a LUN, The first value is any one of a group of values ​​that is exclusive to the LUN and associated with different pages of the plurality of pages. The instruction sequence of the setting instruction also contains parameter data in addition to the address. The address includes a first address included in any one of the first address space and the second address space and a second address capable of specifying the LUN or the first value. The second device stores the parameter data at a location indicated by the first address of one of the plurality of pages corresponding to the first value when the second address is the first value.

5. A semiconductor memory device comprising: a terminal group to which a command sequence including a setting command for an address included in the first address space is input; A first device having a first register group and a memory cell array; and The second device is arranged between the terminal group and the first device and includes a second register group and a memory storing the first information. The first address space includes: A first space is used for accessing the first register group; and a second space used for access to the second register set and exclusive with the first space, The first information is information recording the correspondence between the second space and the second register group. The first device stores the parameter data in the first register group when the address is included in the first space, and does not store the parameter data in the first register group when the address is not included in the first space. The second device stores the parameter data in the second register set when the address is included in the second space, and does not store the parameter data in the second register set when the address is not included in the second space. The semiconductor memory device according to claim 5 , wherein: The second register group includes multiple storage areas, The second space includes a plurality of first addresses, The first information records the correspondence between the plurality of first addresses and the plurality of storage areas. When the address is any one of the plurality of first addresses, the second device stores parameter data in the storage area associated with the address using the first information in the plurality of storage areas.

7. The semiconductor memory device according to claim 6, wherein The first address space includes a plurality of third spaces corresponding to the plurality of second addresses, and the plurality of third spaces respectively include a plurality of segments. The first space and the second space include mutually exclusive segment groups.

8. The semiconductor memory device according to claim 1 or 5, wherein The setting instruction is a SetFeature instruction.

9. A memory system comprising: The semiconductor memory device according to any one of claims 1 to 7; and The memory controller sends a command sequence of the setting command to the semiconductor memory device.

10. A method for controlling a semiconductor memory device, wherein: The semiconductor memory device comprises: a terminal group to which a command sequence including an address setting command is input; a first device comprising a first register group mapped to a first address space and a memory cell array; and a second device, disposed between the terminal group and the first device, comprising a second register group including a plurality of pages mapped to a second address space that is exclusive to the first address space and is common to the first address space. The method includes the step of determining, when the address included in the command sequence received by the second device is a first value, a page of a storage destination of parameter data among the plurality of pages based on the command sequence.

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