Integrated circuit bit stream generation method and device, electronic equipment and storage medium
Through the automated integrated circuit bitstream generation method, combined with strategy combination and physical constraints, the problem of low automation in integrated circuit optimization design is solved, and the success rate of layout and routing and design efficiency are improved.
Patent Information
- Application Number
- CN202510685270.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-09-19
AI Technical Summary
In the existing technology, the optimization design of integrated circuits has a low degree of automation, which leads to layout and routing failures and relies on manual intervention and professional knowledge.
The integrated circuit is optimized by automatically obtaining a preset strategy combination. When the optimization fails, the log file and netlist file are read, physical constraints are set, and the strategy combination and physical constraints are combined to perform optimization again, thereby realizing automatic integrated circuit bitstream generation.
It improves the success rate and design efficiency of integrated circuit layout and routing, reduces manual intervention, simplifies the process of setting physical constraints, and improves overall design efficiency and reliability.
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Figure CN120671622A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device, and storage medium for generating a bit stream for an integrated circuit. Background Art
[0002] Integrated circuits such as FPGAs (Field-Programmable Gate Arrays) are programmable logic devices that allow users to design and configure hardware circuits based on their needs to suit different application scenarios. The FPGA design process typically includes multiple steps, such as requirements analysis and design definition, HDL writing and simulation, synthesis and implementation, bitstream file generation, hardware verification and debugging. During the synthesis and implementation stages, designers need to employ various optimization strategies (such as timing optimization, area optimization, and power optimization) to ensure that the design meets performance requirements, thereby successfully generating a bitstream file that can be used to configure the FPGA chip. However, a combination of strategies sometimes cannot resolve layout and routing failures. When the strategy combination optimization fails, optimization is often continued by modifying the strategy and combining it with physical constraints.
[0003] In related technologies, policy modifications often require manual intervention, which can lead to low optimization efficiency for designs that require frequent policy changes. Furthermore, physical constraints often need to be implemented by developers early in the development process, relying heavily on their expertise and experience. Summary of the Invention
[0004] The present application provides an integrated circuit bitstream generation method, device, electronic device and storage medium to at least solve the problem of low automation level in the optimization design of integrated circuits in the related art.
[0005] The present application provides a method for generating a bitstream of an integrated circuit, comprising:
[0006] Obtaining a first preset strategy combination;
[0007] Optimizing the integrated circuit based on a first preset strategy combination;
[0008] In the event of optimization failure, read the log file and the integrated circuit netlist file generated in the last step of the optimization process;
[0009] Set physical constraints based on the integrated circuit netlist file and log file, and generate constraint files;
[0010] The integrated circuit is continuously optimized based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream. When the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
[0011] The present invention provides a method for generating an integrated circuit bitstream that can automatically obtain a preset strategy combination to optimize the integrated circuit. In the event of an optimization failure, the method can automatically read the integrated circuit netlist file generated in the last step before the error is reported, as well as the latest log file. Physical constraints can be automatically determined based on the integrated circuit netlist file and log file, and the next optimization is automatically performed based on the preset strategy combination and physical constraints to generate the final integrated circuit bitstream. The integrated circuit bitstream generation method provided by this application can be automatically implemented throughout the entire process without the need for manual intervention, effectively improving work efficiency. Furthermore, the combination of strategy combination and physical constraints effectively improves the success rate of integrated circuit layout and routing.
[0012] In an optional implementation, setting physical constraints based on the integrated circuit netlist file and the log file includes:
[0013] Based on preset scripts, search for problem keywords in log files;
[0014] Based on the problem keywords, determine the problem module, which is the module that causes optimization failure;
[0015] Based on the integrated circuit netlist file, determine the physical location of all submodules in the problem module;
[0016] Set physical constraints based on the physical locations of all submodules in the problem module.
[0017] In this implementation, no physical constraints are required initially. After the first round of optimization fails, the automatically generated log file is read and automatically parsed to identify the module that caused the error, eliminating the need for manual review. Furthermore, a script can automatically analyze the netlist file, determine the physical locations of the submodules of interest, and automatically set physical constraints based on these locations. This entire process is automated, requiring no manual intervention, effectively preventing human error and simplifying the physical constraint setting process, significantly improving design efficiency.
[0018] In an optional embodiment, physical constraints are set based on the physical locations of all submodules in the problem module, including:
[0019] Based on the physical locations of all submodules in the problem module, determine the target area, which is the area where the problem module and all submodules in the problem module are most distributed;
[0020] Constrain the problem module to the target area.
[0021] In this implementation, the module is constrained to one SLR through Pblock constraints, reducing the probability of placement and routing failure due to crossing SLRs. This also compensates for the method of providing strategies only through EDA software. By combining physical constraints with software strategies, the success rate of placement and routing is effectively improved.
[0022] In an optional embodiment, determining the physical locations of all submodules in the problem module based on the integrated circuit netlist file includes:
[0023] Based on the preset command, search the integrated circuit netlist file and obtain the module handle;
[0024] Based on the module handle, identify all submodules in the problem module;
[0025] Based on the location query instruction, the area query instruction and the attribute query instruction, the physical location of each submodule is determined.
[0026] In this embodiment, the physical position of each submodule in the problem module can be automatically and accurately determined, which greatly improves the degree of automation of the design and reduces manual intervention.
[0027] In an optional implementation, constraining the question module to the target area includes:
[0028] Determine the footprint of the problem module;
[0029] Based on the occupied area, the constraint block is determined;
[0030] The problem module is constrained to the target region based on the constraint block.
[0031] In this implementation, the problem that the problem module cannot be completely placed due to the Pblock being too small can be effectively avoided, and the optimization success rate can be effectively improved, thereby improving the optimization efficiency.
[0032] In an optional implementation, optimizing the integrated circuit based on the first preset strategy combination includes:
[0033] Obtaining a preset optimization script; wherein the optimization script is provided with generation instructions, the generation instructions being used to generate a netlist file and a log file at each step of the optimization;
[0034] The first preset strategy optimizes the integrated circuit based on the optimization script.
[0035] In this implementation, the EDA software's placement and routing process is pre-configured in the TCL optimization script, with netlist and log files generated for each step. This facilitates access to the corresponding netlist and log files for physical constraints after the initial placement and routing fails. This fully automated implementation effectively reduces manual intervention and improves design efficiency.
[0036] In an optional implementation, when the integrated circuit optimization based on the first preset strategy combination and the constraint file fails, a second preset strategy combination is obtained, and the first preset strategy combination is replaced with the second preset strategy combination.
[0037] In this embodiment, when the strategy combination optimization fails, the strategy combination can be automatically switched and the physical constraints can be automatically continued to complete the optimization, which effectively saves optimization time and improves the overall design efficiency and reliability.
[0038] The present application also provides an integrated circuit bitstream generating device, comprising:
[0039] An acquisition module, configured to acquire a first preset strategy combination;
[0040] an optimization module, configured to optimize the integrated circuit based on a first preset strategy combination;
[0041] A reading module is used to read the log file and the integrated circuit netlist file generated in the last step of the optimization process when the optimization fails;
[0042] A constraint module is used to set physical constraints based on the integrated circuit netlist file and the log file, and generate a constraint file;
[0043] The optimization module is further configured to continue optimizing the integrated circuit based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream. When the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
[0044] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned integrated circuit bit stream generation methods when executing the computer program.
[0045] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned integrated circuit bit stream generation methods are implemented. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0047] Figure 1 A schematic flow chart of a method for generating a bitstream of an integrated circuit provided in an embodiment of the present application;
[0048] Figure 2 A schematic diagram of the physical constraint process provided in an embodiment of the present application;
[0049] Figure 3 A schematic diagram of a module that failed the first round of placement and routing according to an embodiment of the present application;
[0050] Figure 4 is a schematic diagram of a module after Pblock physical constraints are performed according to an embodiment of the present invention;
[0051] Figure 5 A schematic flow chart of another integrated circuit bitstream generation method provided in an embodiment of the present application;
[0052] Figure 6 FIG. 4 is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0053] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0054] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.
[0055] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0056] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the integrated circuit bitstream generation method depends, the specific application environment architecture or specific hardware architecture is described herein.
[0057] To facilitate understanding, some definitions involved in the embodiments of the present invention are first explained.
[0058] EDA (Electronic design automation): electronic design automation;
[0059] SLR (Super Logic Region): Super logic region;
[0060] SLL (Super Long Line): FPGA super long line;
[0061] Pblock: Physically constrains some logic, that is, it binds some logic to a fixed resource area on the FPGA;
[0062] Implementation: Map the synthesized logic netlist to the specific hardware resources of the FPGA, and complete the process of layout and routing, timing analysis, and bitstream generation.
[0063] Physical constraints: refer to the rules that limit and optimize the physical layout and resource allocation of the design on the FPGA chip.
[0064] The embodiments of the present application are applied to the implementation link of FPGA to complete the layout and routing of FPGA.
[0065] FPGAs operate by mapping code files to the FPGA's inherent gate circuits. The design process typically involves both comprehensive design and implementation. The implementation phase includes key steps such as optimization, layout, and routing. Once routing is successful, the final step is to generate the bitstream file. However, as designs scale and timing requirements increase, the implementation phase often fails due to high code complexity, limited resources, and tight timing. Specific challenges include layout and routing congestion, difficulty in timing convergence, deep logic layers, low resource utilization, and long design iteration times.
[0066] In related technologies, implementation often relies on placement and routing strategies provided by EDA software, such as PerformanceExplore (used to explore different design parameters and layouts to find the optimal configuration for improved performance), PerformanceRetiming (optimizing performance by adjusting circuit timing), and PerformanceBalanceSLRs (used to balance resources across different regions to avoid overloading certain resources). However, these strategies cannot always resolve placement and routing failures, and therefore often require integration with physical constraints. However, both strategy modification and physical constraint setting rely heavily on manual operation, resulting in low automation and inefficiency.
[0067] In view of this, an embodiment of the present application provides a method for generating an integrated circuit bitstream, and the method is described in detail in conjunction with the execution flow of the method for generating an integrated circuit bitstream.
[0068] In this embodiment, a method for generating an integrated circuit bitstream is provided, which can be executed by a server, a terminal, a mobile terminal, or other devices. Figure 1 FIG. 1 is a flow chart of a method for generating a bit stream of an integrated circuit according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:
[0069] Step S101: Obtain a first preset strategy combination. In this embodiment, the first preset strategy combination can be obtained by calling a TCL (Tool Command Language, a programming language) script. One or more strategy combinations to be run can be set in advance in the program.
[0070] Specifically, the first preset strategy combination may be as follows:
[0071] {set opt_design_flags"", set place_design_flags"-directiveAltSpreadLogic_high", set route_design_flags"-directive AlternateCLBRouting"}.
[0072] That is, the first preset strategy combination adopts the optimization design strategy, layout design strategy and routing design strategy, among which the flag of the optimization design strategy is empty and the default value is adopted; the layout design strategy adopts the "directiveAltSpreadLogic_high" instruction, which indicates the use of high-intensity logic distribution optimization; the routing design strategy adopts the "directive AlternateCLBRouting" instruction, which instructs the design tool to use an alternative and optimized method for routing between CLBs (Configurable Logic Blocks).
[0073] Step S102: Optimizing the integrated circuit based on a first preset strategy combination.
[0074] The integrated circuit in this embodiment can be an FPGA chip. Below, using an FPGA chip as an example, the first preset strategy combination is used to optimize the FPGA chip. The optimization in this embodiment encompasses multiple processes, including integrated circuit optimization design, layout design, and routing design, to meet various design requirements, such as timing, resources, and power consumption.
[0075] In addition, the optimization process of the EDA software can be set in the TCL script in advance to automatically optimize the FPGA chip based on the first preset strategy combination.
[0076] Step S103: If the optimization fails, read the log file and the integrated circuit netlist file generated in the last step of the optimization process.
[0077] When optimizing an integrated circuit using a combination of strategies, it may be possible for a bitstream file to fail to be generated due to various reasons, such as timing constraint violations and resource conflicts. In the event of an optimization failure, this embodiment reads the FPGA netlist file generated by the EDA software in the last step before the error is reported, as well as the latest log file.
[0078] If the optimization is successful, the bitstream file is generated directly.
[0079] Step S104 : setting physical constraints based on the integrated circuit netlist file and the log file, and generating a constraint file.
[0080] Specifically, the module that caused the optimization failure can be parsed from the log file and recorded. All submodules of the module can then be determined based on the generated FPGA netlist file. Based on the physical locations of the identified modules and their corresponding submodules, the module is constrained to an SLR. Once the constraints are complete, they are written to the constraint file.
[0081] SSI technology devices consist of multiple SLRs and an interposer, each connected by an SLL. However, the SLL also introduces additional delays. To minimize the impact of SLL delays on the design, physical constraints should be applied to the design to exclude SLR crossings from the critical path. In this case, physically constrained Pblocks should be kept within a single SLR to minimize SLR crossings. This can further improve the timing and routing of SSI technology devices. Pblocks are also a key method for optimizing routing and improving timing.
[0082] Furthermore, physical constraints play a crucial role in FPGA design, significantly impacting a design's performance, power consumption, resource utilization, and timing closure. Physical constraints allocate specific logic resources (such as LUTs, FFs, BRAMs, and DSPs) to specific locations on the FPGA chip, avoiding resource conflicts. Reasonable resource allocation reduces routing congestion and improves routing success rates. Furthermore, physical constraints place critical logic resources in close proximity, reducing signal transmission delays and improving timing performance, ultimately achieving timing optimization. Furthermore, physical constraints can optimize the layout of clock networks, reducing clock skew and delay, thereby achieving clock optimization.
[0083] Step S105 , continuing to optimize the integrated circuit based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream. When the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
[0084] When the constraints are completed, the optimization is restarted based on the first preset strategy combination and the constraint file. If the optimization is completed, an integrated circuit bitstream file will be further generated, and the bitstream file is used to configure the integrated circuit hardware.
[0085] If the optimization still fails, adjust the strategy combination and try again until the set strategy combination is tried completely or a bitstream file is generated.
[0086] In this embodiment, a preset strategy combination can be automatically obtained to optimize the integrated circuit. In the event of an optimization failure, the integrated circuit netlist file and the latest log file generated in the last step before the error are automatically read. Physical constraints can be automatically determined based on the integrated circuit netlist file and log file, and the next optimization can be automatically performed based on the preset strategy combination and physical constraints to generate the final integrated circuit bitstream. The integrated circuit bitstream generation method provided in this application can be fully automated without the need for manual intervention, effectively improving work efficiency. Furthermore, the combination of strategy combination and physical constraints effectively improves the success rate of integrated circuit layout and routing.
[0087] In some optional implementations, the above step S104, i.e., setting physical constraints based on the integrated circuit netlist file and the log file, includes:
[0088] Step S1041: Search for problem keywords in the log file based on a preset script, such as ERROR or failed.
[0089] Step S1042: Based on the problem keywords, the problem module is identified. The problem module is the module that caused the optimization failure. For example, problem keywords such as ERROR or failed can be used to extract the problem module information. In the case of FPGA, a module refers to a functional unit in the FPGA design. The module that caused the optimization failure may be a logic module, a functional module, a constraint module, etc.
[0090] Step S1043 determines the physical locations of all submodules in the problematic module based on the IC netlist file. In an IC, achieving a specific function requires placing logic submodules or other submodules in different functional areas. If optimization fails, the IC netlist file can be queried to obtain the physical locations of each submodule. This physical location can be used to determine the submodule distribution.
[0091] Step S1044: Set physical constraints based on the physical locations of all submodules in the problem module.
[0092] Specifically, it is possible to count the SLRs where the module and its submodules are distributed the most, and then use the Pblock constraint method to constrain the module to this SLR.
[0093] In this embodiment, no physical constraints are required in the initial stages. After the first round of optimization fails, the automatically generated log file is read and automatically parsed to identify the module that caused the error, eliminating the need for manual review. Simultaneously, a script can automatically analyze the netlist file, obtain the physical locations of each submodule of interest, and automatically set physical constraints based on these locations. This entire process is automated, requiring no manual intervention, effectively preventing human error and simplifying the physical constraint setting process, significantly improving design efficiency.
[0094] In addition, in this embodiment, the presence of a cross-SLR phenomenon is determined based on the determined physical locations of each submodule. If so, the module is constrained to a single SLR, and after the constraint is complete, the constraint file is written. If not, the strategy combination is adjusted and tried again until the set strategy combination is completed or a bitstream file is generated.
[0095] In some optional implementations, for modules that must cross SLRs, cross-SLR optimization can be performed through the following steps.
[0096] Determine whether the path across the SLR modules is a critical path;
[0097] When a path across SLR modules is a critical path, a cross-SLR optimization strategy is enabled, where the cross-SLR optimization strategy is used to preferentially allocate preset dedicated routing resources to cross-SLR signals.
[0098] The cross-SLR optimization strategy is added to the preset strategy portfolio for optimizing integrated circuits.
[0099] By pre-allocating dedicated routing resources to critical cross-SLR paths, the connectivity of the paths can be effectively ensured, improving the success rate of placement and routing.
[0100] In some optional implementations, the above step S1044, i.e., setting physical constraints based on the physical locations of all submodules in the problem module, includes:
[0101] Step S10441: Based on the physical locations of all submodules in the problem module, a target area is determined. The target area is the area where the problem module and all submodules in the problem module are most distributed.
[0102] Step S10442: constrain the problem module to the target area.
[0103] Taking FPGAs as an example, the target region in this embodiment, or SLR, is a partitioning method for FPGA chips. FPGA chips are typically divided into multiple SLRs, each of which contains a portion of logic resources. In this embodiment, Pblock constraints are used to specify that the logic units of the problematic module can only be implemented within a single SLR. This effectively optimizes placement and routing, reduces cross-SLR connection delays, ensures that the design meets timing requirements, and improves overall performance.
[0104] In this embodiment, the module is constrained to one SLR through Pblock constraints, reducing the probability of placement and routing failure caused by crossing SLRs, and compensating for the method of providing strategies only through EDA software. By combining physical constraints with software strategies, the success rate of placement and routing is effectively improved.
[0105] Process reference for physical constraints Figure 2 As shown in the figure, after the first round of optimization fails, the log file is read to obtain the problem module; the netlist file is read to obtain the physical location of each sub-module in the problem module; the SLR where most of the problem module is located is determined, that is, the target area; and finally, the module is constrained in the SLR in the Pblock manner.
[0106] Reference Figure 3The figure shows an FPGA with four SLRs. The gray and white parts are the modules that caused the failure of the first round of placement and routing. Most of them are located in SLR0 (at the top), and some are located in SLR1 (at the second top). They are physically constrained to SLR0 through Pblocks and passed through the second round of placement and routing. Figure 4 As shown, the EDA software constrains them all to SLR0 (at the top).
[0107] In some optional implementations, the above step S1043, i.e., determining the physical locations of all submodules in the problem module based on the integrated circuit netlist file, includes:
[0108] Step S10431: Based on the preset command, search the integrated circuit netlist file and obtain the module handle.
[0109] Step S10432: Based on the module handle, determine all submodules in the problem module.
[0110] Step S10433: Determine the physical location of each submodule based on the location query instruction, the area query instruction, and the attribute query instruction.
[0111] In the netlist file, first obtain the module handle through the preset command, namely: set cells[get_cells-hierarchical-filter{NAME=~*$module_name*}], then traverse all sub-modules of the module through foreach, and finally obtain the physical location of each sub-module through get_sites (location query instruction in this embodiment) and get_tiles (area query instruction in this embodiment) and get_property (property query instruction in this embodiment).
[0112] The TCL script for the specific preset command is as follows:
[0113] foreach cell$cells{
[0114] #Get Site and Tile
[0115] set site[get_sites-of$cell]
[0116] set tile[get_tiles-of$site]
[0117] #Get SLR
[0118] set slr[get_property SLR$tile]
[0119] }
[0120] After the traversal is completed, the problem module and its submodules are distributed in the most SLRs, and then the Pblock constraint method is used to constrain the module to this SLR.
[0121] In this embodiment, the physical position of each submodule in the problem module can be determined automatically and accurately, which greatly improves the degree of automation of the design and reduces manual intervention.
[0122] In some optional implementations, step S10442, constraining the problem module to the target area, includes:
[0123] Step a1: determine the occupied area of the problem module.
[0124] Step a2: Determine the constraint block based on the occupied area.
[0125] Step a3: constrain the problem module to the target area based on the constraint block.
[0126] In this embodiment, the occupied area of the problem module can be calculated by obtaining the position and area of each sub-module, and the size of Pblock can be determined based on the occupied area.
[0127] In order to avoid the problem module not being fully placed due to the Pblock being too small, which in turn causes the second round of placement and routing to fail, in this embodiment, the Pblock is constrained to be larger and have more margin.
[0128] The following example illustrates this: the following program constrains the module U_MODULEA_SubModule that causes placement and routing failure to a Pblock named pblock_U_MODULEA. The code is as follows:
[0129] {
[0130] create_pblock pblock_U_MODULEA
[0131] resize_pblock pblock_U_MODULEA-add{
[0132] SLICE_X99Y895:SLICE_X431Y1198
[0133] BUFG_GT_X0Y360:BUFG_GT_X0Y455
[0134] BUFG_GT_SYNC_X0Y225:BUFG_GT_SYNC_X0Y284
[0135] DSP48E2_X1Y358:DSP48E2_X7Y477
[0136] PCIE4CE4_X0Y6:PCIE4CE4_X0Y7
[0137] RAMB18_X2Y358:RAMB18_X8Y477
[0138] RAMB36_X2Y179:RAMB36_X8Y238
[0139] URAM288_X0Y240:URAM288_X0Y315
[0140] }
[0141] add_cells_to_pblock pblock_U_MODULEA[get_cells[list dut_inst / U_MODULEA / U_MODULEA_SubModule]]-clear_locs
[0142] }
[0143] In this embodiment, the problem that the problem module cannot be completely placed due to the Pblock being too small can be effectively avoided, and the optimization success rate can be effectively improved, thereby improving the optimization efficiency.
[0144] In some optional implementations, step S102, i.e., optimizing the integrated circuit based on the first preset strategy combination, includes:
[0145] Step S1021 , obtaining a preset optimization script; wherein the optimization script is provided with generation instructions, and the generation instructions are used to generate a netlist file and a log file in each step of the optimization.
[0146] Step S1022 : Optimizing the integrated circuit based on the optimization script using a first preset strategy.
[0147] In this example, the EDA software's placement and routing process is pre-configured in the TCL optimization script, with netlist and log files generated for each step. This facilitates access to the corresponding netlist and log files for physical constraints after the initial placement and routing fails. This fully automated implementation effectively reduces manual intervention and improves design efficiency.
[0148] In some optional implementations, when the integrated circuit optimization based on the first preset strategy combination and the constraint file fails, a second preset strategy combination is obtained and the first preset strategy combination is replaced with the second preset strategy combination.
[0149] That is, you can set up several strategy combinations to be run in advance in the program, such as: switch$StrategyMode{s1{set opt_design_flags"", set place_design_flags"-directiveAltSpreadLogic_high", set route_design_flags"-directive AlternateCLBRouting"}s2{set opt_design_flags"-directive Explore"set place_design_flags"-directiveExplore"set route_design_flags"-directive Explore"}}.
[0150] Reference Figure 5 As shown in the figure, if the S1 strategy combination fails in both the first and second rounds of optimization, the S2 strategy combination is automatically selected for further optimization. That is, if the first round of optimization based on the S1 strategy combination fails, the log file and netlist information are read, and physical constraints are set. A second round of optimization is then performed based on the physical constraints and the S1 strategy combination. If successful, a bitstream file is automatically generated. If it still fails, the S2 strategy combination is tried again until all the set strategies are exhausted or a bitstream file is generated.
[0151] In addition, as an optional implementation, multiple strategy combinations can be run in parallel to improve design efficiency.
[0152] In this embodiment, when the strategy combination optimization fails, the strategy combination can be automatically switched and the physical constraints can be automatically continued to complete the optimization, which effectively saves the optimization time and improves the overall design efficiency and reliability.
[0153] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.
[0154] The embodiments of the present application further provide an integrated circuit bitstream generating device, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be repeated hereafter. As used below, the term "module" may be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and contemplated.
[0155] This embodiment provides an integrated circuit bitstream generating device, comprising:
[0156] An acquisition module, configured to acquire a first preset strategy combination;
[0157] an optimization module, configured to optimize the integrated circuit based on a first preset strategy combination;
[0158] A reading module is used to read the log file and the integrated circuit netlist file generated in the last step of the optimization process when the optimization fails;
[0159] A constraint module is used to set physical constraints based on the integrated circuit netlist file and the log file, and generate a constraint file;
[0160] The optimization module is further configured to continue optimizing the integrated circuit based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream. When the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
[0161] In an optional embodiment, the constraint module includes:
[0162] A search unit is used to search for problem keywords in log files based on a preset script;
[0163] A problem module determination unit is used to determine the problem module based on the problem keyword, where the problem module is the module that causes the optimization failure;
[0164] The physical location determination unit determines the physical locations of all submodules in the problem module based on the integrated circuit netlist file;
[0165] The setting unit is used to set physical constraints based on the physical positions of all submodules in the problem module.
[0166] In an optional embodiment, the setting unit is further configured to:
[0167] Based on the physical locations of all submodules within the problem module, a target region is determined. The target region is the area with the most problem module and all its submodules. The problem module is then constrained to the target region. This involves determining the footprint of the problem module, determining a constraint based on the footprint, and then constraining the problem module to the target region based on the constraint.
[0168] In an optional implementation, the physical location determination unit is further configured to:
[0169] Based on the preset command, search the integrated circuit netlist file and obtain the module handle;
[0170] Based on the module handle, identify all submodules in the problem module;
[0171] Based on the location query instruction, the area query instruction and the attribute query instruction, the physical location of each submodule is determined.
[0172] In an optional embodiment, the optimization module is further configured to:
[0173] Obtaining a preset optimization script; wherein the optimization script is provided with generation instructions, the generation instructions being used to generate a netlist file and a log file at each step of the optimization;
[0174] The first preset strategy optimizes the integrated circuit based on the optimization script.
[0175] In an optional embodiment, the acquisition module is further configured to:
[0176] In the case that the integrated circuit optimization based on the first preset strategy combination and the constraint file fails, a second preset strategy combination is obtained, and the first preset strategy combination is replaced by the second preset strategy combination.
[0177] For the description of the features in the embodiment corresponding to the integrated circuit bitstream generating device, please refer to the relevant description of the embodiment corresponding to the integrated circuit bitstream generating method, and no further details will be given here.
[0178] The embodiment of the present application also provides an electronic device, such as Figure 6 As shown, it includes a memory 10 and a processor 20, wherein the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned integrated circuit bit stream generation method embodiments.
[0179] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned integrated circuit bitstream generation method embodiments when run.
[0180] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.
[0181] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned integrated circuit bitstream generation method embodiments are implemented.
[0182] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned integrated circuit bitstream generation method embodiments are implemented.
[0183] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0184] The above is a detailed introduction to the integrated circuit bitstream generation method, device, electronic device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
Claims
1. A method for generating a bit stream of an integrated circuit, characterized in that: include: Obtaining a first preset strategy combination; Optimizing the integrated circuit based on the first preset strategy combination; In the event of optimization failure, read the log file and the integrated circuit netlist file generated in the last step of the optimization process; Setting physical constraints based on the integrated circuit netlist file and the log file, and generating a constraint file; The integrated circuit is continuously optimized based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream. When the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
2. The method according to claim 1, characterized in that The setting of physical constraints based on the integrated circuit netlist file and the log file includes: Based on a preset script, search for problem keywords in the log file; Determine a problem module based on the problem keywords, where the problem module is the module that causes optimization failure; Determining the physical locations of all submodules in the problem module based on the integrated circuit netlist file; The physical constraints are set based on the physical positions of all submodules in the problem module.
3. The method according to claim 2, characterized in that The setting of the physical constraints based on the physical positions of all submodules in the problem module includes: Determine a target area based on the physical locations of all submodules in the problem module, where the target area is the area where the problem module and all submodules in the problem module are most widely distributed; The problem module is constrained to be on the target area.
4. The method according to claim 2, characterized in that Determining the physical locations of all submodules in the problem module based on the integrated circuit netlist file includes: Based on a preset command, searching the integrated circuit netlist file to obtain a module handle; Based on the module handle, determining all submodules in the problem module; The physical location of each submodule is determined based on the location query instruction, the area query instruction, and the attribute query instruction.
5. The method according to claim 3, characterized in that The constraining the problem module to the target area includes: Determine the occupied area of the problem module; determining a constraint block based on the occupied area; The problem module is constrained to the target area based on the constraint block.
6. The method according to claim 1, characterized in that The optimizing the integrated circuit based on the first preset strategy combination includes: Obtaining a preset optimization script; wherein the optimization script is provided with a generation instruction, and the generation instruction is used to generate the netlist file and the log file in each step of the optimization; The first preset strategy optimizes the integrated circuit based on the optimization script.
7. The method according to claim 1, characterized in that In the case that the integrated circuit optimization based on the first preset strategy combination and the constraint file fails, a second preset strategy combination is obtained, and the first preset strategy combination is replaced by the second preset strategy combination.
8. An integrated circuit bit stream generating device, characterized in that: include: An acquisition module, configured to acquire a first preset strategy combination; an optimization module, configured to optimize the integrated circuit based on the first preset strategy combination; A reading module is used to read the log file and the integrated circuit netlist file generated in the last step of the optimization process when the optimization fails; A constraint module, configured to set physical constraints based on the integrated circuit netlist file and the log file, and generate a constraint file; The optimization module is further configured to continue optimizing the integrated circuit based on the first preset strategy combination and the constraint file to generate an integrated circuit bitstream, and when the integrated circuit bitstream is generated, it indicates that the integrated circuit optimization is successful.
9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the integrated circuit bitstream generation method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the integrated circuit bitstream generation method according to any one of claims 1 to 7 are implemented.