Multi-turn counting integrated circuit and multi-turn counting encoder based on double-pulse triggering
Through a multi-turn counting integrated circuit based on double-pulse triggering, the problem of poor robustness of the rotation turn counter is solved, and turn counting with strong anti-interference ability, low power consumption and low cost is achieved. It also provides fine interval resolution function and is suitable for stable data acquisition and control in complex application scenarios.
Patent Information
- Application Number
- CN202510745863.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-09-19
AI Technical Summary
Existing rotation count counters have poor robustness, are easily affected by environmental factors, have insufficient counting accuracy and reliability, are complex to design and debug, are costly, and are susceptible to power supply interference.
A multi-turn counting integrated circuit based on dual-pulse triggering is adopted, including a clock selection circuit, a signal handshaking circuit, a cross-clock domain circuit, a filtering circuit, an edge extraction circuit, a status register, an event extraction circuit and a turn number register, to achieve high-precision clock control and filtering. Combined with a low-power design, it has the characteristics of anti-interference and low cost.
Ensure stable signal transmission and counting accuracy in complex electromagnetic environments, reduce energy consumption, improve data collection details, provide rich information support for the system, reduce production and maintenance costs, and improve system reliability and economy.
Smart Images
Figure CN120671710A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of encoders, and in particular to a multi-turn counting integrated circuit based on double-pulse triggering and a multi-turn counting encoder. Background Art
[0002] A revolution counter is a counter specifically designed to track rotational or periodic events. It is widely used in applications such as motor speed monitoring, motion detection, and automation systems. It counts by detecting marks or magnetic features on rotating objects. There are two main types of revolution counters: incremental encoders and absolute encoders. Incremental encoders rely on pulse signals to increase or decrease the count, while absolute encoders provide specific position values, not just the number of revolutions.
[0003] Existing solutions mostly use discrete components, which have poor robustness. First, counting accuracy is limited by the resolution and signal noise of the sensitive components. Second, discrete electronic components are susceptible to environmental factors such as heat, humidity, and vibration, which can reduce counting accuracy. Furthermore, wiring problems or power supply interference can cause counting interruptions or errors, posing risks to applications.
[0004] Furthermore, existing revolution counters are relatively complex to design and debug, especially in high-speed or multi-axis applications. Their high cost and dependence on power supplies can also limit their use in certain applications. Therefore, when selecting and designing a revolution counter, it is crucial to fully consider its performance, limitations, and overall system impact. Summary of the Invention
[0005] The purpose of the present invention is to provide a multi-turn counting integrated circuit and a multi-turn counting encoder based on double pulse triggering, which not only have a reliable turn counting function, but also take into account the fine interval resolution function, thereby realizing a multi-turn counting integrated circuit design with strong anti-interference performance, low power consumption and low cost.
[0006] In order to achieve the above-mentioned object, the present invention provides a multi-turn counting integrated circuit based on double pulse triggering, comprising a clock selection circuit, a position interval register, and a signal handshake circuit, a cross-clock domain circuit, a filtering circuit, an edge extraction circuit, a status register, an event extraction circuit and a turn number register connected in sequence; wherein,
[0007] The clock selection circuit is used to receive an external clock signal and output a reference clock;
[0008] The signal exchange circuit is used to exchange the order of the signals according to the two input pulse signals, thereby binding the direction of increase in the number of turns and the direction of rotation;
[0009] The cross-clock domain circuit is used to complete the synchronization of asynchronous pulse signals;
[0010] The filtering circuit is used to filter the two synchronized pulse signals;
[0011] The edge extraction circuit is used to capture the rising edge and falling edge of the two pulse signals after filtering and convert them into trigger signals;
[0012] The status register is used to perform a status jump according to the trigger signal;
[0013] The event extraction circuit is used to extract key events from the state changes of the state register;
[0014] The rotation number register is used to store the accumulated rotation number information;
[0015] The position interval register has an input end connected to the output end of the status register. The position interval register is used to record current position interval information and cooperate with the circle number register to provide a complete position description.
[0016] Optionally, the filtering circuit adopts a glitch filter with adjustable pulse width threshold.
[0017] Optionally, the multi-turn counting integrated circuit based on double-pulse triggering also includes a turn synchronization pulse generation circuit, the input end of the turn synchronization pulse generation circuit is connected to the output end of the status register, and is used to generate a synchronous output pulse signal to ensure that the rotation turn information and the current position interval information are synchronously updated within a single cycle.
[0018] Optionally, the multi-turn counting integrated circuit based on double-pulse triggering further includes a state initialization pulse, and the state register, the turn number register and the position interval register are respectively initialized by the state initialization pulse.
[0019] Optionally, the external clock signal includes a low-speed clock signal, a high-speed clock signal and a clock selection signal, and the clock selection signal is used to determine whether to select one of the low-speed clock signal and the high-speed clock signal.
[0020] Optionally, the revolution register is configured with a high threshold protection function.
[0021] Optionally, the revolution register is further configured with a low threshold protection function.
[0022] Based on the same inventive concept, the present invention also provides a multi-turn counting encoder with a built-in multi-turn encoder chip, on which the multi-turn counting integrated circuit based on double pulse triggering as described above is integrated.
[0023] Optionally, the multi-turn encoder chip is provided with two input terminals and an output terminal, and the multi-turn counting encoder further comprises two pulse Hall sensors, which are electrically connected to the two input terminals respectively.
[0024] Optionally, the output end adopts an RS485 communication interface.
[0025] The present invention provides a multi-turn counting integrated circuit and a multi-turn counting encoder based on double pulse triggering, which have at least one of the following beneficial effects:
[0026] 1) Advanced design concepts have been adopted to achieve a turn counting integrated circuit with strong anti-interference performance, low power consumption, and low cost. Its core advantage lies in the use of high-precision clock control and filtering circuits, which can effectively resist external interference in complex electromagnetic environments, ensuring stable signal transmission and counting accuracy. At the same time, the use of low-power technology enables the circuit to significantly reduce energy consumption during long-term operation and large-scale systems. This is particularly important for portable devices and embedded systems, not only extending battery life but also reducing heat dissipation requirements, improving the reliability and cost-effectiveness of the entire system.
[0027] 2) It has the ability to distinguish interval information in detail, and can count the upper and lower intervals of each circle separately, providing the system with more detailed and accurate time or position feedback. This design not only improves the detail of data collection, but also provides rich information support for subsequent data processing and control decision-making, allowing the system to more flexibly respond to and handle various emergencies in complex application scenarios.
[0028] 3) By optimizing the circuit structure and adopting mature processes, the production and maintenance costs are effectively reduced, making it highly cost-effective in mass production and commercial applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0030] Figure 1 A schematic diagram of a multi-turn counting integrated circuit based on double pulse triggering provided by one embodiment of the present invention;
[0031] Figure 2 A schematic diagram of state transitions of a status register provided by an embodiment of the present invention;
[0032] Figure 3 A schematic diagram of a multi-turn counting encoder provided in accordance with an embodiment of the present invention.
[0033] in:
[0034] 100-Multi-turn counting integrated circuit; 200-Multi-turn encoder chip; 300-Pulse Hall sensor; 400-RS485 communication interface;
[0035] 101 - clock selection circuit; 102 - signal exchange circuit; 103 - cross-clock domain circuit; 104 - filtering circuit; 105 - edge extraction circuit; 106 - status register; 107 - event extraction circuit; 108 - turn register; 109 - position interval register; 110 - turn synchronization pulse generation circuit. DETAILED DESCRIPTION
[0036] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0037] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features.
[0038] Please refer to Figure 1 This embodiment provides a multi-turn counting integrated circuit 100 based on double pulse triggering, including a clock selection circuit 101, a position interval register 109, and a signal handshake circuit 102, a cross-clock domain circuit 103, a filtering circuit 104, an edge extraction circuit 105, a status register 106, an event extraction circuit 107, and a turn number register 108 connected in sequence; wherein,
[0039] The clock selection circuit 101 is used to receive an external clock signal and output a reference clock;
[0040] The signal exchange circuit 102 is used to exchange the order of the signals according to the two input pulse signals, thereby binding the direction of increase in the number of turns and the direction of rotation;
[0041] The cross-clock domain circuit 103 is used to complete the synchronization of asynchronous pulse signals;
[0042] The filtering circuit 104 is used to filter the two synchronized pulse signals;
[0043] The edge extraction circuit 105 is used to capture the rising edge and falling edge of the two pulse signals after filtering and convert them into trigger signals;
[0044] The state register 106 is used to perform state jump according to the trigger signal;
[0045] The event extraction circuit 107 is used to extract key events from the state changes of the state register 106;
[0046] The rotation number register 108 is used to store the accumulated rotation number information;
[0047] The position interval register 109 has an input end connected to the output end of the status register 106 . The position interval register 109 is used to record the current position interval information and cooperate with the circle number register 108 to provide a complete position description.
[0048] The dual-pulse-triggered multi-turn counting integrated circuit 100 provided in this embodiment employs advanced design concepts, achieving a turn counting function with strong anti-interference capabilities, low power consumption, and low cost. Its core advantage lies in the use of high-precision clock control and filtering circuit 104, which effectively resists external interference in complex electromagnetic environments, ensuring stable signal transmission and counting accuracy. Furthermore, the use of low-power technology enables the circuit to significantly reduce energy consumption during long-term operation and in large-scale systems. This is particularly important for portable devices and embedded systems, extending battery life while reducing heat dissipation requirements and improving overall system reliability and cost-effectiveness.
[0049] In addition to traditional lap counting, the circuit also features detailed interval resolution, counting the upper and lower halves of each lap separately, providing the system with more detailed and accurate time or position feedback. This design not only enhances data acquisition detail but also provides rich information support for subsequent data processing and control decisions, enabling the system to more flexibly respond to and handle various emergencies in complex application scenarios.
[0050] Furthermore, cost control was fully considered during the circuit design process. By optimizing the circuit structure and adopting mature processes, production and maintenance costs are effectively reduced, making it highly cost-effective for mass production and commercial applications. Overall, the multi-turn counting integrated circuit 100 based on dual-pulse triggering provided in this embodiment not only achieves reliable turn counting but also takes into account fine interval resolution. With the multiple advantages of anti-interference, low power consumption, and low cost, it can provide stable and efficient timing control and data acquisition solutions for various digital systems.
[0051] Specifically, in this embodiment, the external clock signals received by the clock selection circuit 101 include a low-speed clock signal, a high-speed clock signal, and a clock selection signal. The high-speed clock signal typically has a higher frequency, and a signal with a frequency greater than 50 MHz is generally considered a high-speed clock signal. The low-speed clock signal has a relatively lower frequency, typically less than 50 MHz. The clock selection signal is used to determine whether to select the low-speed clock signal or the high-speed clock signal.
[0052] The clock selection circuit 101 outputs a reference clock such as a low-frequency clock or a high-frequency clock based on the selected clock source. The low-frequency clock is used in low-speed and power-sensitive scenarios, and the high-frequency clock is used in high-speed and performance scenarios. This reference clock will serve as the working clock reference for other modules in the system (such as the signal exchange circuit 102, the cross-clock domain circuit 103, the filtering circuit 104, the edge extraction circuit 105, the status register 106, the event extraction circuit 107 and the lap register 108, etc.), providing a unified clock signal for the entire system.
[0053] The most important part of the multi-turn counting integrated circuit 100 is the signal processing part. The main input of the signal chain is two pulse signals (i.e. Figure 1 The two pulse signals first enter the signal exchange circuit 102, which is used to exchange the order of signals, thereby binding the direction of increase in the number of turns and the direction of rotation. When a change in the direction of rotation is detected, the signal exchange circuit 102 can exchange key signal channels. By exchanging or not exchanging key signal channels, the system can flexibly determine the positive and negative nature of the rotation direction. Once the direction is determined, the output of the signal exchange circuit 102 affects the subsequent status register 106, thereby controlling the increase and decrease direction of the number of turns register 108, thereby achieving an accurate number of turns counting function.
[0054] In this embodiment, the two pulse signals enter the cross-clock domain circuit 103 after being processed by the signal exchange circuit 102. The cross-clock domain circuit 103 is used to handle the signal transmission problem between different clock domains, solve the cross-clock domain data synchronization problem, and prevent metastable phenomena.
[0055] After the two pulse signals complete the asynchronous pulse synchronization, they enter the filter circuit 104 for filtering. In this embodiment, the filter circuit 104 uses a glitch filter with an adjustable pulse width threshold to filter out short-term interference (i.e., glitches) in the signal, eliminate high-frequency noise, and ensure signal stability and reliability.
[0056] Then, the rising edge and falling edge of the two pulse signals after filtering are captured by the edge extraction circuit 105 and converted into corresponding trigger signals, providing a reliable basis for subsequent state recording, event judgment and counting functions.
[0057] The state register 106 is used to perform state jump according to the trigger signal. The jump of the state register 106 is in accordance with Figure 2 The state transition process shown in the figure uses a bidirectional arrow to indicate that the rotation direction supports both clockwise and counterclockwise directions. Through simple binary encoding and a bidirectional jump mechanism design, flexible direction control and state tracking capabilities are achieved while maintaining the simplicity of the state machine.
[0058] The event extraction circuit 107 then extracts key events from the state changes of the status register 106 and updates two output registers: the revolution register 108 and the position interval register 109. The revolution register 108 is used to store the accumulated revolution information of a device (such as a motor or rotating object), while the position interval register 109 is used to record the current position interval information of the device and cooperates with the revolution register 108 to provide a complete position description.
[0059] Preferably, the multi-turn counting integrated circuit 100 based on double-pulse triggering also includes a turn synchronization pulse generating circuit 110, the input end of the turn synchronization pulse generating circuit 110 is connected to the output end of the status register 106, and is used to generate a synchronous output pulse signal to ensure that the rotation turn information and the current position interval information are synchronously updated within a single cycle.
[0060] Preferably, the multi-turn counting integrated circuit 100 based on double pulse triggering further includes a state initialization pulse, and the state register 106, the turn number register 108 and the position interval register 109 are respectively initialized by the state initialization pulse.
[0061] Preferably, the revolution register 108 is configured with a high threshold protection function. When the count value of the revolution register 108 reaches a preset upper limit, a protection mechanism is triggered to prevent damage to the device due to excessive rotation.
[0062] More preferably, the revolution register 108 is also equipped with a low-threshold protection function. When the count value of the revolution register 108 reaches a preset lower limit, the protection mechanism is triggered to prevent the device from idling or stalling. This dual-threshold protection mechanism ensures that the device operates within a safe range, preventing both overload and underload, thereby improving system reliability and safety.
[0063] Based on the same inventive concept, an embodiment of the present invention further provides a multi-turn counting encoder having a built-in multi-turn encoder chip 200 , on which the multi-turn counting integrated circuit 100 based on double pulse triggering as described above is integrated.
[0064] Please refer to Figure 3 The multi-turn encoder chip 200 has two input terminals and one output terminal. The multi-turn counting encoder also includes two pulse Hall sensors 300, which are electrically connected to the two input terminals, respectively. Providing two Hall sensors as peripheral inputs of the multi-turn encoder chip 200 improves measurement reliability.
[0065] Preferably, the output end adopts RS485 communication interface 400, which has strong anti-interference performance and good protocol compatibility, which not only ensures the reliability of signal transmission, but also takes into account the flexibility of system architecture, and is particularly suitable for the stable operation requirements of multi-turn counting encoders in complex industrial environments.
[0066] In summary, the embodiments of the present invention provide a multi-turn counting integrated circuit and a multi-turn counting encoder based on dual-pulse triggering, which not only realizes reliable multi-turn counting, but also takes into account the fine interval resolution function. It can provide stable and efficient timing control and data acquisition solutions for various digital systems with the multiple advantages of anti-interference, low power consumption and low cost.
[0067] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.
Claims
1. A multi-turn counting integrated circuit based on double pulse triggering, characterized in that: It includes a clock selection circuit, a position interval register, and a signal handshake circuit, a cross-clock domain circuit, a filtering circuit, an edge extraction circuit, a status register, an event extraction circuit and a lap number register connected in sequence; wherein, The clock selection circuit is used to receive an external clock signal and output a reference clock; The signal exchange circuit is used to exchange the order of the signals according to the two input pulse signals, thereby binding the direction of increase in the number of turns and the direction of rotation; The cross-clock domain circuit is used to complete the synchronization of asynchronous pulse signals; The filtering circuit is used to filter the two synchronized pulse signals; The edge extraction circuit is used to capture the rising edge and falling edge of the two pulse signals after filtering and convert them into trigger signals; The status register is used to perform a status jump according to the trigger signal; The event extraction circuit is used to extract key events from the state changes of the state register; The rotation number register is used to store the accumulated rotation number information; The position interval register has an input end connected to the output end of the status register. The position interval register is used to record current position interval information and cooperate with the circle number register to provide a complete position description.
2. The multi-turn counting integrated circuit based on double pulse triggering according to claim 1, characterized in that: The filtering circuit adopts a glitch filter with adjustable pulse width threshold.
3. The multi-turn counting integrated circuit based on double pulse triggering as claimed in claim 1, characterized in that: The multi-turn counting integrated circuit based on dual-pulse triggering also includes a turn synchronization pulse generation circuit, the input end of which is connected to the output end of the status register, for generating a synchronous output pulse signal to ensure that the rotation turn information and the current position interval information are synchronously updated within a single cycle.
4. The multi-turn counting integrated circuit based on double pulse triggering according to claim 1, characterized in that: The multi-turn counting integrated circuit based on double-pulse triggering further includes a state initialization pulse, and the state register, the turn number register, and the position interval register are respectively initialized by the state initialization pulse.
5. The multi-turn counting integrated circuit based on double pulse triggering as claimed in claim 1, characterized in that: The external clock signal includes a low-speed clock signal, a high-speed clock signal, and a clock selection signal. The clock selection signal is used to determine whether to select one of the low-speed clock signal and the high-speed clock signal.
6. The multi-turn counting integrated circuit based on double pulse triggering as claimed in claim 1, characterized in that: The revolution register is configured with a high threshold protection function.
7. The multi-turn counting integrated circuit based on double pulse triggering as claimed in claim 6, characterized in that: The revolution register is also equipped with a low threshold protection function.
8. A multi-turn counting encoder, characterized in that: A multi-turn encoder chip is built in, and a multi-turn counting integrated circuit based on double pulse triggering according to any one of claims 1 to 7 is integrated on the multi-turn encoder chip.
9. The multi-turn counting encoder according to claim 8, wherein: The multi-turn encoder chip is provided with two input terminals and an output terminal. The multi-turn counting encoder further comprises two pulse Hall sensors, which are electrically connected to the two input terminals respectively.
10. The multi-turn counting encoder according to claim 9, wherein: The output terminal adopts RS485 communication interface.