Top layer interconnection structure, forming method thereof and chip
By forming a groove that continuously surrounds the first area in the second area of the top interconnect layer and filling it with a passivation layer, the problem of moisture entering the chip due to deformation of the top interconnect layer in harsh environments is solved, thereby improving product reliability.
Patent Information
- Application Number
- CN202510809497.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-09-19
AI Technical Summary
Under the harsh testing environment of high temperature, high humidity and high voltage, the top interconnect layer deforms, causing water vapor to enter the chip and affect product reliability.
A first groove continuously surrounding the first area is formed in the second area of the top interconnect layer, and the groove is covered and filled with a passivation layer, so that the top interconnect layer and the passivation layer "bite" each other, reducing the gap during deformation and increasing the water vapor intrusion path.
By reducing the gap between the top interconnect layer and the passivation layer, the product's reliability in the dual 85 test is improved and moisture is prevented from entering the chip.
Smart Images
Figure CN120674405A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a top-level interconnection structure, a forming method thereof, and a chip. Background Art
[0002] After the chips are divided and packaged in the wafer fab, they undergo a series of product-level reliability tests. The double 85 test is the most common and important of these tests. For standard products, the double 85 test typically involves testing for a set time in an environment with a temperature of 85 degrees Celsius and a humidity of 85%. For products with more demanding requirements, the humidity is often raised to above 85%, even to 95%, and a higher operating voltage is applied to conduct the test in a harsh test environment.
[0003] The above harsh test environment places higher demands on the reliability of the product in dual 85 testing. Summary of the Invention
[0004] The embodiment of the present application provides a top interconnect structure, comprising an interlayer dielectric layer, a top interconnect layer and a passivation layer;
[0005] The top interconnect layer is embedded in the surface of the interlayer dielectric layer. The surface of the top interconnect layer includes a first area located in the middle and a second area surrounding the first area. A first groove continuously surrounding the first area is provided in the second area. The passivation layer covers the interlayer dielectric layer and the surface of the second area of the top interconnect layer, fills the first groove, and exposes the first area of the top interconnect layer.
[0006] Optionally, the first groove extends continuously in parallel with the edge of the first region to surround the first region.
[0007] Optionally, the second area is provided with at least two first grooves that are spaced apart and extend continuously in parallel to the edge of the first area.
[0008] Optionally, the first groove extends continuously in a zigzag manner to surround the first area.
[0009] Optionally, the first region of the top interconnect layer is a second groove.
[0010] Optionally, a first minimum distance between the first groove and the edge of the second zone away from the first zone is greater than or equal to a first preset value, a second minimum distance between the first groove and the edge of the second zone close to the first zone is greater than or equal to a second preset value, and the first minimum distance and the second minimum distance are both less than or equal to half the width of the second zone.
[0011] Optionally, the depth of the first groove is greater than or equal to 1 / 5 of the thickness of the top interconnection layer, and the depth of the first groove is less than or equal to 1 / 2 of the thickness of the top interconnection layer.
[0012] According to another aspect of the present application, a method for forming a top-layer interconnect structure is provided, comprising:
[0013] Providing a top interconnect layer, wherein the top interconnect layer is embedded in the interlayer dielectric layer, and the surface of the top interconnect layer includes a first area located in the middle and a second area surrounding the first area;
[0014] performing patterning on the top interconnect layer to form a first groove in the second region of the top interconnect layer, wherein the first groove continuously surrounds the first region;
[0015] forming a passivation layer to cover the surfaces of the interlayer dielectric layer and the top interconnect layer, and to fill the first groove;
[0016] The passivation layer is patterned to remove the passivation layer on the first region to expose the first region of the top interconnection layer.
[0017] Optionally, after patterning the passivation layer to expose the first region of the top interconnection layer, the exposed top interconnection layer is further etched to form the first region into a second groove.
[0018] According to another aspect of the present application, a chip is further provided, comprising the top-level interconnection structure described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Those skilled in the art will appreciate that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation to the present invention.
[0020] Figure 1 A flow chart of a method for forming a top-level interconnect structure provided in an embodiment of the present application;
[0021] Figures 2A to 2D A schematic structural diagram corresponding to corresponding steps of the method for forming a top-layer interconnect structure provided in an embodiment of the present application;
[0022] Figure 3A A schematic top view of a first groove provided in an embodiment of the present application;
[0023] Figure 3B A schematic top view of another first groove provided in an embodiment of the present application;
[0024] Figure 3C A schematic top view of another first groove provided in an embodiment of the present application;
[0025] Figure 3D This is a schematic top view of another first groove provided in an embodiment of the present application.
[0026] In the accompanying drawings: 10-substrate; 21-top interconnect layer; 21a-pad; 21b-top interconnect line; AA-first area; BB-second area; 22-interlayer dielectric layer; 23-photoresist layer; 23a-first opening; 24-first groove; 24a-first sub-groove; 24b-second sub-groove; 25-passivation layer; 25a-first passivation layer; 25b-second passivation layer; 251-second opening; 26-second groove. DETAILED DESCRIPTION
[0027] As described in the background technology, after analyzing products that failed in ordinary double 85 tests and harsh double 85 tests, the inventors found that the top interconnect layer (such as the pad) of the product underwent significant deformation under the above-mentioned high temperature, high humidity and high voltage environment, and caused water vapor to enter the interior of the chip along the gaps in the deformation of the top interconnect layer, resulting in reliability problems (such as failure).
[0028] To this end, embodiments of the present application provide a top-layer interconnect structure, a method for forming the same, and a chip. The top-layer interconnect structure includes an interlayer dielectric layer, a top-layer interconnect layer, and a passivation layer. The top-layer interconnect layer is embedded in the surface of the interlayer dielectric layer. The surface of the top-layer interconnect layer includes a first region located in the middle and a second region surrounding the first region. The second region is provided with a first groove that continuously surrounds the first region. The passivation layer covers the interlayer dielectric layer and the surface of the second region of the top-layer interconnect layer, fills the first groove, and exposes the first region of the top-layer interconnect layer. In the present application, a first groove that continuously surrounds the first region is formed in the second region of the top-layer interconnect layer, i.e., the surface area of the top-layer interconnect layer outside of the soldering area. The passivation layer fills the first groove, allowing the top-layer interconnect layer and the passivation layer to "interlock" with each other. This not only reduces the gap between the top-layer interconnect layer and the passivation layer when they deform, but also increases the path for external moisture to enter the chip through the gap between the two, thereby improving the product's performance in the dual 85 test, that is, improving product reliability.
[0029] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0030] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion. Spatially relative terms such as "under," "below," "below," "above," "above," etc. may be used herein for convenience of description to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are intended to also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, then, the elements or features described as "under...", "below," or "below" will be oriented as "on" other elements or features. The device can be oriented differently (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "one," "an," and "said / the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "including" is used to determine the presence of features, steps, operations, elements, and / or parts, but does not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0031] An embodiment of the present application provides a method for forming a top-level interconnection structure.
[0032] Figure 1 A flowchart of a method for forming a top-level interconnect structure provided in an embodiment of the present application.
[0033] like Figure 1 As shown, the method for forming a top-layer interconnect structure provided in an embodiment of the present application includes:
[0034] S01: Providing a top interconnect layer, wherein the top interconnect layer is embedded in an interlayer dielectric layer, and a surface of the top interconnect layer includes a first area in the middle and a second area surrounding the first area;
[0035] S02: performing patterning on the top interconnect layer to form a first groove in the second region of the top interconnect layer, wherein the first groove continuously surrounds the first region;
[0036] S03: forming a passivation layer to cover the surfaces of the interlayer dielectric layer and the top interconnection layer, and filling the first groove;
[0037] S04: performing patterning on the passivation layer to remove the passivation layer on the first region to expose the first region of the top interconnection layer.
[0038] Figures 2A to 2D The structural diagram corresponding to the corresponding steps of the method for forming the top interconnect structure provided in the embodiment of the present application is shown below. Figures 2A to 2D The method for forming the top-layer interconnection structure provided by this embodiment is described in detail.
[0039] First, please refer to Figure 2A , perform step S01, provide a top interconnection layer 21, the top interconnection layer 21 is embedded in the interlayer dielectric layer 22, and the surface of the top interconnection layer 21 includes a first area AA located in the middle and a second area BB surrounding the first area AA.
[0040] In some embodiments of the present application, the top interconnect layer 21 is the topmost interconnect layer in the interconnect structure. The top interconnect layer 21 and the interconnect structure are both located on a substrate 10. The substrate 10 is formed with integrated circuit devices and various doped components such as n-type doped wells, p-type doped wells, sources and drains, other doped components, or combinations thereof, to form various devices or components of the devices. The integrated circuit devices include various IC devices formed on a semiconductor substrate. The IC devices include fin field-effect transistors (FinFETs), diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. The top interconnect layer 21 and the interconnect structure are disposed above the integrated circuit devices and are electrically connected to the integrated circuit devices.
[0041] The substrate 10 may be any suitable substrate material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator.
[0042] The top interconnect layer 21 is embedded in the interlayer dielectric layer 22, with only the top wall of the top interconnect layer 21 exposed on the surface of the interlayer dielectric layer 22. The exposed surface (i.e., the top wall) of the top interconnect layer 21 includes a first region AA located in the center and a second region BB surrounding the first region AA. The shape of the first region AA may correspond to the area to be subsequently used for soldering, such as a rectangle or a circle. The second region BB may be an annular region on the surface of the top interconnect layer 21 excluding the first region AA. In some examples, the steps of forming the top interconnect layer 21 may include, for example, forming a groove and a through hole in the interlayer dielectric layer 22, wherein the through hole is located in the groove and exposes the next top interconnect layer; forming (e.g., by CVD, PVD, or chemical plating) a metal material layer to fill the through hole and the groove and cover the surface of the interlayer dielectric layer 22; removing (by dry etching or chemical mechanical polishing) the metal material layer on the surface of the interlayer dielectric layer 22 and above the groove to expose the surface of the interlayer dielectric layer 22; using the metal material layer in the groove as the top interconnect layer 21, and using the metal material layer in the through hole as the conductive via.
[0043] Next, please refer to Figure 2B , performing step S02, patterning the top interconnection layer 21 to form a first groove 24 in the second area BB of the top interconnection layer 21, and the first groove 24 continuously surrounds the first area AA.
[0044] The top interconnect layer 21 may include top interconnect lines 21b having relatively small critical dimensions and pads 21a having relatively large critical dimensions. In the present application, the patterning described above may be performed only on the portion of the top interconnect layer 21 belonging to the pads 21a (for external interconnection) to form a first recess 24 in the second area BB of the top interconnect layer 21. The patterning step may, for example, include forming a photoresist layer 23 covering the interlayer dielectric layer 22 and the surface of the top interconnect layer 21, performing a photolithography process to form a first opening 23a in the photoresist layer 23 to expose a portion of the top interconnect layer 21 (pads 21a) in the second area BB. As shown in a top view, the first opening 23a is continuous and surrounds the first area AA. Subsequently, an etching process (dry etching or wet etching) is performed to etch the exposed top interconnect layer 21 to form a first recess 24 in the second area BB of the top interconnect layer 21. The first recess 24 continuously surrounds the first area AA, and the depth of the first recess 24 may be determined based on the thickness of the top interconnect layer 21 and actual requirements. In some examples, the depth of the first groove 24 may be 1 / 5 to 1 / 2 of the thickness of the top interconnect layer 21 .
[0045] Next, please refer to Figure 2C , executing step S03 , forming a passivation layer 25 to cover the surfaces of the interlayer dielectric layer 22 and the top interconnection layer 21 , and filling the first groove 24 .
[0046] Before forming the passivation layer 25, the remaining photoresist layer may be removed, and the surfaces of the interlayer dielectric layer 22 and the top interconnect layer 21 may be cleaned. The passivation layer 25 may include a first passivation layer 25a and a second passivation layer 25b formed sequentially. The first passivation layer 25a covers the surfaces of the interlayer dielectric layer 22 and the top interconnect layer 21 and fills the first groove 24. The first passivation layer 25a may be an insulating material with good step coverage to facilitate adhesion to the interlayer dielectric layer 22 and the top interconnect layer 21 and to fill the first groove 24. The thickness (minimum thickness) of the first passivation layer 25a may be greater than the depth of the first groove 24. The second passivation layer 25b covers the first passivation layer 25a and may be an insulating material with good water vapor barrier properties. In some examples of the present application, the first passivation layer 25a may include one or more of silicon oxide, silicon oxynitride, or undoped silicon glass (USG), and the second passivation layer 25b may include silicon nitride. In other examples of the present application, a passivation layer made of an organic material, such as polyimide, may be provided on the second passivation layer 25b. Of course, it is also feasible for the entire passivation layer to be made of an organic passivation material, such as a stacked structure consisting of polyimide and benzocyclobutene.
[0047] Next, please refer to Figure 2D , performing step S04 , patterning the passivation layer 25 , removing the passivation layer 25 on the first area AA to expose the first area AA of the top interconnection layer 21 .
[0048] It can be understood that the patterning is only for the top interconnect layer 21 belonging to the pad 21a, that is, after forming a patterned mask layer (e.g., a patterned photoresist layer) to expose the first area AA, an etching process is performed to remove the passivation layer 25 on the first area AA, and a second opening 251 is formed in the passivation layer 25 to expose the surface of the top interconnect layer 21 in the first area AA. Figure 2D In the example shown, after exposing the surface of the top interconnect layer 21 in the first area AA, the second opening 251 can be used to remove a portion of the thickness of the top interconnect layer 21 in the first area AA, so that the top interconnect layer 21 in the first area AA is formed into a second groove 26, and then the patterned mask layer is removed.
[0049] The embodiment of the present application also provides a top-level interconnection structure.
[0050] Figure 2D A schematic cross-sectional view of the top-level interconnect structure provided in an embodiment of the present application.
[0051] like Figure 2DAs shown, the top interconnect structure provided by the embodiment of the present application includes an interlayer dielectric layer 22, a top interconnect layer 21, and a passivation layer 25. The top interconnect layer 21 is embedded in the surface of the interlayer dielectric layer 22. The surface of the top interconnect layer 21 includes a first area AA located in the middle and a second area BB surrounding the first area AA. A first groove 24 is provided in the second area BB and continuously surrounds the first area AA. The passivation layer 25 covers the interlayer dielectric layer 22 and the surface of the second area BB of the top interconnect layer 21, fills the first groove 24, and exposes the first area AA of the top interconnect layer 21.
[0052] The top interconnect structure is the structure at the top of the interconnect structure. Top interconnect layer 21 is the topmost interconnect layer in the interconnect structure. Top interconnect layer 21 and the interconnect structure are both located on substrate 10. Substrate 10 is formed with integrated circuit devices and components for forming various devices or devices. Top interconnect layer 21 and the interconnect structure are disposed above the integrated circuit devices and are electrically connected to the integrated circuit devices. Substrate 10 can be any suitable substrate 10 material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SiO2), silicon-on-insulator (SiO2), silicon-germanium-on-insulator (SiGe), and germanium-on-insulator (GeO2).
[0053] Please continue to refer to Figure 2D The top interconnect layer 21 may include a top interconnect line 21b with a relatively small critical dimension and a pad 21a with a relatively large critical dimension. Both the top interconnect line 21b and the pad 21a are embedded in the interlayer dielectric layer 22, with only the surfaces (top walls) of the top interconnect line 21b and the pad 21a exposed outside the interlayer dielectric layer 22. The top interconnect layer 21, which is located near the pad 21a, has a first area AA and a second area BB. A first recess 24 is provided in the second area BB of the top interconnect layer 21, which is located near the pad 21a. The shape of the first area AA can correspond to the area subsequently used for soldering, such as a rectangle or a circle. The second area BB can be an annular area on the surface of the top interconnect layer 21, excluding the first area AA. A passivation layer 25 covers the surfaces of the interlayer dielectric layer 22 and the top interconnect layer 21, excluding the first area AA, and fills the first recess 24. Specifically, a second opening 251 is provided in the passivation layer 25, exposing only the top interconnect layer 21 in the first area AA (i.e., the area of the pad 21a used for external connection). The first groove 24 may be located near the middle area of the second area BB, and the range of the middle area is determined according to corresponding design rules. For example, the first groove 24 is at a first minimum distance (e.g., Figure 3A L1 in the figure is greater than or equal to the first preset value, and the first groove 24 is at a second minimum distance (eg, Figure 3AL2 in ( L2 in ) is greater than or equal to the second preset value, and the above-mentioned first minimum distance and the above-mentioned second minimum distance are both less than or equal to half of the width of the second region. In addition, the depth of the first groove 24 is also determined based on the thickness of the top interconnect layer 21 and actual needs. In some examples, the depth of the first groove 24 may be greater than or equal to 1 / 5 of the thickness of the top interconnect layer 21, and the depth of the first groove 24 is less than or equal to 1 / 2 of the thickness of the top interconnect layer 21. In other examples, the above-mentioned first preset value may be 3 microns to 7 microns, the second preset value may be 5 microns to 10 microns, and the width of the groove may be 1 micron to 3 microns.
[0054] Figure 3A This is a schematic top view of a first groove 24 provided in an embodiment of the present application. Figure 3A As shown, the first groove 24 extends continuously in a serpentine manner on the second area BB and surrounds the first area AA. Figure 3B This is a top view of another first groove 24 provided in an embodiment of the present application. Figure 3B As shown, the first groove 24 extends continuously in a meandering manner on the second area BB in an M-shaped manner and surrounds the first area AA. Figure 3C This is a top view of another first groove 24 provided in an embodiment of the present application. Figure 3C As shown, the first groove 24 extends continuously and zigzagly on the second area BB in a manner parallel to the edge (contour) of the first area AA and surrounds the first area AA. For example, if the first area AA is circular, the top view shape of the first groove 24 may be circular; if the first area AA is rectangular, the top view shape of the first groove 24 may be a circular rectangle. Figure 3D Schematic diagram of a top view of another first groove 24 provided in an embodiment of the present application. Figure 3D As shown, the second area BB may include a plurality of nested first grooves surrounding the first area AA, and each first groove may be configured with reference to the aforementioned first groove, for example Figure 3D The first sub-groove 24a and the second sub-groove 24b in the first area BB are arranged such that the first sub-groove 24a extends continuously and zigzags on the second area BB in a manner parallel to the edge (contour) of the first area AA and surrounds the first area AA, and the second sub-groove 24b is spaced from the first sub-groove 24a and is arranged around the first sub-groove 24a.
[0055] Please continue to refer to Figure 2DThe surface of the top interconnect layer 21 exposed by the passivation layer 25 can be lower than the surrounding unexposed surface of the top interconnect layer 21. Specifically, the surface of the top interconnect layer 21 in the first area AA can be lower than the surface of the top interconnect layer 21 in the second area BB. In other words, the first area AA of the top interconnect layer 21 forms a second recess 26, which mates with the second opening 251 in the passivation layer 25. This allows the interface between the top interconnect layer 21 and the passivation layer 25 (the subsequent gap) to be higher than the surface of the subsequent first area AA (the area used for soldering), thereby reducing the risk of moisture intrusion through the gap. Of course, it is also feasible to omit the aforementioned second recess 26 in the first area AA and make the surface of the first area AA flush with the second surface. Alternatively, the surfaces of the first area AA and the second area BB may not be completely flat, for example, gradually increasing in height from the middle of the first area AA toward the edge of the second area BB.
[0056] Please continue to refer to Figure 2D The passivation layer 25 may include a first passivation layer 25a and a second passivation layer 25b formed sequentially. The first passivation layer 25a covers the surface of the interlayer dielectric layer 22 and the top interconnect layer 21 and fills the first groove 24. It may be made of an insulating material with good step coverage to facilitate adhesion to the interlayer dielectric layer 22 and the top interconnect layer 21 and to fill the first groove 24. The thickness (minimum thickness) of the first passivation layer 25a may be greater than the depth of the first groove 24. The second passivation layer 25b covers the first passivation layer 25a and may be an insulating material with good water vapor barrier properties. In some examples of the present application, the first passivation layer 25a may include one or more of silicon oxide, silicon oxynitride, or undoped silicon glass (USG), and the second passivation layer 25b may include silicon nitride. In other examples of the present application, a passivation layer made of an organic material, such as polyimide, may be provided on the second passivation layer 25b. Of course, it is also feasible for the entire passivation layer 25 to be made of an organic passivation material, such as a stacked structure consisting of polyimide and benzocyclobutene.
[0057] In summary, embodiments of the present application provide a top-layer interconnect structure, a method for forming the same, and a chip. The top-layer interconnect structure includes an interlayer dielectric layer, a top-layer interconnect layer, and a passivation layer. The top-layer interconnect layer is embedded in the surface of the interlayer dielectric layer. The surface of the top-layer interconnect layer includes a first region located in the middle and a second region surrounding the first region. The second region is provided with a first groove that continuously surrounds the first region. The passivation layer covers the interlayer dielectric layer and the surface of the second region of the top-layer interconnect layer, fills the first groove, and exposes the first region of the top-layer interconnect layer. In this application, a first groove that continuously surrounds the first region is formed in the second region of the top-layer interconnect layer, i.e., the surface area of the top-layer interconnect layer outside of the soldering area. The passivation layer fills the first groove, allowing the top-layer interconnect layer and the passivation layer to "interlock" with each other. This not only reduces the gap between the top-layer interconnect layer and the passivation layer when they deform, but also increases the path for external moisture to enter the chip through the gap between the two, thereby improving the product's performance in the dual 85 test, that is, improving product reliability.
[0058] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A top-level interconnect structure, characterized in that: including an interlayer dielectric layer, a top interconnect layer, and a passivation layer; The top interconnect layer is embedded in the surface of the interlayer dielectric layer. The surface of the top interconnect layer includes a first area located in the middle and a second area surrounding the first area. A first groove continuously surrounding the first area is provided in the second area. The passivation layer covers the interlayer dielectric layer and the surface of the second area of the top interconnect layer, fills the first groove, and exposes the first area of the top interconnect layer.
2. The top interconnect structure according to claim 1, wherein: The first groove continuously extends in parallel with an edge of the first region to surround the first region.
3. The top interconnect structure according to claim 2, wherein: The second area is provided with at least two first grooves spaced apart and extending continuously in parallel to the edge of the first area.
4. The top interconnect structure according to claim 1, wherein: The first groove continuously extends in a zigzag manner to surround the first region.
5. The top interconnect structure according to claim 1, wherein: The first region of the top interconnect layer is a second recess.
6. The top interconnect structure according to claim 1, wherein: A first minimum distance between the first groove and the second zone away from the edge of the first zone is greater than or equal to a first preset value, a second minimum distance between the first groove and the second zone close to the edge of the first zone is greater than or equal to a second preset value, and the first minimum distance and the second minimum distance are both less than or equal to half the width of the second zone.
7. The top interconnect structure according to claim 1, wherein: The depth of the first groove is greater than or equal to 1 / 5 of the thickness of the top interconnection layer, and the depth of the first groove is less than or equal to 1 / 2 of the thickness of the top interconnection layer.
8. A method for forming a top interconnect structure, characterized in that: include: Providing a top interconnect layer, wherein the top interconnect layer is embedded in the interlayer dielectric layer, and the surface of the top interconnect layer includes a first area located in the middle and a second area surrounding the first area; performing patterning on the top interconnect layer to form a first groove in the second region of the top interconnect layer, wherein the first groove continuously surrounds the first region; forming a passivation layer to cover the surfaces of the interlayer dielectric layer and the top interconnect layer, and to fill the first groove; The passivation layer is patterned to remove the passivation layer on the first region to expose the first region of the top interconnection layer.
9. The method for forming a top-level interconnection structure according to claim 8, wherein: The passivation layer is patterned to expose the first region of the top interconnection layer, and then the exposed top interconnection layer is etched to form the first region into a second groove.
10. A chip, characterized in that: The chip comprises a top-level interconnect structure according to any one of claims 1 to 7.