Method and device for processing Ethernet data stream, computer system and network system

Abstract

The invention discloses a method and device for processing Ethernet data flow, a computer system, a network system and a computer readable storage medium. The method is applied to a receiving end device comprising a first forward error correction (FEC) decoder and a second FEC decoder. The method comprises the following steps: acquiring transmission information of a first data stream; and if the transmission information satisfies a trigger condition, adjusting the error correction capability of the receiving end device. By applying the method, the device, the computer system, the network system and the computer readable storage medium, the data stream can be flexibly and effectively processed.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202310377636.7 and invention name “Method, device, computer system and network system for processing Ethernet data stream”. Technical Field

[0002] The present application relates to a method, device, computer system, network system and computer-readable storage medium for processing Ethernet data streams. Background Art

[0003] In order to combat the effects of bit errors in communication transmission, forward error correction (FEC) is introduced into the communication system to correct the bit errors and thus recover the transmitted data. As the communication link rate increases, the bit error rate (BER) also gradually increases, requiring a stronger FEC to correct the bit errors. In Ethernet communications, the Institute of Electrical and Electronics Engineers (IEEE) 802.3bs 200GE / 400GE selects a single-stage FEC RS (544,514) to correct bit errors at a rate of 100G / lane. For the 200G / lane rate, in order to combat the higher received BER, in some schemes, another level of FEC coding is added to the original Reed-Solomon (RS) code to form a cascade code. The basic system transmission diagram using the cascade code is shown below. Figure 1 , where the first FEC encoder and the second FEC encoder together form a concatenated code. In some scenarios, the concatenated code has poor adaptability. Summary of the Invention

[0004] The present application discloses a method, device, computer system, network system and computer-readable storage medium for processing Ethernet data streams, which can flexibly and effectively process Ethernet data streams.

[0005] According to a first aspect of the present application, a method for processing an Ethernet data stream is provided, applied to a receiving device comprising a first forward error correction (FEC) decoder and a second FEC decoder. The method comprises: obtaining transmission information of the first data stream; and adjusting the error correction capability of the receiving device if the transmission information satisfies a trigger condition. Using this method, even in scenarios where concatenated codes are configured, the error correction capability of the receiving device can still be adjusted based on actual application scenarios.

[0006] In one possible implementation, the transmission information includes one or more of a bit error rate (BER), a number of error bits, a symbol error rate (SER), a number of error symbols, a codeword error rate (CER), a number of error codewords, channel state information, and eye diagram parameters of the first data stream. The method of the present application can be based on the number of errors or error rates of various error units as a measure of a threshold or trigger condition, and can be widely applied in various scenarios.

[0007] In one possible implementation, the receiving end device further includes a first deinterleaver, and the transmission information satisfies a trigger condition, and the error correction capability of the receiving end device is adjusted, including one or more of (1)-(6):

[0008] (1) If the number of bit errors in P codewords at the second FEC decoder is less than J, then disable the first deinterleaver and the second FEC decoder, where P and J are positive integers and P>J>1;

[0009] (2) If the number of bit errors in the P codewords at the second FEC decoder is less than K, the first deinterleaver is disabled and the hard decision decoding HDD of the second FEC decoder is enabled, where K is a positive integer and K>J;

[0010] (3) If the number of bit errors in the P codewords at the second FEC decoder is less than L, then the first deinterleaver is disabled and the soft decision decoding (SDD) of the second FEC decoder is enabled in configuration 2, where L is a positive integer and L>K;

[0011] (4) If the number of bit errors in the P codewords at the second FEC decoder is less than M, then disable the first deinterleaver and enable configuration 1 of the second FEC decoder SDD, where M>L;

[0012] (5) If the number of bit errors in the P codewords at the second FEC decoder is less than N, then enable the FEC decoder to be configured as SDD configuration 1 and enable configuration 2 of the first deinterleaver, where N>M;

[0013] (6) If none of (1) to (5) is satisfied, enable Configuration 1 of the second FEC decoder and enable Configuration 1 of the first deinterleaver.

[0014] In a possible implementation, when the transmission information satisfies a trigger condition, adjusting the error correction capability of the receiving device includes any one of the following:

[0015] (1) enabling configuration 1 of soft decision decoding (SDD) of the second FEC decoder;

[0016] (2) enabling configuration 2 of the SDD of the second FEC decoder;

[0017] (3) enabling hard decision decoding HDD of the second FEC decoder;

[0018] (4) Disable the second FEC decoder.

[0019] The error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 is higher than that of the HDD of the second FEC decoder.

[0020] In a possible implementation, the receiving end device further includes a first deinterleaver, and the transmission information satisfies a trigger condition, and the error correction capability of the receiving end device is adjusted, including any one of the following:

[0021] (1) enabling configuration 1 of the soft decision decoding SDD of the second FEC decoder and enabling configuration 1 of the first deinterleaver;

[0022] (2) enabling configuration 1 of the SDD of the second FEC decoder and enabling configuration 2 of the first deinterleaver;

[0023] (3) enabling SDD configuration 1 of the second FEC decoder and disabling the first deinterleaver;

[0024] (4) enabling Configuration 2 of the SDD of the second FEC decoder and disabling the first deinterleaver;

[0025] (5) enabling the hard decision decoding HDD of the second FEC decoder and disabling the first deinterleaver;

[0026] (6) disabling the second FEC decoder and the first deinterleaver;

[0027] The deinterleaving delay and / or power consumption of configuration 1 of the first deinterleaver is higher than the deinterleaving delay and / or power consumption of configuration 2 of the first deinterleaver; the error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than the error correction capability of configuration 2, and the error correction capability of configuration 2 is stronger than the error correction capability of the HDD of the second FEC decoder.

[0028] In one possible implementation, the receiving end device further includes a data position inverse transformer, a first deinterleaver, and a second deinterleaver. The data position inverse transformer is configured to perform an inverse transformation operation on the positions of received data bits or symbols whose positions have been transformed by the data position transformer. The transmission information satisfies a trigger condition, and the error correction capability of the receiving end device is adjusted, including any one of the following:

[0029] (1) The bit error rate BER of the data stream received by the receiving end device satisfies BER <= a, deactivate the data position inverter, the second FEC decoder, the first deinterleaver, and the second deinterleaver, where a > 0;

[0030] (2) The BER of the data stream received by the receiving end device satisfies a < BER <= b, deactivate the data position inverter, the second deinterleaver, and the first deinterleaver, and activate the hard decision decoding HDD of the second FEC decoder;

[0031] (3) The BER of the data stream received by the receiving end device satisfies b < BER <= c, deactivate the data position inverter, the second deinterleaver, and the first deinterleaver, and activate the soft decision decoding SDD of the second FEC decoder;

[0032] (4) The BER of the data stream received by the receiving end device satisfies c < BER <= d, deactivate the data position inverter and the first deinterleaver and activate the soft decision decoding SDD of the second FEC decoder, the data position inverter, and the second deinterleaver;

[0033] (5) The BER of the data stream received by the receiving end device satisfies d < BER <= e, activate the soft decision decoding SDD of the second FEC decoder, the data position inverter, the second deinterleaver, and the first deinterleaver.

[0034] Based on these schemes, the error correction ability of the receiving end device can be flexibly adjusted based on the strength of the error correction ability and considering power consumption and / or latency, etc.

[0035] In a possible implementation, the transmission information is related to the number of error units at the first FEC decoder and / or the second FEC decoder.

[0036] In a possible implementation, the error unit includes a codeword or a bit or a symbol or a bit group containing any number of bits.

[0037] In a possible implementation, the transmission information includes: information on how to adjust the error correction ability of the receiving end device.

[0038] In a possible implementation, the information on how to adjust the error correction ability of the receiving end device includes: deactivate or weaken the error correction ability of the second FEC decoder.

[0039] In a possible implementation, the receiving end device further includes a deinterleaver, and the information on how to adjust the error correction ability of the receiving end device includes:

[0040] disabling or reducing the error correction capability of the second FEC decoder; and / or

[0041] Disabling or weakening the deinterleaving effect of the deinterleaver.

[0042] In a possible implementation, the receiving end device further includes a deinterleaver and a data position inverse transformer, and the information on how to adjust the error correction capability of the receiving end device includes:

[0043] disabling or reducing the error correction capability of the second FEC decoder; and / or

[0044] disabling or weakening the deinterleaving effect of the deinterleaver; and / or

[0045] The function of the data position inverse converter is disabled.

[0046] In a possible implementation manner, the transmission information comes from a register of the transmitting / receiving end device and / or the transmission information is triggered by a primitive.

[0047] According to a second aspect of the present application, a method for processing an Ethernet data stream is provided. The method is performed by a transmitting device, the transmitting device including a first forward error correction (FEC) encoder and a second FEC encoder. The method includes configuring a data stream processing mode of the transmitting device based on an indication. Using this method, the data stream processing mode of the transmitting device can be flexibly configured.

[0048] In a possible implementation, the instruction includes information on how to adjust the error correction capability of the transmitting end device and the data stream processing method.

[0049] In a possible implementation, configuring the data stream processing mode indication of the transmitting end device includes: disabling or weakening the error correction capability of the second FEC decoder.

[0050] In a possible implementation, the transmitting end device further includes a first interleaver, and configuring the data stream processing mode indication of the transmitting end device includes:

[0051] disabling or weakening the error correction capability of the second FEC decoder;

[0052] and / or

[0053] Disabling or weakening the interleaving effect of the first interleaver.

[0054] In a possible implementation, the transmitting end device further includes a first interleaver and a data position converter, and configuring the data stream processing mode indication of the transmitting end device includes:

[0055] disabling or reducing the error correction capability of the second FEC decoder; and / or

[0056] disabling or reducing the error correction capability of the first interleaver; and / or

[0057] The data relocation converter function is disabled.

[0058] In a possible implementation manner, the instruction comes from a receiving device corresponding to the sending device.

[0059] In a possible implementation manner, the indication is in a register of the transmitting end device and / or the indication is triggered by a primitive.

[0060] According to a third aspect of the present application, an apparatus for processing an Ethernet physical layer data stream includes a processor, wherein the processor is configured to execute the method described in any one of the first aspect and possible implementations of the first aspect.

[0061] According to a fourth aspect of the present application, an apparatus for processing an Ethernet physical layer data stream includes a processor, wherein the processor is configured to execute the method described in any one of the second aspect and possible implementations of the second aspect of the claim.

[0062] In one possible implementation, the device includes an Ethernet interface.

[0063] According to a fifth aspect of the present application, a computer system includes the apparatus.

[0064] According to the sixth aspect of the present application, a network system includes a sending end device and a receiving end device, the sending end device includes the device described in any one of the third aspect and its possible implementation methods, and the receiving end device includes the device in any one of the fourth aspect and its possible implementation methods.

[0065] According to the seventh aspect of the present application, a computer program (product) can enable a processor or computer to execute the corresponding steps and / or processes in the above method embodiments when the computer program is executed by a computer.

[0066] A computer-readable storage medium stores at least one program instruction or code, which is loaded and executed by a computer to enable the computer to implement any of the above methods.

[0067] A chip is provided, comprising a processor for calling and executing instructions stored in a memory, so that a device equipped with the chip executes the methods in the above aspects.

[0068] Another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute code in the memory. When the code is executed, the processor is used to execute the methods in the above aspects.

[0069] A device is provided, comprising a chip according to any one of the above solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 A schematic diagram of the concatenated code channel transmission model of the present application;

[0071] Figures 2A to 2N This is a schematic diagram of the concatenated code channel transmission model of this application;

[0072] Figure 3 A flowchart of a method for processing Ethernet data streams according to an embodiment of the present application is provided;

[0073] Figure 4 A schematic diagram of the structure of an apparatus for processing Ethernet data streams according to an embodiment of the present application;

[0074] Figure 5 This is a schematic structural diagram of another device for processing Ethernet data streams according to an embodiment of the present application;

[0075] Figure 6 A schematic diagram of the structure of a computer system according to an embodiment of the present application;

[0076] Figure 7 This is a schematic diagram of the structure of the network system according to an embodiment of the present application. DETAILED DESCRIPTION

[0077] Bit errors (BE) are inevitable in communication transmissions due to environmental interference, system errors, and other factors. A bit error refers to a discrepancy between the data received by the receiving end and the data sent by the transmitting end. Bit errors in the transmission of critical control signals on a device can cause system crashes and data loss. Furthermore, bit errors significantly impact communication latency and the consumer experience with video, gaming, and calls. Therefore, the bit error rate (BER), the number of bit errors at the receiving end, is a key metric for measuring communication system performance.

[0078] The smaller the BER at the receiving end, the higher the transmission reliability. To ensure high system reliability, the communication system will set requirements for the receiving BER. For example, the IEEE 802.3bs 400GE standard requires that the BER when data enters the media access control (MAC) layer at the receiving end be lower than 1×10^(-13), that is, 1×10-13 , and the BER when the link transmission is just completed and enters the receiving end is about 2.4ⅹ10^(-4), that is, 2.4ⅹ10 -4 Therefore, to eliminate most bit errors, FEC is used to correct them and restore the transmitted data. After FEC correction, the BER of the data entering the MAC layer at the receiving end is significantly reduced.

[0079] However, the channel status may cause the bit error rate (i.e., receive BER) of the signal reaching the receiving end to be high due to environmental changes or human factors. Even after FEC correction, the receive BER may not meet specific communication requirements for a period of time.

[0080] like Figure 1 In a concatenated code channel transmission scenario, the transmitting device includes a first FEC encoder and a second FEC encoder, and the receiving device includes a first FEC decoder and a second FEC decoder. The data stream of the transmitting device is encoded by the first FEC encoder and the second FEC encoder, and then transmitted to the receiving device via the PMA / PMD. The receiving device decodes the received data stream using the second FEC decoder and then the second FEC decoder, obtaining the data stream initially sent by the transmitting device. The first FEC encoder is the outer code of the concatenated code and can be a Reed-Solomon (RS) encoder, such as the RS(544,514) code. Correspondingly, the first FEC decoder can be an RS decoder, such as the RS(544,514) code, which performs error correction on the 10-bit symbol of the RS(544,514) code. The second FEC encoder is the inner code of the concatenated code, and may be an FEC code based on bit error correction, and may be different from the RS (544, 514) code. For example, the second FEC encoder may be a Bose-Chaudhuri-Hocquenghem (BCH) code encoder, an extended BCH code encoder, a Hamming code encoder, or an extended Hamming code encoder; accordingly, the second FEC decoder may be an FEC decoder based on bit error correction and having the same code type as the second FEC encoder.

[0081] In some embodiments, the first FEC encoder may be any one of a BCH code encoder, a Fire code encoder, a turbo code encoder, a turbo product code (TPC) encoder, a staircase code encoder, and a low-density parity check (LDPC) code encoder. The second FEC encoder may be any one of a Fire code encoder, a turbo code encoder, a TPC encoder, a staircase code encoder, and an LDPC code encoder.

[0082] like Figure 2A and Figure 2B ,exist Figure 1 In the concatenated code scenario, a first interleaver is further added between the first FEC encoder and the second FEC encoder to further reduce the bit error rate. In some embodiments, the first interleaver can be a convolutional interleaver. Accordingly, a first deinterleaver is included between the second FEC decoder and the first FEC decoder of the receiving end device, and the first deinterleaver can also be a convolutional deinterleaver. Figure 2A After being encoded by the first FEC encoder, the data enters the first interleaver. The first interleaver interleaves the data from the first FEC encoder. The interleaved data enters the second FEC encoder. After being encoded by the second FEC encoder, it is sent to the second FEC decoder of the receiving device through the channel. The second FEC decoder corresponds to the second FEC encoder and is used to decode the data encoded by the second FEC encoder. The data decoded by the second FEC decoder enters the first deinterleaver to deinterleave the incoming data. The deinterleaved data enters the first FEC decoder to perform FEC decoding on the incoming data. According to Figure 2B After being encoded by the first and second FEC encoders, the data reaches the first interleaver. The first interleaver interleaves the data from the first FEC encoder and transmits the interleaved data to the receiving device via a channel. The data stream received by the receiving device is deinterleaved by the first deinterleaver, decoded by the second FEC decoder, and decoded by the first FEC decoder to obtain the original data.

[0083] The second FEC decoder can use soft decision decoding (SDD). Using soft decision decoding for the inner code makes almost all received codewords correctable, allowing the number of bit errors to be directly determined. This results in slightly different bit error statistics from those for RS codes. For uncorrectable codewords, the number of bit errors can be set to the minimum Hamming distance d of the inner code. The error statistics for the second FEC decoder using SDD for the inner code may differ slightly from the actual number of bit errors, but statistical data can be used to help mitigate this discrepancy. If the inner code uses hard decision decoding (HDD), the aforementioned SDD error statistics can also be used.

[0084] like Figure 2C to Figure 2E ,exist Figure 2A and / or Figure 2BOn this basis, one or more interleavers can be further added to the transmitting device to further reduce the bit error rate through multiple interleaving. Correspondingly, the receiving device can also further add one or more deinterleavers to deinterleave the received code stream that has undergone multiple interleaving. One or more of the one or more interleavers further added can also be convolutional interleavers. Correspondingly, one or more of the one or more deinterleavers further added to the receiving device can also be convolutional deinterleavers. Figure 2C to Figure 2E and Figure 2L to Figure 2N Each of the given two interleavers ( Figure 2C to Figure 2E and Figure 2L to Figure 2N In a concatenated code scenario of any one of the first interleaver and the second interleaver shown in , the logical structure of the transmitting device and the receiving device.

[0085] On the basis of the concatenated code including multiple interleavers, the bit error rate can be further reduced by adding a data position converter in the transmitting device and receiving a data position inverse converter corresponding to the data position converter in the receiving device. Figure 2F and Figure 2G Shows a 1-interleaver ( Figure 2F and Figure 2G The logical structure of the transmitting device and the receiving device in the cascade code scenario of the first interleaver) and the data position converter shown. Figure 2L to Figure 2N Shows a 2-interleaver ( Figure 2L to Figure 2N The logical structure of the transmitting end device and the receiving end device in the cascade code scenario of the first interleaver and the second interleaver) and the data position converter shown.

[0086] like Figure 3 As shown, an embodiment of the present application provides a method for processing an Ethernet data stream, which is applied to a receiving device including a first FEC decoder and a second FEC decoder, and the method includes:

[0087] S10: Acquire transmission information of the first data stream.

[0088] Specifically, the first data stream is a data stream sent from a transmitting device to a receiving device, and the receiving device obtains transmission information of the first data stream based on the first data stream. In some embodiments, the transmission information includes one or more of the following: bit error rate (BER), number of error bits, symbol error rate (SER), number of error symbols, codeword error rate (CER), number of error codewords, channel state information (CSI), and eye diagram parameters of the first data stream. The channel state information includes frequency response. Frequency response refers to the phenomenon that when a constant voltage output electrical signal is connected to a system, the sound pressure generated by a speaker increases or decreases with frequency and the phase changes with frequency. This relationship between sound pressure and phase and frequency is called frequency response. It also refers to the frequency range that a system can reproduce within the allowed amplitude range, and the amount of signal variation within this range is called frequency response, also known as frequency characteristics. Key eye diagram parameters include extinction ratio, jitter, crossing point, rise time, fall time, and margin. The extinction ratio is defined as the ratio of the "1" level to the "0" level in the eye diagram. The extinction ratio requirements vary depending on the rate, transmission distance, and laser type. The extinction ratio is a very important parameter in the measurement of optical communication transmitters, and its size determines the quality of the communication signal.

[0089] The sending device can be Figures 1 to 2N The receiving device can be any of the sending end devices shown in Figures 1 to 2N In any of the receiving devices shown in , the sending device includes a first FEC encoder and a second FEC encoder. Correspondingly, the receiving device includes a second FEC decoder and a first FEC decoder. The first FEC encoder of the sending device corresponds to the first FEC decoder of the receiving device, and the second FEC encoder of the sending device corresponds to the second FEC decoder of the receiving device.

[0090] S20: If the transmission information meets a trigger condition, adjust the error correction capability of the receiving device.

[0091] The receiving end device obtains the transmission information of the first data stream, determines whether the transmission information meets the trigger condition, and if so, adjusts the error correction capability of the receiving end device. In some embodiments, the receiving end device is Figures 1 to 2N The receiving device described in any one of the above, wherein the trigger condition is related to the number of error units at the first FEC decoder and / or the second FEC decoder. In some embodiments, the error unit includes a codeword, a bit, a symbol, or a bit group containing any number of bits.

[0092] In some embodiments, the receiving device may be Figures 1 to 2N The receiving end device shown in any one of the above, the transmission information includes the BER of the first data stream, and the adjustment of the error correction capability of the receiving end device may include any one of the following (1) to (3):

[0093] (1) Enable configuration 1 of the SDD of the second FEC decoder;

[0094] (2) enabling configuration 2 of the SDD of the second FEC decoder;

[0095] (3) enabling the HDD of the second FEC decoder;

[0096] (4) Disable the second FEC decoder.

[0097] The error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 of the SDD of the second FEC decoder is stronger than that of the HDD of the second FEC decoder.

[0098] In some embodiments, the receiving device may be Figures 1 to 2N The receiving end device shown in any one of the preceding claims, the transmission information includes the BER of the first data stream, and the trigger condition includes one of the following (a) to (e):

[0099] (a) The BER of the first data stream satisfies BER<=a;

[0100] (b) The BER of the first data stream satisfies a <BER<=b;

[0101] (c) The BER of the first data stream satisfies b <BER<=c;

[0102] (d) The BER of the first data stream satisfies c <BER<=d;

[0103] (e) The BER of the first data stream satisfies d <BER<=e;

[0104] Where a>0.

[0105] Accordingly, if the transmission information satisfies one of the above trigger conditions (a) to (e), the receiving device is Figures 2A to 2E 、 Figure 2H to Figure 2N The receiving end device shown in any one of the above, the receiving end device includes a first FEC decoder, a second FEC decoder and a first deinterleaver, and adjusting the error correction capability of the receiving end device includes any one of the following (A) to (E):

[0106] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder and the first deinterleaver, where a > 0;

[0107] (B) When the BER of the first data stream satisfies a < BER <= b, disable the first deinterleaver and enable the HDD of the second FEC decoder;

[0108] (C) When the BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver and enable Configuration 2 of the SDD of the second FEC decoder;

[0109] (D) When the BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and enable Configuration 1 of the SDD of the second FEC decoder;

[0110] (E) When the BER of the first data stream satisfies d < BER <= e, enable Configuration 1 of the SDD of the second FEC decoder and the first deinterleaver.

[0111] Correspondingly, if the transmission information meets one of the above triggering conditions (a) to (e), the receiving-end device is Figure 2C to Figure 2E any of the receiving-end devices shown in, and the receiving-end device includes a first FEC decoder, a second FEC decoder, a first deinterleaver, and a second deinterleaver. Adjusting the error correction ability of the receiving-end device includes any one of the following (A) to (E):

[0112] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder, the first deinterleaver, and the second deinterleaver, where a > 0;

[0113] (B) When the BER of the first data stream satisfies a < BER <= b, disable the first deinterleaver and the second deinterleaver, and enable the HDD of the second FEC decoder;

[0114] (C) When the BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver and the second deinterleaver, and enable the SDD of the second FEC decoder;

[0115] (D) When the BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and the second deinterleaver and enable the SDD of the second FEC decoder;

[0116] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the first deinterleaver.

[0117] Correspondingly, if the transmitted information meets one of the above triggering conditions (a) to (e), the receiving end device is Figure 2F and Figure 2G the receiving end device shown, the receiving end device includes a first FEC decoder, a second FEC decoder, and a data position inverse converter. Adjusting the error correction ability of the receiving end device includes any one of the following (A) to (E):

[0118] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder and the data position inverse converter;

[0119] (B) When the BER of the first data stream satisfies a < BER <= b, disable the second FEC decoder and enable the data position inverse converter;

[0120] (C) When the BER of the first data stream satisfies b < BER <= c, disable the data position inverse converter and enable the HDD of the second FEC decoder;

[0121] (D) When the BER of the first data stream satisfies c < BER <= d, disable the data position inverse converter and enable the SDD of the second FEC decoder;

[0122] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the data position inverse converter.

[0123] Correspondingly, if the transmitted information meets one of the above triggering conditions (a) to (e), the receiving end device is Figure 2H to Figure 2N any one of the receiving end devices shown. The receiving end device includes a first FEC decoder, a second FEC decoder, a data position inverse converter, and a first deinterleaver. The data position inverse converter is used to perform an inverse transformation operation on the positions of the data bits or symbols whose positions have been transformed by the data position converter. Then, adjusting the error correction ability of the receiving end device includes any one of the following (A) to (E):

[0124] (A) When the BER of the first data stream satisfies BER <= a, disable the data position inverse converter, the second FEC decoder, and the first deinterleaver, a > 0;

[0125] (B) When the BER of the first data stream satisfies a < BER <= b, disable the data position inverse converter and the first deinterleaver, and enable the HDD of the second FEC decoder;

[0126] (C) The BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver, and enable the SDD of the second FEC decoder;

[0127] (D) The BER of the first data stream satisfies c < BER <= d, disable the data position inverse converter and enable the first deinterleaver and the SDD of the second FEC decoder;

[0128] (E) The BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder, the data position inverse converter, and the first deinterleaver.

[0129] Correspondingly, if the transmitted information satisfies one of the above trigger conditions (a) to (e), the receiving end device is Figure 2L to Figure 2N any of the receiving end devices shown in, the receiving end device includes a first FEC decoder, a second FEC decoder, a data position inverse converter, a first deinterleaver, and a second deinterleaver, and the data position inverse converter is used to perform an inverse transformation operation on the positions of the received data bits or symbols whose positions have been transformed by the data position converter, then adjust the error correction ability of the receiving end device, including any one of the following (A) to (E):

[0130] (A) The BER of the first data stream satisfies BER <= a, disable the data position inverse converter, the second FEC decoder, the first deinterleaver, and the second deinterleaver, a > 0;

[0131] (B) The BER of the first data stream satisfies a < BER <= b, disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the HDD of the second FEC decoder;

[0132] (C) The BER of the first data stream satisfies b < BER <= c, disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the SDD of the second FEC decoder;

[0133] (D) The BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and enable the SDD of the second FEC decoder;

[0134] (E) The BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the first deinterleaver.

[0135] In some embodiments, the receiving end device may be Figures 1 to 2NThe receiving end device shown in any one of the above, wherein the transmission information includes the number of codeword errors in the first data stream, and adjusting the error correction capability of the receiving end device includes one of the following (a) to (e):

[0136] (1) disabling the second FEC decoder;

[0137] (II) enabling the HDD of the second FEC decoder;

[0138] (III) enabling configuration 2 of the SDD of the second FEC decoder;

[0139] (IV) enabling SDD configuration 1 of the second FEC decoder;

[0140] (V) enabling the FEC decoder to be configured as Configuration 1 of SDD and enabling Configuration 2 of the first deinterleaver;

[0141] (VI) Enable Configuration 1 of the second FEC decoder and enable Configuration 1 of the first deinterleaver

[0142] Accordingly, if the transmission information satisfies one of the above trigger conditions (I) to (IV), the receiving end device may be Figures 1 to 2N The receiving end device shown in any one of the above, the receiving end device includes a first FEC decoder and a second FEC decoder, and the transmission information includes one of the following (I) to (VI):

[0143] (I) the number of bit errors in P codewords at the second FEC decoder is less than J, where P and J are positive integers and P>J>1;

[0144] (II) the number of bit errors in the P codewords at the second FEC decoder is less than K, where K is a positive integer and K>J;

[0145] (III) the number of bit errors in the P codewords at the second FEC decoder is less than L, where L is a positive integer and L>K;

[0146] (IV) the number of bit errors in the P codewords at the second FEC decoder is less than M, where M>L;

[0147] (V) the number of bit errors in the P codewords at the second FEC decoder is less than N, where N>M;

[0148] (VI) If none of (I) to (V) are satisfied.

[0149] Accordingly, if the transmission information satisfies one of the above trigger conditions (I) to (VI), the receiving device may be Figures 1 to 2NIn any of the receiving end devices shown in , the receiving end device includes a first FEC decoder and a second FEC decoder, and adjusting the error correction capability of the receiving end device includes any of the following:

[0150] (I) if the number of bit errors in P codewords at the second FEC decoder is less than J, where P and J are positive integers and P>J>1, disabling the second FEC decoder;

[0151] (II) if the number of bit errors in the P codewords at the second FEC decoder is less than K, where K is a positive integer and K>J, then enabling HDD of the second FEC decoder;

[0152] (III) if the number of bit errors in the P codewords at the second FEC decoder is less than L, where L is a positive integer and L>K, then enable configuration 2 of the SDD of the second FEC decoder;

[0153] (IV) If the number of bit errors in the P codewords at the second FEC decoder is less than M, where M>L, then SDD configuration 1 of the second FEC decoder is enabled.

[0154] The error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 is higher than that of the HDD of the second FEC decoder.

[0155] Accordingly, if the transmission information satisfies one of the trigger conditions (I) to (VI) above, in some embodiments, the receiving device may be Figures 2A to 2E 、 Figure 2H to Figure 2N The receiving end device shown in any one of the above, wherein the receiving end device includes a first FEC decoder, a second FEC decoder, and a first deinterleaver, and if the transmission information meets the trigger condition, adjusting the error correction capability of the receiving end device includes one of (I)-(VI):

[0156] (I) if the number of bit errors in P codewords at the second FEC decoder is less than J, disabling the first deinterleaver and the second FEC decoder, where P and J are positive integers and P>J>1;

[0157] (II) if the number of bit errors in the P codewords at the second FEC decoder is less than K, disabling the first deinterleaver and enabling the HDD of the second FEC decoder, where K is a positive integer and K>J;

[0158] (III) if the number of bit errors in the P codewords at the second FEC decoder is less than L, then disabling the first deinterleaver and enabling configuration 2 of the SDD of the second FEC decoder, where L is a positive integer and L>K;

[0159] (IV) if the number of bit errors in the P codewords at the second FEC decoder is less than M, then disabling the first deinterleaver and enabling configuration 1 of the second FEC decoder SDD, where M>L;

[0160] (V) if the number of bit errors in the P codewords at the second FEC decoder is less than N, then enabling Configuration 1 of the SDD of the FEC decoder and enabling Configuration 2 of the first deinterleaver, where N>M;

[0161] (VI) If none of (1) to (5) is satisfied, then enable Configuration 1 of the second FEC decoder and enable Configuration 1 of the first deinterleaver.

[0162] Accordingly, if the transmission information satisfies one of the trigger conditions (I) to (VI), in some embodiments, the receiving device may be Figure 2F and Figure 2G The receiving end device shown in any one of the above, wherein the receiving end device includes a first FEC decoder, a second FEC decoder, and a data position inverse transformer, and if the transmission information meets the trigger condition, adjusting the error correction capability of the receiving end device includes one of (I)-(VI):

[0163] (I) if the number of bit errors in P codewords at the second FEC decoder is less than J, disabling the data position inverse transformer and the second FEC decoder, where P and J are positive integers and P>J>1;

[0164] (II) if the number of bit errors in the P codewords at the second FEC decoder is less than K, then disabling the second FEC decoder and enabling the inverse data position transformer, where K is a positive integer and K>J;

[0165] (III) if the number of bit errors in the P codewords at the second FEC decoder is less than L, disabling the inverse data position converter and enabling the HDD of the second FEC decoder, where L is a positive integer and L>K;

[0166] (IV) if the number of bit errors in the P codewords at the second FEC decoder is less than M, then disabling the inverse data position transformer and enabling configuration 2 of the SDD of the second FEC decoder, where M>L;

[0167] (V) if the number of bit errors in the P codewords at the second FEC decoder is less than N, then disabling the inverse data position transformer and enabling the FEC decoder to be configured as SDD Configuration 1, where N>M;

[0168] (VI) If none of (I) to (V) is satisfied, then enable configuration 1 of the SDD of the second FEC decoder and enable the inverse data position transformer.

[0169] Accordingly, if the transmission information satisfies one of the trigger conditions (I) to (VI) above, in some embodiments, the receiving device may be Figure 2C to Figure 2E 、 Figure 2L to Figure 2N The receiving end device shown in any one of the above, wherein the receiving end device includes a first FEC decoder, a second FEC decoder, a first deinterleaver, and a second deinterleaver, and if the transmission information meets the trigger condition, adjusting the error correction capability of the receiving end device includes one of (I)-(VI):

[0170] (I) if the number of bit errors in P codewords at the second FEC decoder is less than J, disabling the first deinterleaver, the second deinterleaver, and the second FEC decoder, where P and J are positive integers and P>J>1;

[0171] (II) if the number of bit errors in the P codewords at the second FEC decoder is less than K, disabling the second deinterleaver and the second FEC decoder and enabling the first deinterleaver, where K is a positive integer and K>J;

[0172] (III) if the number of bit errors in the P codewords at the second FEC decoder is less than L, disabling the second FEC decoder and enabling the first deinterleaver and the second deinterleaver, where L is a positive integer and L>K;

[0173] (IV) if the number of bit errors in the P codewords at the second FEC decoder is less than M, disabling the first deinterleaver and the second deinterleaver and enabling the HDD of the second FEC decoder, where M>L;

[0174] (V) if the number of bit errors in the P codewords at the second FEC decoder is less than N, then disabling the first deinterleaver and the second deinterleaver and enabling Configuration 2 of the SDD of the second FEC decoder, where N>M;

[0175] (VI) If none of (1) to (5) is satisfied, disabling the first deinterleaver and the second deinterleaver and enabling configuration 1 of the SDD of the second FEC decoder.

[0176] Accordingly, if the transmission information satisfies one of the trigger conditions (I) to (VI) above, in some embodiments, the receiving device may be Figure 2L to Figure 2NThe receiving end device shown in any one of the above, wherein the receiving end device includes a first FEC decoder, a second FEC decoder, a first deinterleaver, a second deinterleaver, and a data position inverse transformer, and if the transmission information meets the trigger condition, adjusting the error correction capability of the receiving end device includes one of (I)-(VI):

[0177] (I) if the number of bit errors in P codewords at the second FEC decoder is less than J, disabling the first deinterleaver, the second deinterleaver, the second FEC decoder, and the inverse data position transformer, where P and J are positive integers and P>J>1;

[0178] (II) if the number of bit errors in the P codewords at the second FEC decoder is less than K, disabling the second deinterleaver, the second FEC decoder, and the data position inverse transformer, and enabling the first deinterleaver, where K is a positive integer and K>J;

[0179] (III) if the number of bit errors in the P codewords at the second FEC decoder is less than L, then disabling the second FEC decoder and enabling the first deinterleaver, the second deinterleaver, and the inverse data position transformer, where L is a positive integer and L>K;

[0180] (IV) if the number of bit errors in the P codewords at the second FEC decoder is less than M, disabling the first deinterleaver, the data position inverse transformer, and the second deinterleaver and enabling the HDD of the second FEC decoder, where M>L;

[0181] (V) if the number of bit errors in the P codewords at the second FEC decoder is less than N, then disabling the first deinterleaver and the second deinterleaver and enabling Configuration 2 of the SDD of the second FEC decoder, where N>M;

[0182] (VI) If none of (1) to (5) is satisfied, disabling the first deinterleaver and the second deinterleaver and enabling configuration 1 of the SDD of the second FEC decoder.

[0183] The deinterleaving delay and / or power consumption of configuration 1 of the first deinterleaver is higher than the deinterleaving delay and / or power consumption of configuration 2 of the first deinterleaver; the error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than the error correction capability of configuration 2, and the error correction capability of configuration 2 is higher than the error correction capability of the HDD of the second FEC decoder. The error correction capabilities of the first deinterleaver and the second FEC decoder are higher than the function of the data position inverse transformer.

[0184] In some embodiments, the receiving device may be Figures 1 to 2NThe receiving end device shown in any one of the above, the transmission information includes the number of error units of the first data stream. In some embodiments, the transmission information includes one or more of the bit error rate BER, the number of error bits, the symbol error rate SER, the number of error symbols, the codeword error rate CER, the number of error codewords, channel state information, and eye diagram parameters of the first data stream. Taking the error unit as an error codeword as an example, the trigger condition includes the following: the receiving end device can be Figures 2A to 2E and Figure 2H to Figure 2N The receiving end device shown in any one of the preceding claims, wherein the receiving end device further includes a first deinterleaver, and adjusting the error correction capability of the receiving end device includes any one of the following:

[0185] ① Enable configuration 1 of the soft decision decoding SDD of the second FEC decoder and enable configuration 1 of the first deinterleaver;

[0186] ② Enable configuration 1 of the SDD of the second FEC decoder and enable configuration 2 of the first deinterleaver;

[0187] ③ Enable SDD configuration 1 of the second FEC decoder and disable the first deinterleaver;

[0188] ④ Enable configuration 2 of the SDD of the second FEC decoder and disable the first deinterleaver;

[0189] 5. Enable the hard decision decoding HDD of the second FEC decoder and disable the first deinterleaver;

[0190] 6. Disabling the second FEC decoder and the first deinterleaver;

[0191] The deinterleaving delay and / or power consumption of configuration 1 of the first deinterleaver is higher than the deinterleaving delay and / or power consumption of configuration 2 of the first deinterleaver; the error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than the error correction capability of configuration 2, and the error correction capability of configuration 2 is higher than the error correction capability of the HDD of the second FEC decoder. The error correction capabilities of the first deinterleaver and the second FEC decoder are higher than the function of the data position inverse transformer.

[0192] Accordingly, if the transmission information satisfies one of the above trigger conditions ① to ⑥, in some embodiments, the receiving end device may be Figures 2A to 2E 、 Figure 2H to Figure 2N The receiving end device shown in any one of the above, wherein the receiving end device includes a first FEC decoder, a second FEC decoder, and a first deinterleaver, and if the transmission information meets the triggering condition, adjusting the error correction capability of the receiving end device includes one of ① to ⑥:

[0193] ① If the number of bit errors in P codewords at the second FEC decoder is less than J, then configuration 1 of the soft decision decoding SDD of the second FEC decoder is enabled and configuration 1 of the first deinterleaver is enabled, where P and J are positive integers and P>J>1;

[0194] ② If the number of bit errors in the P codewords at the second FEC decoder is less than K, then enable configuration 1 of the SDD of the second FEC decoder and enable configuration 2 of the first deinterleaver, where K is a positive integer and K>J;

[0195] ③ If the number of bit errors in the P codewords at the second FEC decoder is less than L, enable SDD configuration 1 of the second FEC decoder and disable the first deinterleaver, where L is a positive integer and L>K;

[0196] ④ If the number of bit errors in the P codewords at the second FEC decoder is less than M, then enable configuration 2 of the SDD of the second FEC decoder and disable the first deinterleaver, where M>L;

[0197] ⑤ If the number of bit errors in the P codewords at the second FEC decoder is less than N, enabling the hard decision decoding HDD of the second FEC decoder and disabling the first deinterleaver, where N>M;

[0198] ⑥ If none of ① to ⑤ are satisfied, disable the second FEC decoder and the first deinterleaver.

[0199] Specifically, an example of using a threshold of the received BER as a trigger condition to trigger adjustment of the error correction capability of the receiving end device can be referred to Table 1.

[0200] Table 1

[0201]

[0202] In some embodiments, the receiving device may be Figures 1 to 2N In any of the receiving end devices shown in , when the receiving end device receives a manually triggered first indication, if the first indication does not include information on how to adjust, the error correction capability of the receiving end device is adjusted according to a first preset method. In some embodiments, the first indication may be located in a register of the receiving end device and / or the first indication may be triggered by a primitive. In some embodiments, the first preset method may include any one of the following (1) to (3):

[0203] (1) Enable configuration 1 of the SDD of the second FEC decoder;

[0204] (2) enabling configuration 2 of the SDD of the second FEC decoder;

[0205] (3) enabling the HDD of the second FEC decoder;

[0206] (4) Disable the second FEC decoder.

[0207] The error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 of the SDD of the second FEC decoder is stronger than that of the HDD of the second FEC decoder.

[0208] In some embodiments, the receiving device is Figures 2A to 2E 、 Figure 2H to Figure 2N The receiving end device shown in any one of the above, the receiving end device includes a first FEC decoder, a second FEC decoder and a first deinterleaver, and the first preset method includes any one of the following (A) to (E):

[0209] (A) disabling the second FEC decoder and the first deinterleaver;

[0210] (B) disabling the first deinterleaver and enabling the HDD of the second FEC decoder;

[0211] (C) disabling the first deinterleaver and enabling configuration 2 of the SDD of the second FEC decoder;

[0212] (D) disabling configuration 1 of the first deinterleaver and enabling the SDD of the second FEC decoder;

[0213] (E) Enable Configuration 1 of the SDD of the second FEC decoder and the first deinterleaver.

[0214] In some embodiments, the receiving device is Figure 2C to Figure 2E The receiving end device shown in any one of the above, the receiving end device includes a first FEC decoder, a second FEC decoder, a first deinterleaver and a second deinterleaver, and the first preset method includes any one of the following (A) to (E):

[0215] (A) disabling the second FEC decoder, the first deinterleaver, and the second deinterleaver;

[0216] (B) disabling the first deinterleaver and the second deinterleaver, and enabling the HDD of the second FEC decoder;

[0217] (C) disabling the first deinterleaver and the second deinterleaver, and enabling the SDD of the second FEC decoder;

[0218] (D) disabling the first deinterleaver and the second deinterleaver and enabling the SDD of the second FEC decoder;

[0219] (E) Enabling the SDD of the second FEC decoder and the first deinterleaver.

[0220] In some embodiments, the receiving device is Figure 2F and Figure 2G The receiving end device shown in the figure includes a first FEC decoder, a second FEC decoder and a data position inverse transformer, and the first preset mode includes any one of the following (A) to (E):

[0221] (A) disabling the second FEC decoder and the data position inverse transformer;

[0222] (B) disabling the second FEC decoder and enabling the data position inverse transformer;

[0223] (C) disabling the data position inverse converter and enabling the HDD of the second FEC decoder;

[0224] (D) disabling the data position inverse transformer and enabling the SDD of the second FEC decoder;

[0225] (E) Enabling the SDD of the second FEC decoder and the inverse data position transformer.

[0226] In some embodiments, the receiving device is Figure 2H to Figure 2N The receiving end device shown in any one of the above, the receiving end device includes a first FEC decoder, a second FEC decoder, a data position inverse transformer and a first deinterleaver, the data position inverse transformer is used to perform an inverse transformation operation on the position of the received data bits or symbols whose positions have been transformed by the data position transformer, then the first preset mode includes any one of the following (A) to (E):

[0227] (A) disabling the data position inverse transformer, the second FEC decoder, and the first deinterleaver;

[0228] (B) disabling the data position inverse transformer and the first deinterleaver, and enabling the HDD of the second FEC decoder;

[0229] (C) disabling the first deinterleaver and enabling the SDD of the second FEC decoder;

[0230] (D) disabling the data position inverse transformer and enabling the SDDs of the first deinterleaver and the second FEC decoder;

[0231] (E) Enable the SDD of the second FEC decoder, the data position inverse converter, and the first deinterleaver.

[0232] In some embodiments, the receiving-end device is Figure 2L to Figure 2N any of the receiving-end devices shown in, the receiving-end device includes a first FEC decoder, a second FEC decoder, a data position inverse converter, a first deinterleaver, and a second deinterleaver, the data position inverse converter is configured to perform an inverse transformation operation on the positions of the received data bits or symbols whose positions have been transformed by a data position converter, and the first indication includes any one of the following (A) to (E):

[0233] (A) Disable the data position inverse converter, the second FEC decoder, the first deinterleaver, and the second deinterleaver;

[0234] (B) Disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the HDD of the second FEC decoder;

[0235] (C) Disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the SDD of the second FEC decoder;

[0236] (D) Disable the first deinterleaver and enable the SDD of the second FEC decoder;

[0237] (E) Enable the SDD of the second FEC decoder and the first deinterleaver.

[0238] In some embodiments, the first indication includes information on how to adjust the error correction capability of the receiving-end device. The first indication may include any one of the above (1) to (3), so that the receiving-end device can adjust the error correction capability of the receiving-end device according to the content included in the first indication.

[0239] In some embodiments, the receiving-end device is Figures 2A to 2E 、 Figure 2H to Figure 2N any of the receiving-end devices shown in, the receiving-end device includes a first FEC decoder, a second FEC decoder, and a first deinterleaver, and the first indication includes any one of the following (A) to (E):

[0240] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder and the first deinterleaver, where a > 0;

[0241] (B) When the BER of the first data stream satisfies a < BER <= b, disable the first deinterleaver and enable the HDD of the second FEC decoder;

[0242] (C) When the BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver and enable the SDD of the second FEC decoder in configuration 2;

[0243] (D) When the BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and enable the SDD of the second FEC decoder in configuration 1;

[0244] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder in configuration 1 and the first deinterleaver.

[0245] In some embodiments, the receiving-end device is Figure 2C to Figure 2E and Figure 2L to Figure 2N any of the receiving-end devices shown in, the receiving-end device includes a first FEC decoder, a second FEC decoder, a first deinterleaver and a second deinterleaver, and the first indication includes any one of the following (A) to (E):

[0246] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder, the first deinterleaver and the second deinterleaver, where a > 0;

[0247] (B) When the BER of the first data stream satisfies a < BER <= b, disable the first deinterleaver and the second deinterleaver, and enable the HDD of the second FEC decoder;

[0248] (C) When the BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver and the second deinterleaver, and enable the SDD of the second FEC decoder;

[0249] (D) When the BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and the second deinterleaver and enable the SDD of the second FEC decoder;

[0250] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the first deinterleaver.

[0251] In some embodiments, the receiving-end device is Figure 2F and Figure 2G the receiving-end device shown in, the receiving-end device includes a first FEC decoder, a second FEC decoder and a data position inverse converter, and the first indication includes any one of the following (A) to (E):

[0252] (A) When the BER of the first data stream satisfies BER <= a, disable the second FEC decoder and the data position inverse converter, where a > 0;

[0253] (B) When the BER of the first data stream satisfies a < BER <= b, disable the second FEC decoder and enable the data position inverse converter;

[0254] (C) When the BER of the first data stream satisfies b < BER <= c, disable the data position inverse converter and enable the HDD of the second FEC decoder;

[0255] (D) When the BER of the first data stream satisfies c < BER <= d, disable the data position inverse converter and enable the SDD of the second FEC decoder;

[0256] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the data position inverse converter.

[0257] In some embodiments, the receiving end device is Figure 2H to Figure 2N the receiving end device shown in any of

[0258] (A) When the BER of the first data stream satisfies BER <= a, disable the data position inverse converter, the second FEC decoder and the first deinterleaver, where a > 0;

[0259] (B) When the BER of the first data stream satisfies a < BER <= b, disable the data position inverse converter and the first deinterleaver, and enable the HDD of the second FEC decoder;

[0260] (C) When the BER of the first data stream satisfies b < BER <= c, disable the first deinterleaver, and enable the SDD of the second FEC decoder;

[0261] (D) When the BER of the first data stream satisfies c < BER <= d, disable the data position inverse converter and enable the first deinterleaver and the SDD of the second FEC decoder;

[0262] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder, the data position inverse converter and the first deinterleaver.

[0263] In some embodiments, the receiving-end device is Figure 2L to Figure 2N any one of the receiving-end devices shown in

[0264] (A) When the BER of the first data stream satisfies BER <= a, disable the data position inverse transformer, the second FEC decoder, the first deinterleaver, and the second deinterleaver, where a > 0;

[0265] (B) When the BER of the first data stream satisfies a < BER <= b, disable the data position inverse transformer, the second deinterleaver, and the first deinterleaver, and enable the HDD of the second FEC decoder;

[0266] (C) When the BER of the first data stream satisfies b < BER <= c, disable the data position inverse transformer, the second deinterleaver, and the first deinterleaver, and enable the SDD of the second FEC decoder;

[0267] (D) When the BER of the first data stream satisfies c < BER <= d, disable the first deinterleaver and enable the SDD of the second FEC decoder;

[0268] (E) When the BER of the first data stream satisfies d < BER <= e, enable the SDD of the second FEC decoder and the first deinterleaver.

[0269] Embodiments of the present application further provide another method for processing an Ethernet physical layer data stream, which is executed by a sending-end device. The sending-end device may be Figures 1 to 2N any one of the sending-end devices described above. The method includes: configuring the data stream processing mode of the sending-end device based on a second indication.

[0270] In some embodiments, the second indication includes information on how to configure the data stream processing mode of the sending-end device.

[0271] In some embodiments, the second indication is in the register of the sending-end device and / or the second indication is triggered by a primitive.

[0272] In some embodiments, the second indication comes from a receiving-end device corresponding to the sending-end device.

[0273] In some embodiments, the sending-end device may be Figures 1 to 2NThe transmitting end device shown in any one of the above, the transmitting end device includes a first FEC encoder and a second FEC encoder, and the second indication may include any one of the following (1) to (3):

[0274] (1) Enable configuration 1 of the SDD of the second FEC encoder;

[0275] (2) enabling configuration 2 of the SDD of the second FEC encoder;

[0276] (3) enabling the HDD of the second FEC encoder;

[0277] (4) Disable the second FEC decoder.

[0278] The error correction capability of configuration 1 of the SDD of the second FEC encoder is higher than that of configuration 2, and the error correction capability of configuration 2 is higher than that of the HDD of the second FEC encoder.

[0279] In some embodiments, the sending device may be Figures 2A to 2E 、 Figure 2H to Figure 2N The transmitting end device shown in any one of the above, wherein the transmitting end device includes a first FEC encoder, a second FEC encoder, and a first interleaver, and the second indication may include any one of the following ① to ⑥:

[0280] ① Enable configuration 1 of the SDD of the second FEC encoder and enable configuration 1 of the first interleaver;

[0281] ② Enable configuration 1 of the SDD of the second FEC encoder and enable configuration 2 of the first interleaver;

[0282] ③ Enable SDD configuration 1 of the second FEC encoder and disable the first interleaver;

[0283] ④ Enable configuration 2 of the SDD of the second FEC encoder and disable the first interleaver;

[0284] 5. Enable the HDD of the second FEC encoder and disable the first interleaver;

[0285] 6. Disabling the second FEC encoder and the first interleaver;

[0286] In some embodiments, the sending device is Figures 2A to 2E 、 Figure 2H to Figure 2N The transmitting end device shown in any one of the above, the receiving end device includes a first FEC encoder, a second FEC encoder and a first interleaver, and the second indication includes any one of the following (A) to (E):

[0287] (A) disabling the second FEC encoder and the first interleaver;

[0288] (B) disabling the first interleaver and enabling the HDD of the second FEC encoder;

[0289] (C) disabling the first interleaver and enabling configuration 2 of the SDD of the second FEC encoder;

[0290] (D) disabling configuration 1 of the first interleaver and enabling the SDD of the second FEC encoder;

[0291] (E) Enabling Configuration 1 of the SDD of the second FEC encoder and the first interleaver.

[0292] In some embodiments, the sending device is Figure 2C to Figure 2E and Figure 2L to Figure 2N The transmitting end device shown in any one of the above, the transmitting end device includes a first FEC encoder, a second FEC encoder, a first interleaver and a second interleaver, and the second preset mode includes any one of the following (A) to (E):

[0293] (A) disabling the second FEC encoder, the first interleaver, and the second interleaver;

[0294] (B) disabling the first interleaver and the second interleaver, and enabling the HDD of the second FEC encoder;

[0295] (C) disabling the first interleaver and the second interleaver, and enabling the SDD of the second FEC encoder;

[0296] (D) disabling the first interleaver and the second interleaver and enabling the SDD of the second FEC encoder;

[0297] (E) Enabling the SDD of the second FEC encoder and the first interleaver.

[0298] The interleaving delay and / or power consumption of configuration 1 of the first interleaver is higher than the interleaving delay and / or power consumption of configuration 2 of the first interleaver; the error correction capability of configuration 1 of the SDD of the second FEC encoder is higher than the error correction capability of configuration 2, and the error correction capability of configuration 2 is stronger than the error correction capability of the HDD of the second FEC encoder.

[0299] In some embodiments, the transmitting device may be Figure 2F and Figure 2G The transmitting end device shown in any one of the above, wherein the transmitting end device includes a first FEC encoder, a second FEC encoder and a data position converter, and the second indication includes one of (I)-(VI):

[0300] (1) disabling the data position converter and the second FEC encoder;

[0301] (II) disabling the second FEC encoder and enabling the data position converter;

[0302] (III) disabling the data relocation converter and enabling the HDD of the second FEC encoder;

[0303] (IV) disabling the data relocation converter and enabling configuration 2 of the SDD of the second FEC encoder;

[0304] (V) disabling the data position converter and enabling the FEC encoder to be configured as SDD configuration 1;

[0305] (VI) Enable Configuration 1 of the SDD of the second FEC encoder and enable the data location converter.

[0306] In some embodiments, the receiving device is Figure 2F and Figure 2G The receiving end device shown in FIG. 1 includes a first FEC encoder, a second FEC encoder, and a data position converter, and the second preset mode includes any one of the following (A) to (E):

[0307] (A) disabling the second FEC encoder and the data position converter;

[0308] (B) disabling the second FEC encoder and enabling the data position converter;

[0309] (C) disabling the data position inverse converter and enabling the HDD of the second FEC encoder;

[0310] (D) disabling the inverse data position transformer and enabling the SDD of the second FEC encoder;

[0311] (E) Enabling the SDD of the second FEC encoder and the data location converter.

[0312] In some embodiments, the transmitting device may be Figure 2C to Figure 2E 、 Figure 2H to Figure 2N The transmitting end device shown in any one of the above, wherein the transmitting end device includes a first FEC encoder, a second FEC encoder, a first interleaver and a second interleaver, and the indication includes one of (I)-(VI):

[0313] (1) disabling the first interleaver, the second interleaver, and the second FEC encoder;

[0314] (II) disabling the second interleaver and the second FEC encoder and enabling the first interleaver;

[0315] (III) disabling the second FEC encoder and enabling the first deinterleaver and the second interleaver;

[0316] (IV) disabling the first interleaver and the second deinterleaver and enabling the HDD of the second FEC encoder;

[0317] (V) disabling the first interleaver and the second interleaver and enabling configuration 2 of the SDD of the second FEC encoder;

[0318] (VI) Configuration 1 of disabling the first interleaver and the second interleaver and enabling the SDD of the second FEC encoder.

[0319] In some embodiments, the sending device is Figure 2H to Figure 2N The transmitting end device shown in any one of the above, wherein the transmitting end device includes a first FEC encoder, a second FEC encoder, a data position converter, and a first interleaver, wherein the data position converter is used to convert the position of the received data bits or symbols, the second preset mode includes any one of the following (A) to (E):

[0320] (A) disabling the data position converter, the second FEC encoder, and the first interleaver;

[0321] (B) disabling the data position converter and the first interleaver, and enabling the HDD of the second FEC encoder;

[0322] (C) disabling the first interleaver and enabling the SDD of the second FEC encoder;

[0323] (D) disabling the data position converter and enabling the SDDs of the first deinterleaver and the second FEC encoder;

[0324] (E) Enabling the SDD of the second FEC encoder, the data position converter, and the first interleaver.

[0325] In some embodiments, the sending device may be Figure 2L to Figure 2N The transmitting end device shown in any one of the preceding claims, the transmitting end device includes a first FEC encoder, a second FEC encoder, a data position converter, a first interleaver, and a second interleaver, the data position converter is used to convert the position of received data bits or symbols, and the indication may include any one of the following:

[0326] (1) disabling the data position converter, the second FEC encoder, the first interleaver, and the second interleaver;

[0327] (II) disabling the data position converter, the second interleaver, and the first interleaver, and enabling the HDD of the second FEC encoder;

[0328] (III) disabling the data position converter, the second interleaver, and the first interleaver, and enabling the SDD of the second FEC encoder;

[0329] (IV) disabling the first interleaver and enabling the SDD of the second FEC encoder;

[0330] (V) Enable SDD of the second FEC encoder.

[0331] In some embodiments, the sending device is Figure 2L to Figure 2N The transmitting end device shown in any one of the above, the transmitting end device includes a first FEC encoder, a second FEC encoder, a data position converter, a first interleaver and a second interleaver, the data position converter is used to convert the position of the received data bits or symbols, and the second preset mode includes any one of the following (A) to (E):

[0332] (A) disabling the data position inverse transformer, the second FEC decoder, the first deinterleaver, and the second deinterleaver;

[0333] (B) disabling the data position inverse transformer, the second deinterleaver, and the first deinterleaver, and enabling the HDD of the second FEC decoder;

[0334] (C) disabling the data position inverse transformer, the second deinterleaver, and the first deinterleaver, and enabling the SDD of the second FEC decoder;

[0335] (D) disabling the first deinterleaver and enabling the SDD of the second FEC decoder;

[0336] (E) Enabling the SDD of the second FEC decoder and the first deinterleaver.

[0337] The interleaving delay and / or power consumption of configuration 1 of the first interleaver is higher than the interleaving delay and / or power consumption of configuration 2 of the first interleaver; the error correction capability of configuration 1 of the SDD of the second FEC encoder is higher than the error correction capability of configuration 2, and the error correction capability of configuration 2 is higher than the error correction capability of the HDD of the second FEC encoder. The error correction capabilities of the first interleaver, the second interleaver, and the second FEC encoder are higher than the function of the data position converter.

[0338] In some embodiments, the transmitting device and the receiving device can jointly adjust the error correction capability of the data stream, that is, the receiving device adjusts the error correction capability of the data stream based on the first trigger condition, and the transmitting device adjusts the error correction capability of the data stream to be sent based on the second trigger condition.

[0339] In some embodiments, if the transmission information meets the trigger condition, when adjusting the error correction capability of the receiving device, the connection between the transmitting device and the receiving device can be interrupted. After the adjustment is completed, the connection is re-established with the adjusted configuration, and the data stream is transmitted according to the adjusted error correction capability of the receiving device.

[0340] Figures 1 to 2N The concatenated code method can effectively improve the transmission process of data streams with high bit error rates. However, in some scenarios, such as data stream transmission between devices in a data center, data stream transmission in high-speed computing, and artificial intelligence (AI), when the data stream transmission bit error rate is low or in some scenarios, when the data stream transmission bit error rate fluctuates slightly, the standard reliability requirements can be met without concatenated codes. Therefore, the embodiments of the present application provide a method for disabling some components or weakening the error correction capabilities of some components.

[0341] exist Figures 1 to 2N In the concatenated code scenario shown, the second FEC decoder can decode using both HDD and SDD modes. The adjustment methods in this scenario are shown in Table 1. To achieve optimal decoding error correction capability, the second FEC decoder's SDD configuration 1 can be enabled. When its error correction capability needs to be weakened, the second FEC decoder's SDD configuration 2 can be enabled. Compared to configuration 1, the second FEC decoder's soft decoding configuration 2 offers lower latency and / or power consumption. This can be achieved by reducing test patterns and / or changing the decoding algorithm. While the error correction performance of the second FEC decoder's soft decoding configuration 2 is weaker, it is still stronger than the second FEC decoder's hard decoding configuration. Therefore, data stream transmission latency and power consumption can be reduced by disabling the second FEC decoder or weakening its error correction capability. To weaken the second FEC decoder's error correction capability, the error correction capability of the second FEC decoder's SDD mode can be reduced to reduce data stream transmission latency and power consumption, or the second FEC decoder's SDD mode can be replaced with a hard decoding mode.

[0342] Table 1 is based on Figures 1 to 2N Adjustment method of cascade code scene

[0343] Adjustment method Second FEC decoder Method 1 Enable the second FEC decoder SDD configuration 1 Method 2 Enable the second FEC decoder SDD configuration 2 Method 3 Disable the second FEC decoder

[0344] exist Figures 2A to 2E and Figure 2H to Figure 2N In any of the cascade code scenarios shown in , the data stream transmission delay and power consumption can be reduced by disabling the second FEC decoder, disabling the interleaver, weakening the interleaving effect of the interleaver, and weakening the error correction capability of the second FEC decoder. The specific adjustment method is shown in Table 2.

[0345] The second FEC decoder and the first FEC decoder both count the number of bit errors during decoding, and set control information based on the number of bit errors and the judgment threshold. The control information is used to indicate the disabling information. In some embodiments, the disabling information includes a disenable_indicater control parameter, which is used to indicate the following adjustment methods in the transceiver device:

[0346] Table 2 is based on Figures 2A to 2E and Figure 2H to Figure 2N Adjustment method for any of the cascade code scenarios shown in

[0347] Adjustment method Second FEC decoder First deinterleaver Method 1 Enable the second FEC decoder SDD configuration 1 Enable first deinterleaver configuration 1 Method 2 Enable the second FEC decoder SDD configuration 1 Enable first deinterleaver configuration 2 Method 3 Enable the second FEC decoder SDD configuration 1 Disable the first deinterleaver Method 4 Enable the second FEC decoder SDD configuration 2 Disable the first deinterleaver Method 5 Enable the second FEC decoder HDD Disable the first deinterleaver Method 6 Disable the second FEC decoder Disable the first deinterleaver

[0348] In some embodiments, the first and / or second interleaver is a convolution interleaver. When the convolution interleaver is enabled, the convolution interleaver can be configured with different delays through a register, that is, the delay of each row of interleaving is set. Table 2 schematically shows two convolution interleaver configurations with different delays: configuration 1 and configuration 2, wherein the convolution interleaver delay and / or power consumption of configuration 1 is higher than the convolution interleaver delay and / or power consumption of configuration 2. In some embodiments, there may be more than two convolution interleaver configurations, for example, in addition to the aforementioned configurations 1 and 2, configurations 3, 4, ..., n with successively lower delays and / or power consumption may also be included.

[0349] Because the convolutional interleaver consumes more power and / or latency than the soft decoding of the second FEC decoder, reducing the convolutional interleaver configuration or disabling it is a priority. Convolutional interleaver configuration 2 offers lower latency and / or power consumption than configuration 1, which can be achieved by reducing the number of registers or modifying parameters. Consequently, configuration 2 results in reduced interleaving effectiveness and weaker error correction performance.

[0350] In some embodiments, Figures 1 to 2N The second FEC encoder and the second FEC decoder are disabled or enabled at the same time, that is, when the second FEC decoder is disabled, the second FEC encoder is also disabled; when the second FEC decoder is enabled, the second FEC encoder is also enabled.

[0351] In some embodiments, Figures 2A to 2E and Figure 2H to Figure 2NThe interleaver and deinterleaver shown in any one of the figures are enabled or disabled at the same time, that is, when the deinterleaver is disabled, the interleaver is also disabled at the same time; when the deinterleaver is enabled, the interleaver is also enabled at the same time.

[0352] If the number of bit errors of the first FEC decoder is not considered for judgment, and only the number of bit errors of the second FEC decoder and the threshold are used for size judgment, in some embodiments, the number of bit errors and the threshold can be processed in units of codewords, bits, symbols, or bit groups containing any number of bits. Taking codewords as an example, Figures 2A to 2E 、 Figure 2H to Figure 2N In any of the receiving devices shown in , various adjustment methods according to Table 2 are as follows:

[0353] (1) If the number of bit errors in the P codewords at the second FEC decoder is less than J, the deinterleaver is disabled ( Figures 2A to 2E 、 Figure 2H to Figure 2N any one of the first deinterleaver and / or second deinterleaver shown in ) and the second FEC decoder, wherein P and J are positive integers and P>J>1;

[0354] (2) If the number of bit errors in the P codewords at the second FEC decoder is less than K, the deinterleaver is disabled ( Figures 2A to 2E 、 Figure 2H to Figure 2N any one of the first deinterleaver and / or second deinterleaver shown in ) and enabling the HDD of the second FEC decoder, wherein K is a positive integer and K>J;

[0355] (3) If the number of bit errors in the P codewords at the second FEC decoder is less than L, the deinterleaver is disabled ( Figures 2A to 2E 、 Figure 2H to Figure 2N any one of the first deinterleaver and / or second deinterleaver shown in L) and enabling configuration 2 of the SDD of the second FEC decoder, where L is a positive integer and L>K;

[0356] (4) If the number of bit errors in the P codewords at the second FEC decoder is less than M, the deinterleaver is disabled ( Figures 2A to 2E 、 Figure 2H to Figure 2N any one of the first deinterleaver and / or second deinterleaver shown in ) and enabling configuration 1 of the second FEC decoder SDD, where M>L;

[0357] (5) If the number of bit errors in the P codewords at the second FEC decoder is less than N, the FEC decoder is enabled to be configured as SDD configuration 1 and the deinterleaver is enabled ( Figures 2A to 2E 、 Figure 2H to Figure 2N Configuration 2 of the first deinterleaver and / or the second deinterleaver shown in any one of , wherein N>M;

[0358] (6) Otherwise, enable configuration 1 of the second FEC decoder and enable the deinterleaver ( Figures 2A to 2E 、 Figure 2H to Figure 2N Configuration 1 of any one of the first deinterleaver and / or second deinterleaver shown in .

[0359] In some embodiments, the triggering condition of each adjustment method can be set with a number of occurrences, and the number of occurrences of each triggering condition can be the same or different. The adjustment is triggered only when the respective occurrence threshold is met.

[0360] Multi-condition switching between these adjustment modes can be achieved through a state machine. Adjustment mode switching can be performed automatically when communication is just established between the transmitter and receiver, or it can be switched during the communication process because the switching conditions are met. During the switching, the connection can be reset or the synchronization lock can be re-established, and then communication can be carried out according to the switched mode. Specifically, there are two switching modes: one is to switch from the default high error state to the low error state, and the other is to switch from the default low error state to the high error state. Switching from the default high error state to the low error state, that is, the system default configuration before communication is established is the high error state. If the actual channel error rate after communication is established meets the high error state, no switching is required; if the actual channel error rate is very low, the configuration will be switched. Switching from the default low error state to the high error state, that is, the system default configuration before communication is established is the low error state. If the actual channel error rate after communication is established meets the low error state, no switching is required; if the actual channel error rate is high, the configuration will be switched.

[0361] In the embodiment of the present application, "disabling" includes "turning off" or "bypassing", and "enabling" includes "enabling in hardware" or "enabling in software".

[0362] In some embodiments, "disabling the second FEC decoder" in the adjustment method can be (1) turning off the second FEC decoder, or (2) not decoding the data stream through the second FEC decoder but not turning off the second FEC decoder, that is, turning on SDD configuration 1, SDD configuration 2, or HDD of the second FEC decoder. "Disabling the second FEC decoder" means (1) turning off the second FEC decoder, which can effectively reduce transmission power consumption.

[0363] In some embodiments, the "disabling the deinterleaver" in the adjustment mode can be (1) turning off the deinterleaver, or (2) not processing the data stream through the deinterleaver, but not turning off the deinterleaver, that is, turning on the deinterleaver in configuration 1 or configuration 2. When the "disabling the deinterleaver" in the adjustment mode is (1) turning off the deinterleaver, the transmission power consumption can be effectively reduced.

[0364] The present invention also provides a method for processing Ethernet data streams. Figure 4This is a schematic diagram of the structure of a device for processing Ethernet data streams provided by an embodiment of the present application, based on Figure 4 The multiple modules shown, Figure 4 The device for processing Ethernet data stream shown is capable of performing the above Figure 3 It should be understood that the device may include more additional modules than those shown or omit some of the modules shown, and the embodiments of the present application are not limited thereto. Figure 4 The device is the receiving end device. Figure 4 As shown, the device includes an acquisition module 401 and an adjustment module 402, wherein: the acquisition module 401 is used to obtain transmission information of the first data stream; the adjustment module 402 is used to adjust the error correction capability of the receiving end device if the transmission information meets the trigger condition.

[0365] In some embodiments, the acquisition module 401 and the adjustment module 402 may be the same logic module or physical circuit, for example, located in the same chip.

[0366] In some embodiments, the transmission information includes one or more of the bit error rate BER, number of error bits, symbol error rate SER, number of error symbols, codeword error rate CER, number of error codewords, channel state information, and eye diagram parameters of the first data stream.

[0367] In some embodiments, the receiving end device further includes a first deinterleaver, and the transmission information satisfies a trigger condition, and adjusts the error correction capability of the receiving end device, including one or more of (1)-(6):

[0368] (1) If the number of bit errors in P codewords at the second FEC decoder is less than J, then disable the first deinterleaver and the second FEC decoder, where P and J are positive integers and P>J>1;

[0369] (2) If the number of bit errors in the P codewords at the second FEC decoder is less than K, the first deinterleaver is disabled and the hard decision decoding HDD of the second FEC decoder is enabled, where K is a positive integer and K>J;

[0370] (3) If the number of bit errors in the P codewords at the second FEC decoder is less than L, then the first deinterleaver is disabled and the soft decision decoding (SDD) of the second FEC decoder is enabled in configuration 2, where L is a positive integer and L>K;

[0371] (4) If the number of bit errors in the P codewords at the second FEC decoder is less than M, then disable the first deinterleaver and enable configuration 1 of the second FEC decoder SDD, where M>L;

[0372] (5) If the number of bit errors in the P codewords at the second FEC decoder is less than N, then enable the FEC decoder to be configured as SDD configuration 1 and enable configuration 2 of the first deinterleaver, where N>M;

[0373] (6) If none of (1) to (5) is satisfied, enable Configuration 1 of the second FEC decoder and enable Configuration 1 of the first deinterleaver.

[0374] In some embodiments, the transmission information satisfies a trigger condition to adjust the error correction capability of the receiving device, including any of the following:

[0375] (1) enabling configuration 1 of soft decision decoding (SDD) of the second FEC decoder;

[0376] (2) enabling configuration 2 of the SDD of the second FEC decoder;

[0377] (3) enabling hard decision decoding HDD of the second FEC decoder;

[0378] (4) Disable the second FEC decoder.

[0379] The error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 is higher than that of the HDD of the second FEC decoder.

[0380] In some embodiments, the receiving end device further includes a first deinterleaver, and the transmission information satisfies a trigger condition, and the error correction capability of the receiving end device is adjusted, including any one of the following:

[0381] (1) enabling configuration 1 of the soft decision decoding SDD of the second FEC decoder and enabling configuration 1 of the first deinterleaver;

[0382] (2) enabling configuration 1 of the SDD of the second FEC decoder and enabling configuration 2 of the first deinterleaver;

[0383] (3) enabling SDD configuration 1 of the second FEC decoder and disabling the first deinterleaver;

[0384] (4) enabling Configuration 2 of the SDD of the second FEC decoder and disabling the first deinterleaver;

[0385] (5) enabling the hard decision decoding HDD of the second FEC decoder and disabling the first deinterleaver;

[0386] (6) disabling the second FEC decoder and the first deinterleaver;

[0387] The deinterleaving delay and / or power consumption of configuration 1 of the first deinterleaver are higher than those of configuration 2 of the first deinterleaver; the error correction capability of configuration 1 of the SDD of the second FEC decoder is higher than that of configuration 2, and the error correction capability of configuration 2 is stronger than that of the HDD of the second FEC decoder.

[0388] In some embodiments, the receiving end device further includes a data position inverse converter, a first deinterleaver, and a second deinterleaver. The data position inverse converter is configured to perform an inverse transformation operation on the positions of the received data bits or symbols whose positions have been transformed by the data position converter. When the transmission information meets the triggering condition and adjusts the error correction capability of the receiving end device, it includes any one of the following:

[0389] (1) When the bit error rate BER of the data stream received by the receiving end device satisfies BER <= a, disable the data position inverse converter, the second FEC decoder, the first deinterleaver, and the second deinterleaver, where a > 0;

[0390] (2) When the BER of the data stream received by the receiving end device satisfies a < BER <= b, disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the hard decision decoding HDD of the second FEC decoder;

[0391] (3) When the BER of the data stream received by the receiving end device satisfies b < BER <= c, disable the data position inverse converter, the second deinterleaver, and the first deinterleaver, and enable the soft decision decoding SDD of the second FEC decoder;

[0392] (4) When the BER of the data stream received by the receiving end device satisfies c < BER <= d, disable the first deinterleaver and enable the soft decision decoding SDD of the second FEC decoder;

[0393] (5) When the BER of the data stream received by the receiving end device satisfies d < BER <= e, enable the soft decision decoding SDD of the second FEC decoder.

[0394] In some embodiments, the transmission information is related to the number of error units at the first FEC decoder and / or the second FEC decoder. The error unit includes a codeword, a bit, a symbol, or a bit group containing any number of bits.

[0395] In some embodiments, the transmission information includes information on how to adjust the error correction capability of the receiving end device.

[0396] In some embodiments, the information on how to adjust the error correction capability of the receiving device includes: disabling or weakening the error correction capability of the second FEC decoder.

[0397] In some embodiments, the receiving device also includes a deinterleaver, and the information on how to adjust the error correction capability of the receiving device includes: disabling or weakening the error correction capability of the second FEC decoder; and / or disabling or weakening the deinterleaving effect of the deinterleaver.

[0398] In some embodiments, the receiving device also includes a deinterleaver and a data position inverse transformer, and the information on how to adjust the error correction capability of the receiving device includes: disabling or weakening the error correction capability of the second FEC decoder; and / or, disabling or weakening the deinterleaving effect of the deinterleaver; and / or, disabling the function of the data position inverse transformer.

[0399] In some embodiments, the transmission information is located in a register of the transmitting device and / or the transmission information is triggered by a primitive.

[0400] like Figure 5 As shown, an embodiment of the present application further provides a device for processing Ethernet data streams, which is located in a sending end device. The device includes a configuration module, which is used to configure a data stream processing method of the sending end device based on a second indication.

[0401] In some embodiments, the instruction includes information on how to adjust the data stream processing method of the transmitting device. In some embodiments, the instruction includes disabling or reducing the error correction capability of the second FEC decoder.

[0402] In some embodiments, the transmitting end device further includes a first interleaver, and the instruction includes: disabling or weakening the error correction capability of the second FEC decoder; and / or disabling or weakening the interleaving effect of the first interleaver.

[0403] In some embodiments, the transmitting device also includes a first interleaver and a data position converter, and the indication includes disabling or weakening the error correction capability of the second FEC decoder; and / or disabling or weakening the interleaving effect of the first interleaver; and / or disabling the function of the data position converter.

[0404] In some embodiments, the indication comes from a receiving device corresponding to the sending device.

[0405] In some embodiments, the indication is in a register of the transmitting device and / or the indication is triggered by a primitive.

[0406] In some embodiments, Figure 4The device of and / or 5 is located in an Ethernet interface or a chip. In some embodiments, the Ethernet interface including the device is located in a computing device. The computing device can be a network device or a server, and the network device can be a routing device or a switching device.

[0407] like Figure 6 As shown, the embodiment of the present application further provides a computer system 600, which includes: a transceiver 601, a processor 602 and a memory 603. The transceiver 601, the processor 602 and the memory 603 are connected via a bus 604. Among them, the transceiver 601 is used to receive and send messages, the memory 603 is used to store instructions or program codes, and the processor 602 is used to call the instructions or program codes in the memory 603 so that the device executes the relevant processing steps of the first module or the second module in the above-mentioned method embodiment. In a specific embodiment, the computer system 600 of the embodiment of the present application may correspond to the first module or the second module in each of the above-mentioned method embodiments, and the processor 602 in the computer system 600 reads the instructions or program codes in the memory 603 so that Figure 6 The computer system 600 shown can execute all or part of the operations in the above-mentioned method embodiments executed by the receiving device and / or the sending device.

[0408] The computer system 600 may also correspond to the above Figure 4 or Figure 5 The device shown, for example, Figure 4 and Figure 5 The acquisition module 401 involved in the process is equivalent to the transceiver 601 , and the adjustment module 402 or the configuration module is equivalent to part or all of the functions in the processor 602 .

[0409] like Figure 7 As shown, a network system according to an embodiment of the present application includes a sending end device and a receiving end device, wherein the sending end device is Figure 5 or Figure 6 The device of the corresponding embodiment, the receiving end device is Figure 4 or Figure 6 The device of the corresponding embodiment.

[0410] In some embodiments, the processor or chip may be a central processing unit (CPU), or other general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports the Advanced RISC Machine (ARM) architecture.

[0411] In an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store device type information.

[0412] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0413] In some embodiments, the computer system 700 may be a network device or a server. For example, the network device may be a routing device or a switching device.

[0414] An embodiment of the present application also provides a computer-readable storage medium, in which at least one program instruction or code is stored. The program instruction or code is executed by a computer to obtain and send the status information, control information described in embodiment one or two separately, or send the status information and the control information together.

[0415] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0416] To clearly illustrate the interchangeability of hardware and software, the above description has generally described the steps and components of each embodiment according to their functions. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0417] The computer program code for implementing the method of the embodiment of the application can be written in one or more programming languages. These computer program codes can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable alignment mark search device, so that when the program code is executed by the computer or other programmable alignment mark search device, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer, or entirely on a remote computer or server.

[0418] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0419] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0420] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0421] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0422] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0423] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first module can be referred to as a second module, and similarly, a second module can be referred to as a first module.

[0424] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0425] As used herein, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of code blocks" means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0426] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0427] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0428] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining…” or “in response to determining…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0429] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0430] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A communication method, characterized in that: Applied to a receiving device, the receiving device includes a second forward error correction (FEC) decoder, the second FEC decoder is an inner code decoder of a concatenated code, the outer code decoder of the concatenated code is a first FEC decoder, the second FEC decoder and the first FEC decoder are used to sequentially perform inner code decoding and outer code decoding on a data stream encoded by the concatenated code, the method comprising: Adjust the error correction capability of the second FEC decoder.

2. The method according to claim 1, characterized in that The adjusting the error correction capability of the second FEC decoder includes: Disabling the second FEC decoder, disabling the error correction capability of the second FEC decoder, or weakening the error correction capability of the second FEC decoder.

3. The method according to claim 2, characterized in that The disabling the second FEC decoder includes: Bypass or disable the second FEC decoder.

4. The method according to any one of claims 1 to 3, characterized in that The receiving end device further includes the first FEC decoder.

5. The method according to any one of claims 1 to 4, characterized in that The adjusting the error correction capability of the second FEC decoder includes: adjusting the error correction capability of the second FEC decoder according to the instruction.

6. The method according to claim 5, characterized in that The adjusting the error correction capability of the second FEC decoder according to the instruction includes: adjusting the error correction capability of the second FEC decoder according to an instruction triggered manually.

7. The method according to claim 5 or 6, characterized in that The indication is located in a register and / or is triggered by a primitive.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: receiving a first data stream sent by a transmitting end device; Adjust the error correction capability of the second FEC decoder according to the transmission information of the first data stream.

9. The method according to claim 8, characterized in that The transmission information includes one or more of a bit error rate BER, a number of error bits, a symbol error rate SER, a number of error symbols, a codeword error rate CER, a number of error codewords, channel state information, or an eye diagram parameter of the first data stream.

10. The method according to claim 8 or 9, characterized in that The method further includes: if the transmission information meets a trigger condition, adjusting the error correction capability of the second FEC decoder.

11. The method according to any one of claims 8 to 10, characterized in that: The transmission information includes information on how to adjust the error correction capability of the receiving device.

12. The method according to any one of claims 1 to 11, characterized in that The receiving end device further includes a deinterleaver, and the deinterleaver is located between the second FEC decoder and the first FEC decoder on the transmission path of the data stream. The method further includes: The error correction capability of the deinterleaver is adjusted.

13. The method according to claim 12, characterized in that The adjusting the error correction capability of the deinterleaver includes: The deinterleaver is disabled or the deinterleaving effect of the deinterleaver is weakened.

14. The method according to claim 13, characterized in that The disabling of the deinterleaving includes: The deinterleaver is bypassed or turned off.

15. The method according to any one of claims 12 to 14, characterized in that: The deinterleaver is a convolutional deinterleaver.

16. The method according to any one of claims 12 to 15, characterized in that: The adjusting the error correction capability of the deinterleaver includes: adjusting the error correction capability of the deinterleaver according to an instruction.

17. The method according to claim 16, characterized in that The adjusting the error correction capability of the deinterleaver according to the instruction includes: adjusting the error correction capability of the deinterleaver according to an instruction triggered manually.

18. The method according to claim 16 or 17, characterized in that The indication is located in a register and / or is triggered by a primitive.

19. The method according to any one of claims 1 to 18, characterized in that The receiving end device further includes a data position inverse transformer, and the method further includes: disabling the data position inverse transformer.

20. A communication method, characterized in that: The method is applied to a transmitting end device, the transmitting end device including a first forward error correction (FEC) encoder and a second FEC encoder, the first FEC encoder being an outer code encoder of a concatenated code, the second FEC encoder being an inner code encoder of the concatenated code, the first FEC encoder and the second FEC encoder being used to sequentially perform outer code encoding and inner code encoding on a data stream, and comprising: Disable the second FEC encoder or reduce the capability of the second FEC encoder.

21. The method according to claim 20, characterized in that The disabling the second FEC encoder includes: bypassing or shutting down the second FEC encoder.

22. The method according to claim 20 or 21, characterized in that The disabling of the second FEC encoder or reducing the capability of the second FEC encoder includes: disabling the second FEC encoder or reducing the capability of the second FEC encoder according to an instruction.

23. The method according to claim 22, characterized in that The instruction comes from the receiving device corresponding to the sending device.

24. The method according to claim 22 or 23, characterized in that The indication is in a register of the transmitting end device and / or the indication is triggered by a primitive.

25. The method according to any one of claims 20 to 24, characterized in that The transmitting end device further includes an interleaver, and in a transmission direction of the data stream, the interleaver is located between the first FEC encoder and the second FEC encoder. The method includes: Disable the interleaver or weaken the interleaving effect of the interleaver.

26. The method according to claim 25, characterized in that The disabling of the interleaver includes bypassing or shutting down the interleaver.

27. The method according to claim 25 or 26, characterized in that The interleaver is a convolutional interleaver.

28. The method according to any one of claims 25 to 27, characterized in that The disabling of the interleaver or weakening the interleaving effect of the interleaver includes: disabling the interleaver or weakening the interleaving effect of the interleaver according to an instruction.

29. The method according to claim 28, characterized in that The instruction comes from the receiving device corresponding to the sending device.

30. The method according to claim 28 or 29, characterized in that The indication is in a register of the transmitting end device and / or the indication is triggered by a primitive.

31. The method according to any one of claims 20 to 30, characterized in that The transmitting end device further includes a data position converter, and the method further includes: disabling the data position converter.

32. A receiving device, characterized in that: It includes a second forward error correction (FEC) decoder, the second FEC decoder is an inner code decoder of the concatenated code, the outer code decoder of the concatenated code is a first FEC decoder, the second FEC decoder and the first FEC decoder are used to successively perform inner code decoding and outer code decoding on the data stream encoded by the concatenated code, and the receiving end device is used to implement the method described in any one of claims 1 to 19.

33. A transmitting end device, characterized in that: It includes a first forward error correction (FEC) encoder and a second FEC encoder, the first FEC encoder is an outer code encoder of a concatenated code, the second FEC encoder is an inner code encoder of the concatenated code, the first FEC encoder and the second FEC encoder are used to perform outer code encoding and inner code encoding on the data stream in sequence, and the sending end device is used to implement the method described in any one of claims 20-31.

34. A receiving device, characterized in that: Includes the receiving end device described in claim 32.

35. A transmitting end device, characterized in that: Includes the sending end device as described in claim 32.

36. A communication system comprising the receiving device according to claim 32 and the transmitting device according to claim 33.

37. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed by a processor, the method according to any one of claims 1 to 31 is implemented.

38. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 31 is implemented.

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