SST driving structure of multi-pulse amplitude modulation signal and front flow system thereof

Abstract

The invention provides a multi-pulse amplitude modulation signal SST driving structure and a pre-process system thereof, the SST driving structure is constructed based on an n-bit DAC module and comprises 2n-1 standard units, all the standard units are divided into n groups, and the number of the standard units in the kth group is 2k-1; wherein n and k are integers, n > = 2, and k < = n; furthermore, the first group is defined as an LSB group, and the nth group is defined as an MSB group; wherein M standard units are divided from the MSB group and are used for resistor correction; wherein M is an integer, and M is less than or equal to 2n-1. According to the invention, the problems that the linearity of the circuit is easily influenced and the output SST swing can be reduced when the resistor is corrected in the existing scheme can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interfaces, and more particularly to an SST driving structure of a multi-pulse amplitude modulation signal and a pre-process system thereof. Background Art

[0002] PAM4 (Pulse Amplitude Modulation 4) signals are currently widely used in high-speed interfaces such as PCIe (a high-speed serial computer expansion bus standard) and Ethernet. The industry is trending towards PAM8 and PAM16 to further improve data throughput. For PAM4 and higher modulation levels, the widely used DAC (digital-to-analog converter)-based SST (source-series-drive) driver stage structure is a common choice for TX (transmitter) driver modules.

[0003] Figure 1 The figure shows a common single-ended output driver stage structure, consisting of n groups of standard cells. The first group of standard cells is defined as the LSB (least significant bit), and the nth group is defined as the MSB (most significant bit). High-speed signal protocols typically require impedance matching of 50 ohms for single-ended transmission and 100 ohms for differential transmission. Therefore, the SST structure also requires calibration based on process variations to meet protocol requirements for reflection coefficient.

[0004] There are two general solutions: The first solution is to adjust the resistance value within a single standard unit to achieve the target resistance value for the entire parallel connection. The second solution is to place some redundant static resistor units on the dynamic SST module, such as Figure 2 shown.

[0005] Of the two conventional solutions mentioned above, the first requires resistance adjustment within the standard cell, which complicates the standard cell of the TX driver stage and limits the bandwidth of the high-speed circuit. In terms of the implementation of resistance adjustment itself, if the on-resistance of the switch tube is used as the adjustment method, it will affect the linearity of the circuit. The second solution, due to the additional static resistor, can achieve resistance matching correction, but it does not provide drive capability and will reduce the output SST swing.

[0006] Based on the above technical problems, there is an urgent need for an SST structure correction solution that will neither affect the linearity of the circuit nor reduce the output SST swing. Summary of the Invention

[0007] In view of the above problems, the purpose of the present invention is to provide an SST driving structure with multiple pulse amplitude modulation signals and its front-end process system to solve the problem that the existing solution easily affects the linearity of the circuit when correcting the resistance and reduces the output SST swing.

[0008] The SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention includes 2 n -1 standard unit, all standard units are divided into n groups, and the number of standard units in the kth group is 2 k-1 ; Where n and k are integers, n≥2, k≤n; and the first group is defined as the LSB group, and the nth group is defined as the MSB group; wherein M standard cells are divided into the MSB group for resistance correction; wherein M is an integer, M≤2 n-1 .

[0009] In addition, an optional solution is to select m standard cells from the M standard cells divided in the MSB group and perform high resistance conversion when correcting the resistance.

[0010] In addition, an optional solution is that the multi-pulse amplitude modulation signal is a PAM4 signal.

[0011] In addition, an optional solution is that the SST driving structure of the multi-pulse amplitude modulation signal is constructed based on an n-bit DAC module.

[0012] On the other hand, the present invention also provides a front-end process system for the SST drive structure of the aforementioned multi-pulse amplitude modulation signal, including a signal input module, a digital logic module, and a remapping module; wherein, The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The digital logic module is used to process the set value of the PAM4 signal; The remapping module is used to remap the signal generated by the digital logic module, and the remapped signal serves as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal.

[0013] In addition, an optional solution is that the data processing flow formula of the digital logic module is: b'100…00+(1 / 3)S'PAM4; where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, and S is the single-ended swing of the PAM4 signal. S'=S (2 n -1-m) / (2 n -1); where m is an integer, m≤M.

[0014] On the other hand, the present invention also provides another front-end process system of an SST driving structure of a plurality of pulse amplitude modulation signals, comprising a signal input module and a new digital logic module; wherein, The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The novel digital logic module is used to process the set value of the PAM4 signal; The signal generated by the novel digital logic module is directly used as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal.

[0015] In addition, an optional solution is that when the four set values ​​of the PAM4 signal are centered at 0, the data processing flow formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4) m / 2; where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S is the single-ended swing of the PAM4 signal, and S'=S (2 n -1-m) / (2 n -1); where m is an integer, m≤M, and sgn(PAM4) is the sign of the corresponding set value of the PAM4 signal.

[0016] In addition, an optional solution is that when the four set values ​​of the PAM4 signal do not have 0 as the median value, the data processing flow formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4-Q) m / 2; where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, and S'=S (2 n -1-m) / (2 n -1), S is the single-ended swing of the PAM4 signal; where m is an integer, m≤M, Q is the median of the four set values ​​of the PAM4 signal, and sgn(PAM4-Q) is the sign of the result after subtracting the corresponding set value of the PAM4 signal from Q.

[0017] Compared with the prior art, the SST drive structure based on the multi-pulse amplitude modulation signal and its pre-process system have the following beneficial effects: By designing a resistance adjustment scheme for the SST drive structure of a multi-pulse amplitude modulation signal, the resistance can be corrected without affecting the linearity of the circuit and without reducing the output SST swing amplitude. In addition, the information digital logic module in the front-end process system provided by the present invention can eliminate the need to remap the module settings by optimizing the data processing process formula, further reducing the logic overhead of the entire circuit and further reducing signal delay.

[0018] To achieve the above and related ends, one or more aspects of the present invention include specific features that will be described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings set forth certain exemplary aspects of the present invention in detail. However, these aspects are merely indicative of the various ways in which the principles of the present invention may be employed. Furthermore, the present invention is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By referring to the following description and claims in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more apparent and readily understood. In the accompanying drawings: Figure 1 A schematic diagram of a single-ended structure of an SST driving structure for a multi-pulse amplitude modulation signal according to an embodiment of the present invention; Figure 2 This is a grouping diagram of standard cells in the SST drive structure in the existing second solution; Figure 3 A diagram showing the grouping of standard cells in an SST driving structure of a multi-pulse amplitude modulation signal according to an embodiment of the present invention; Figure 4 An eye diagram of a PAM4 signal according to an embodiment of the present invention; Figure 5 A logic diagram of a front-end process system corresponding to an SST driving structure of a pulse amplitude modulation signal provided by an embodiment of the present invention when the resistance is not corrected; Figure 6 A logic diagram of a first pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by an embodiment of the present invention when correcting resistance; Figure 7 A mapping relationship diagram of a remapping module in a first front-end process system corresponding to the SST driving structure of a pulse amplitude modulation signal provided by an embodiment of the present invention when correcting resistance; Figure 8 A logic diagram of a second front-end process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by an embodiment of the present invention when correcting the resistance, when the four set values ​​of the PAM4 signal are 0 as the median value; Figure 9 This is a logic diagram of a second front-end process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by an embodiment of the present invention when correcting the resistance when the four set values ​​of the PAM4 signal do not take 0 as the median value. DETAILED DESCRIPTION

[0020] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0021] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention; the terms "first", "second", and "third" are only used for descriptive purposes and should not be understood as indicating or implying relative importance; in addition, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or it can be internal communication between two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Figure 1 A schematic diagram of a single-ended structure of an SST driving structure for a multi-pulse amplitude modulation signal according to an embodiment of the present invention is shown (same as the single-ended structure of a common output driver stage mentioned in the background art). Figure 3 The grouping of standard cells in the SST driving structure of the multi-pulse amplitude modulation signal provided by the embodiment of the present invention is shown. Figure 1 and Figure 3 It can be seen that the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention is constructed based on an n-bit DAC module; the SST driving structure of the multi-pulse amplitude modulation signal includes 2 n -1 standard cell, where all standard cells are divided into n groups, and the number of standard cells in group k is 2 k-1; Among them, n and k are integers, n is a fixed parameter, n≥2; k is a dynamic parameter, the minimum value of k is 0, and the maximum value of k is n; that is, all standard units are in the order of 1+2+4+8+…+2 n-1 =2 n -1) are grouped, and the nth group is defined as the MSB group (corresponding to MSB), and the first group is defined as the LSB group (corresponding to LSB); in the actual operation process, in order to facilitate the resistance correction of the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention, in the MSB group (including 2 n-1 standard units) to divide part or all of the standard units (defined as M standard units, M is an integer, M≤2 n-1 ), used for resistance correction; thereby achieving resistance correction for the SST drive structure of multiple pulse amplitude modulation signals. It should be noted that among the n groups, at least one LSB group and one MSB group must exist. Therefore, the minimum value of n is 2.

[0023] In a specific embodiment of the present invention, when the resistance of the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention is corrected, m standard cells can be selected from the M standard cells divided in the MSB group for high resistance. The specific operation is: in the corresponding m standard cells selected, the upper and lower switches are forced to lock the disconnected state, thereby high-resistance m standard cells are removed. At this time, the number of effective standard cells is 2 n -1-m pieces.

[0024] It should be noted that the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention is applicable to all types of existing multi-pulse amplitude modulation signals. In actual use, the multi-pulse amplitude modulation signal preferably uses the PAM4 signal. For the PAM4 signal, Figure 4 The eye diagram of the PAM4 signal provided according to an embodiment of the present invention is shown. Figure 4 It can be seen that Figure 4 The PAM4 signal in the scheme is typically centered around DAC code 100..00 (i.e., b'100…00), with symmetrical increments of + / - 1 S standard cells or + / - (1 / 3) S standard cells in the up and down directions to achieve the four PAM4 voltage levels. S is the single-ended swing configured by the designer using programmable methods.

[0025] Specifically, Figure 5 FIG1 shows a logic diagram of a front-end process system corresponding to an SST driving structure of a pulse amplitude modulation signal provided by an embodiment of the present invention when the resistance is not corrected; ... Figure 5It can be seen that after the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention modifies the resistance, the logic diagram of the corresponding front-end process system cannot maintain the consistency of the PAM4 signal amplitude and linearity when the resistance is not corrected. To solve this technical problem, it is necessary to adjust the logic of the front-end process system, that is, Figure 6 The logic diagram of the first pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by the embodiment of the present invention when correcting the resistance is shown. Figure 6 It can be seen that the present invention provides a front-end process system for the SST driving structure of the aforementioned multiple pulse amplitude modulation signals, the system including a signal input module, a digital logic module, and a remapping module; wherein the signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; the digital logic module is used to process the configured set value of the PAM4 signal, and the remapping module is used to remap the signal generated by the digital logic module, and the remapped signal serves as the input signal of the SST driving structure of the multiple pulse amplitude modulation signals; wherein the data processing flow formula of the digital logic module is: b'100…00+(1 / 3)S'(PAM4); where b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal (e.g. Figure 5 As shown, the setting value of the AM4 signal can be set based on the initial binary voltage signal. For example, the four initial binary voltage signals are 00, 01, 10, and 11 respectively, and the corresponding four setting values ​​of the PAM4 signal can be set to (-3, -1, 1, and 3) respectively. S is the single-ended swing of the PAM4 signal, and S'=S (2 n -1-m) / (2 n -1), where m is an integer, m≤M.

[0026] From the above, we can see that compared with the corresponding front-end process system without resistance correction, the coefficient S is modified to S'=S (2 n -1-m) / (2 n -1), this operation is static logic and does not affect the system latency (signal delay). In addition, since the MSB (most significant bit) of the final DAC is no longer the standard 2 n-1 Therefore, the standard binary DAC signal sent by the digital logic module must be remapped to reflect the non-binary MSB.

[0027] Figure 7The mapping relationship diagram (example diagram) of the remapping module in the first pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by the embodiment of the present invention when correcting the resistance is shown. Figure 7 As shown, taking an 8-bit (n=8) DAC as an example, Figure 7 The left side of the diagram shows standard binary digital logic. The input logic is the binary number [D7 D6 D5D4 D3 D2 D1 D0], and the output is [D7' D6' D5' D4' D3' D2' D1' D0]. The mapping process, implemented using a classic digital scheme, is: divide the sum by 90 to get D7', divide the remainder by 64 to get D6', divide the remainder by 32 to get D5', and so on to get D0'. This method is logically correct, but it carries significant logic overhead, especially for high-speed signal links. It is therefore very cost-effective in signal systems with transmission delay requirements.

[0028] It should be noted here that, for the first pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by the above-mentioned embodiment of the present invention when correcting the resistance, after research, it is found that there are still some disadvantages. For example, due to the newly added corresponding remapping module, the logic overhead based on the remapping module will inevitably increase; and due to the existence of the remapping module, a remapping process will inevitably be introduced. Due to the existence of this remapping process, a certain latency will inevitably be added to the high-speed signal link.

[0029] In order to solve the above-mentioned drawbacks of the first pre-process system provided by the present invention, the present invention has designed another pre-process system. Figure 8 This is a logic diagram of the second pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided by the embodiment of the present invention when correcting the resistance, which is composed of Figure 8 It can be seen that the present invention also provides another front-end process system applied to the aforementioned SST driving structure of multiple pulse amplitude modulation signals; the system includes a signal input module and a new digital logic module; wherein the signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; the new digital logic module is used to process the set value of the PAM4 signal; the signal generated by the new digital logic module is directly used as the input signal of the SST driving structure of the multiple pulse amplitude modulation signals.

[0030] Furthermore, typically, the four set values ​​of the PAM4 signal are preferably four arrays with 0 as the median value (for example, set to -3, -1, 1, and 3, respectively). In this case, the data processing flow formula of the novel digital logic module can be set as: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4) m / 2; where b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal (e.g. Figure 5 As shown in the figure, the setting value of the AM4 signal can be set based on the initial binary voltage signal. For example, the four initial binary voltage signals are 00, 01, 10, and 11 respectively, and the corresponding four setting values ​​of the PAM4 signal can be set to -3, -1, 1, and 3 respectively. S is the single-ended swing of the PAM4 signal, and S'=S (2 n -1-m) / (2 n -1); where m is an integer, m≤M; sgn(PAM4) is used to obtain the sign of the set value of each PAM4 signal. For example, when the set value of a PAM4 signal is -3, the data processing flow formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4-m / 2; when the set value of a PAM4 signal is 3, the data processing flow formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4+m / 2.

[0031] It should be noted that, for the four set values ​​of the PAM4 signal, under normal circumstances, it is preferred to set them to two groups of positive and negative numbers with 0 as the median. For example, the preferred set values ​​are 3, -1, 1, and 3 in sequence. However, in some special cases, the set values ​​of the PAM4 signal do not have 0 as the median (for example, the set values ​​are 0, 1, 2, and 3 in sequence). In this case, it is necessary to first find the median of the set values ​​and record it as Q. Then, sgn(PAM4-Q) is used to determine the positive and negative of each PAM4 set value. For example, if the set values ​​of the PAM4 signal are 0, 1, 2, and 3 in sequence, then the median of Q is 1.5. In this case, sgn(PAM4-1.5) is used to determine the positive and negative of each PAM4 set value. The data processing flow formula of the entire new digital logic module is optimized and changed to: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4-Q) m / 2, where Q=1.5.

[0032] It should be noted that the calculation of the median value of a set of PAM4 signal setting values ​​can be done by directly taking the middle value between the maximum and minimum values ​​in the reorganized setting values.

[0033] It can be seen that based on the first solution provided by the present invention, no remapping method is used, but the PAM4 signal is directly "same" in the digital logic module, + sgn(PAM4) A correction parameter of m / 2 can achieve the non-standard MSB remapping requirement. Clearly, compared to the first solution, the second solution provided by the present invention can eliminate the need for a remapping module, effectively reducing not only the logic overhead of the entire circuit but also the latency of the entire high-speed signal link.

[0034] It should be noted that, to further illustrate that the second solution provided by the present invention, although simple in design logic, can still achieve substantially the same effect as the original solution without the need for resistance correction, the following derivation and verification is performed using the case where a certain PAM4 signal input is positive.

[0035] Assuming that the target swing of a PAM4 signal is L, then for the original solution without resistor correction, the corresponding resolution is L / (2 n -1), the corresponding data processing formula (i.e., code) of the original solution is: b'100…00+(1 / 3)S(PAM4), where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, and S is the single-ended swing of the PAM4 signal. At this time, it can be calculated that in the original solution, the DAC output is: (2 n-1 + ) L / (2 n -1).

[0036] Assuming that the target swing of a PAM4 signal is L, then for the second solution provided by the present invention, the corresponding resolution is L / (2 n -1-m), the corresponding data processing formula (i.e., code) of the second solution provided by the present invention is: b'100…00+(1 / 3)S'PAM4+m / 2 (can also be set to b'100…00+(1 / 3)S'PAM4-m / 2); where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S is the single-ended swing of the PAM4 signal, and S'=S (2 n -1-m) / (2 n -1); where m is an integer, m≤M; in this case, the highest bit in b'10…00 is 2 n-1 -m; In the second solution provided by the present invention, the derivation formula of the DAC output is as follows: (2 n-1 -m + + ) L / (2 n -1-m) = [2 n-1 - + (2 n -1-m) / (2 n -1) ] L / (2 n -1-m) = [(2 n-1 - ) ( 2 n -1) + (2 n -1-m)] L / (2 n -1-m) / (2 n -1) = [(2 n - ( 2 n -1) / 2 / (2 n -1-m) + ] L / (2 n -1) Due to 2 n - >>1, therefore (2 n - / (2 n -1-m) = 1; and because 2 n >>1, Therefore, the DAC output in the second solution provided by the present invention is: (2 n-1 + ) * L / (2 n -1).

[0037] In summary, the DAC output (voltage) in the second solution provided by the present invention is consistent with the output (voltage) of the original solution. Therefore, although the second solution provided by the present invention has a simple design logic, it can still achieve basically the same effect as the original solution without the need for resistance correction.

[0038] Compared with the prior art, the SST drive structure based on the multi-pulse amplitude modulation signal and its pre-process system have the following beneficial effects: By designing a resistance adjustment scheme for the SST drive structure of a multi-pulse amplitude modulation signal, the resistance can be corrected without affecting the linearity of the circuit and without reducing the output SST swing amplitude. In addition, the information digital logic module in the front-end process system provided by the present invention can eliminate the need to remap the module settings by optimizing the data processing flow formula, further reducing the logic overhead of the entire circuit and further reducing signal latency.

[0039] As above Figures 1 to 9 The SST drive structure for multiple pulse amplitude modulation signals and its pre-process system according to the present invention are described by way of example. However, those skilled in the art will appreciate that various improvements may be made to the SST drive structure for multiple pulse amplitude modulation signals and its pre-process system without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A multi-pulse amplitude modulation signal SST driving structure; characterized in that, Includes 2 n -1 standard cell, where all standard cells are divided into n groups, and the number of standard cells in group k is 2 k-1 ; Where n and k are integers, n≥2, k≤n; and the first group is defined as the LSB group, and the nth group is defined as the MSB group; wherein M standard cells are divided into the MSB group for resistance correction; wherein M is an integer, M≤2 n-1 .

2. The SST driving structure of multiple pulse amplitude modulation signals according to claim 1, characterized in that: When modifying the resistance, m standard cells are selected from the M standard cells divided in the MSB group and are converted to high resistance.

3. The SST driving structure of multiple pulse amplitude modulation signals according to claim 2, characterized in that: The multi-pulse amplitude modulation signal is a PAM4 signal.

4. The SST driving structure of multiple pulse amplitude modulation signals according to claim 3, characterized in that: The SST driving structure of the multi-pulse amplitude modulation signal is constructed based on an n-bit DAC module.

5. A front-end process system for an SST drive structure of a multi-pulse amplitude modulation signal according to any one of claims 1 to 4, characterized in that: It includes signal input module, digital logic module and remapping module; among them, The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The digital logic module is used to process the set value of the PAM4 signal; The remapping module is used to remap the signal generated by the digital logic module, and the remapped signal serves as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal.

6. The front-end process system of the SST driving structure of multiple pulse amplitude modulation signals as claimed in claim 5, characterized in that: The data processing flow formula of the digital logic module is: b'100…00+(1 / 3)S'PAM4; where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S'=S (2 n -1-m) / (2 n -1), S is the single-ended swing of the PAM4 signal; where m is an integer, m≤M.

7. A front-end process system for an SST drive structure of a multi-pulse amplitude modulation signal according to any one of claims 1 to 4, characterized in that: Including signal input module and new digital logic module; among them, The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The novel digital logic module is used to process the set value of the PAM4 signal; The signal generated by the novel digital logic module is directly used as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal.

8. The front-end process system of the SST driving structure of multiple pulse amplitude modulation signals as claimed in claim 7, characterized in that: When the four set values ​​of the PAM4 signal are centered at 0, the data processing flow formula of the novel digital logic module is: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4) m / 2; where b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal. S'=S (2 n -1-m) / (2 n -1), S is the single-ended swing of the PAM4 signal; where m is an integer, m≤M.

9. The front-end process system of the SST driving structure of multiple pulse amplitude modulation signals as claimed in claim 7, characterized in that: When the four set values ​​of the PAM4 signal do not have 0 as the median value, the data processing flow formula of the novel digital logic module is: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4-Q) m / 2; where b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal. S'=S (2 n -1-m) / (2 n -1), S is the single-ended swing of the PAM4 signal; where m is an integer, m≤M, and Q is the median of the four set values ​​of the PAM4 signal.

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