SST driving structure of multi-pulse amplitude modulation signal and pre-process system thereof

Abstract

The application provides an SST driving structure of a multi-pulse amplitude modulation signal and a pre-process system thereof. n -1 standard unit, wherein all the standard units are divided into n groups, the number of standard units in the kth group is 2 k‑1 ; wherein n and k are integers, n>=2, and k<=n; and the first group is defined as an LSB group, and the nth group is defined as an MSB group; wherein M standard units in the MSB group are divided for resistance correction; wherein M is an integer, and M<=2 n‑1 The application can effectively solve the problem that the existing scheme is easy to affect the linearity of the circuit when correcting the resistance and reduce the output SST swing.

Description

Technical Field

[0001] This invention relates to the field of high-speed interface technology, and more specifically, to an SST driving structure for multi-pulse amplitude modulation signals and its pre-processing system. Background Technology

[0002] PAM4 (4-pulse amplitude modulation) signals are currently widely used in high-speed interfaces, such as PCIe (a high-speed serial computer expansion bus standard) and Ethernet. The industry is also trending towards PAM8 and PAM16 to further improve data throughput. For PAM4 and higher modulation level TX (transmit) driver modules, the widely used DAC (digital-to-analog converter) type, SST (source-in-series driver) based driver stage structure is already a common choice.

[0003] Figure 1 This diagram illustrates a typical single-ended output driver stage structure, comprising n sets of standard cells. The first set of standard cells is defined as the LSB (Least Significant Bit) group, and the nth set is defined as the MSB (Most Significant Bit) group. In high-speed signal protocols, impedance matching is typically required to be 50 ohms for single-ended and 100 ohms for differential. Therefore, the SST structure also needs to be calibrated according to process variations to meet protocol requirements for reflection coefficient.

[0004] There are two common solutions:

[0005] The first approach is to adjust the resistance value within a single standard unit to achieve the target resistance value for the overall parallel connection.

[0006] The second approach is to add some redundant static resistor units to the dynamic SST module, such as... Figure 2 As shown.

[0007] Regarding the two conventional solutions mentioned above, the first solution, due to the need for resistor adjustment within the standard cell, complicates the standard cell of the TX driver stage and limits the bandwidth of the high-speed circuit. Furthermore, if the on-resistance of the switching transistor is used as the adjustment method, it will affect the linearity of the circuit. The second solution, due to the additional static resistor, can achieve resistor matching correction, but it does not provide driving capability itself, thus reducing the output SST swing.

[0008] Based on the above technical problems, there is an urgent need for an SST structure correction scheme that will not affect the linearity of the circuit or reduce the output SST swing. Summary of the Invention

[0009] In view of the above problems, the purpose of this invention is to provide a SST driving structure for multi-pulse amplitude modulation signals and its pre-processing system, so as to solve the problems that existing solutions easily affect the linearity of the circuit when correcting the resistor, and reduce the output SST swing.

[0010] The SST driving structure for multi-pulse amplitude modulation signals provided by this invention includes 2 n -1 standard unit, all standard units are divided into n groups, and the number of standard units in the kth group is 2. k-1 Where n and k are integers, n≥2, k≤n; and the first group is defined as the LSB group, the nth group is defined as the MSB group; M standard units are divided in the MSB group for resistance correction; where M is an integer, M≤2 n-1 .

[0011] Alternatively, when correcting the resistance, m standard cells out of the M standard cells divided in the MSB group are selected and made high-resistance.

[0012] Alternatively, the multi-pulse amplitude modulation signal can be a PAM4 signal.

[0013] Alternatively, the SST driving structure of the multi-pulse amplitude modulation signal can be constructed based on an n-bit DAC module.

[0014] On the other hand, the present invention also provides a pre-process system for the aforementioned SST driving structure of multi-pulse amplitude modulation signals, including a signal input module, a digital logic module, and a remapping module; wherein,

[0015] The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal;

[0016] The digital logic module is used to process the set value of the PAM4 signal;

[0017] The remapping module is used to remap the signal generated by the digital logic module, and the remapped signal is used as the input signal of the SST drive structure of the multi-pulse amplitude modulation signal.

[0018] Alternatively, the data processing flow formula for the digital logic module is as follows:

[0019] b'100…00+(1 / 3)S'PAM4; where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, and S is the single-end swing of the PAM4 signal.

[0020] S'=S*(2n -1-m) / (2 n -1); where m is an integer, m≤M.

[0021] Furthermore, this invention also provides a pre-processing system for an SST driving structure of a multi-pulse amplitude modulation signal, comprising a signal input module and a novel digital logic module; wherein,

[0022] The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal;

[0023] The novel digital logic module is used to process the set value of the PAM4 signal;

[0024] The signal generated by the novel digital logic module is directly used as the input signal of the SST drive structure of the multi-pulse amplitude modulation signal.

[0025] Alternatively, when the four set values ​​of the PAM4 signal have 0 as the median, the data processing formula of the novel digital logic module is as follows:

[0026] b'100…00+(1 / 3)S'PAM4+ sgn(PAM4)*m / 2;where, b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S is the single-end swing of the PAM4 signal, and S'=S*(2 n -1-m) / (2 n -1); where m is an integer, m≤M, and sgn(PAM4) is the sign of the corresponding set value of the PAM4 signal.

[0027] Alternatively, when the four set values ​​of the PAM4 signal do not have 0 as the median, the data processing formula of the novel digital logic module is as follows:

[0028] b'100…00+(1 / 3)S'PAM4+ sgn(PAM4-Q)*m / 2;where, b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S'=S*(2 n -1-m) / (2 n -1), S is the single-ended swing of the PAM4 signal; where m is an integer, m≤M, Q is the median of the four set values ​​of the PAM4 signal, and sgn(PAM4-Q) is the result of subtracting Q from the corresponding set value of the PAM4 signal and taking the sign.

[0029] Compared with existing technologies, the above-mentioned SST driving structure based on multi-pulse amplitude modulation signals and its pre-processing system have the following advantages:

[0030] By designing a resistor adjustment scheme for the SST drive structure of multi-pulse amplitude modulation signal, the linearity of the circuit can be maintained without affecting the circuit when correcting the resistor, and the output SST swing will not be reduced. In addition, the information digital logic module in the front-end process system provided by this invention can eliminate the setting of the remapping module by optimizing the data processing flow formula, further reducing the logic overhead of the entire circuit and further reducing signal delay.

[0031] To achieve the foregoing and related objectives, one or more aspects of the invention include the specific features which will be described in detail below and particularly pointed out. Certain exemplary aspects of the invention are described in detail below with reference to the accompanying drawings. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0032] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings:

[0033] Figure 1 This is a schematic diagram of a single-ended structure of an SST driving structure for a multi-pulse amplitude modulation signal provided in an embodiment of the present invention.

[0034] Figure 2 This is a grouping diagram of the standard cells in the SST drive structure of the existing second scheme;

[0035] Figure 3 This is a grouping diagram of standard cells in the SST driving structure for a multi-pulse amplitude modulation signal provided according to an embodiment of the present invention;

[0036] Figure 4 An eye diagram of a PAM4 signal provided according to an embodiment of the present invention;

[0037] Figure 5 The logic diagram of the pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when the resistor is not corrected;

[0038] Figure 6 The logic diagram of the first type of pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when correcting the resistor;

[0039] Figure 7 This is a mapping diagram of the remapping module in the first type of preprocessing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when correcting the resistor.

[0040] Figure 8 The logic diagram of the second type of pre-processing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when the resistor is corrected is 0 when the four set values ​​of the PAM4 signal are 0.

[0041] Figure 9 The logic diagram of the second type of pre-processing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when the resistor is corrected is not 0 among the four set values ​​of the PAM4 signal. Detailed Implementation

[0042] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0043] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0044] Figure 1 A schematic diagram of a single-ended structure of an SST driving structure for a multi-pulse amplitude modulation signal provided according to an embodiment of the present invention is shown (which is the same as the single-ended structure of a common output driving stage mentioned in the background art). Figure 3 The diagram illustrates the grouping of standard cells in the SST drive structure for a multi-pulse amplitude modulation signal provided according to an embodiment of the present invention. Figure 1 and Figure 3 It can be seen that the SST driving structure for multi-pulse amplitude modulation signals provided by the present invention is constructed based on an n-bit DAC module; the SST driving structure for multi-pulse amplitude modulation signals includes 2 n-1 standard unit, wherein all standard units are divided into n groups, and the number of standard units in the k-th group is 2. k-1 Where n and k are both integers, n is a fixed parameter, n≥2; k is a dynamic parameter, k has a minimum value of 0 and a maximum value of n; that is, all standard units are arranged according to 1+2+4+8+…+2 n-1 (=2) n The distribution of -1) is grouped, and the nth group is defined as the MSB group (corresponding to MSB), and the first group is defined as the LSB group (corresponding to LSB); in actual operation, in order to facilitate the resistance correction of the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention, in the MSB group (containing 2) n-1 Divide a portion or all of the standard units (defined as M standard units, where M is an integer, M≤2) into a portion or all of the standard units. n-1 This is used for resistance correction, thereby realizing resistance correction of the SST drive structure for multi-pulse amplitude modulation signals. It should be noted that in the n groups, at least one LSB group and one MSB group are required, therefore, the minimum value of n is 2.

[0045] In a specific embodiment of the present invention, when correcting the resistor of the SST driving structure of the multi-pulse amplitude modulation signal provided by the present invention, m standard units can be selected from the M standard units divided in the MSB group for high impedance. Specifically, in the selected m standard units, the upper and lower switches are forcibly locked in the open state, thereby eliminating m standard units with high impedance. At this time, the number of effective standard units is 2. n -1-m items.

[0046] It should be noted that the SST driving structure for multi-pulse amplitude modulation signals provided by this invention is applicable to all existing types of multi-pulse amplitude modulation signals. In practical applications, PAM4 signals are preferred for multi-pulse amplitude modulation signals. Figure 4 An eye diagram of a PAM4 signal provided according to an embodiment of the present invention is shown, by... Figure 4 It can be seen that, Figure 4 The PAM4 signal in the PAM4 is usually symmetrically positioned at the preset center point of DAC code100..00 (i.e. b'100…00) and moved up and down by + / - 1 S standard units or + / - (1 / 3) S standard units to realize the 4 voltage levels of PAM4; where S is the single-ended swing configured by the designer using the programmable method.

[0047] Specifically, Figure 5 The diagram shows a logic diagram of the pre-processor system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in an embodiment of the present invention without adjusting the resistor; by Figure 5 It is known that after modifying the resistor in the SST drive structure of the pulse amplitude modulation signal provided in this embodiment of the invention, the logic diagram of the corresponding pre-process system cannot maintain the consistency of the PAM4 signal amplitude and linearity before and after the resistor is not modified. To solve this technical problem, the logic of the pre-process system needs to be adjusted, that is... Figure 6 The diagram shows a logic diagram of a first type of pre-processing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in an embodiment of the present invention when correcting the resistor. Figure 6 It is understood that the present invention provides a pre-processing system for the aforementioned SST driving structure of multi-pulse amplitude modulation signals. This system includes a signal input module, a digital logic module, and a remapping module. The signal input module generates a PAM4 signal and configures a set value for the PAM4 signal. The digital logic module processes the configured set value of the PAM4 signal. The remapping module remaps the signal generated by the digital logic module, and the remapped signal serves as the input signal for the SST driving structure of the multi-pulse amplitude modulation signal. The data processing flow formula of the digital logic module is as follows:

[0048] b'100…00+(1 / 3)S'(PAM4;where, PAM4;where, b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal (e.g., Figure 5 As shown, the setting value of the AM4 signal can be set based on the initial binary voltage signal. For example, if the four initial binary voltage signals are 00, 01, 10, and 11 respectively, then the four setting values ​​of the corresponding PAM4 signal can be set as (-3, -1, 1, 3) respectively. S is the single-ended swing of the PAM4 signal, and S' = S * (2 n -1-m) / (2 n -1), where m is an integer, m≤M.

[0049] From the above, it can be seen that compared with the preprocess system without adjusting the resistance, the coefficient S is modified to S'=S*(2 n -1-m) / (2 n -1), this operation is static logic and does not affect system latency (signal delay). Furthermore, since the final MSB (most significant bit) of the DAC is no longer a standard 2^35, n-1 Each unit has a standard binary DAC signal, therefore the standard binary DAC signal sent by the digital logic module must be remapped to reflect the non-binary MSB.

[0050] Figure 7This diagram illustrates the mapping relationship (example diagram) of the remapping module in the first type of preprocessing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in an embodiment of the present invention when correcting the resistor. Figure 7 As shown, taking an 8-bit (n=8) DAC as an example, Figure 7 The left side of the diagram represents standard binary digital logic. The input logic consists of binary numbers [D7 D6 D5 D4 D3 D2 D1 D0], and the output is [D7'D6'D5'D4'D3'D2'D1'D0]. The mapping process, implemented using a classic digital scheme, is as follows: sum divided by 90 to get D7', remainder divided by 64 to get D6', remainder divided by 32 to get D5', and so on to get D0'. While this method is logically correct, it incurs significant overhead, especially in high-speed signal links where latency is substantial, resulting in very low cost-effectiveness in signal systems with transmission delay requirements.

[0051] It should be noted that, based on the research, the first pre-process system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the above embodiments of the present invention when correcting the resistor still has some drawbacks. For example, since a corresponding remapping module has been added, the logic overhead will inevitably increase; and, since the existence of the remapping module, a remapping process will inevitably be introduced, which will inevitably increase the latency on the high-speed signal link.

[0052] To address the aforementioned drawbacks of the first pre-process system provided by this invention, this invention designs another pre-process system. Figure 8 This is a logic diagram of the second type of pre-processing system corresponding to the SST driving structure of the pulse amplitude modulation signal provided in the embodiment of the present invention when correcting the resistance. Figure 8 It is understood that the present invention also provides another pre-process system for the aforementioned SST driving structure of multi-pulse amplitude modulation signals; the system includes a signal input module and a novel digital logic module; wherein, the signal input module is used to generate a PAM4 signal and configure a setting value for the PAM4 signal; the novel digital logic module is used to process the setting value of the PAM4 signal; the signal generated by the novel digital logic module is directly used as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal.

[0053] Furthermore, typically, the four set values ​​of the PAM4 signal are preferably four arrays with 0 as the median (for example, set sequentially to -3, -1, 1, 3). In this case, the data processing flow formula of the novel digital logic module can be set as follows:

[0054] b'100…00+(1 / 3)S'PAM4+ sgn(PAM4)*m / 2; where b'100…00 is the preset center point of the PAM4 signal, and PAM4 is the set value of the PAM4 signal (e.g., ...). Figure 5 As shown, the setting value of the AM4 signal can be set based on the initial binary voltage signal. For example, if the four initial binary voltage signals are 00, 01, 10, and 11 respectively, then the four setting values ​​of the corresponding PAM4 signal can be set to -3, -1, 1, and 3 respectively. S is the single-ended swing of the PAM4 signal, and S' = S * (2 n -1-m) / (2 n -1); where m is an integer, m≤M; sgn(PAM4) is used to obtain the positive and negative signs of the set value of each PAM4 signal. For example, when the set value of a certain PAM4 signal is -3, the data processing formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4-m / 2; when the set value of a certain PAM4 signal is 3, the data processing formula of the new digital logic module is: b'100…00+(1 / 3)S'PAM4+m / 2.

[0055] It should be noted that, for the four set values ​​of the PAM4 signal, it is generally preferred to set them as two sets of positive and negative numbers with 0 as the median. For example, a set of set values ​​is preferably 3, -1, 1, 3. However, in some special cases, the set values ​​of the PAM4 signal are not with 0 as the median (for example, the set of set values ​​is 0, 1, 2, 3). In this case, it is necessary to first find the median of the set of set values ​​and record it as Q. Then, sgn(PAM4-Q) is used to determine the sign of each set value of PAM4. For example, if the set of set values ​​of the PAM4 signal is 0, 1, 2, 3, then Q is the median value of 1.5. In this case, sgn(PAM4-1.5) is used to determine the sign of each set value of PAM4. The data processing formula of the entire new digital logic module is then optimized and changed to: b'100…00+(1 / 3)S'PAM4+ sgn(PAM4-Q)*m / 2, where Q=1.5.

[0056] It should be noted that the calculation of the median value of a set of PAM4 signal settings can be done by simply taking the median value between the maximum and minimum values ​​of the set.

[0057] Therefore, based on the first solution provided by this invention, instead of using a remapping method, the PAM4 signal is directly "matched" in the digital logic module, and a correction parameter of +sgn(PAM4)*m / 2 is applied to complete the remapping requirement of the non-standard MSB. Clearly, compared to the first solution, the second solution provided by this invention eliminates the need for a remapping module, effectively reducing not only the logic overhead of the entire circuit but also the latency of the entire high-speed signal link.

[0058] It should be noted that, in order to further illustrate that although the second scheme provided by the present invention has a simple design logic, it can still achieve the same effect as the original scheme that does not require resistance correction, the following derivation and verification are performed with a positive PAM4 signal input.

[0059] Assuming the target swing of a PAM4 signal is L, then for the original scheme without resistor correction, the corresponding resolution is L / (2). n -1), the corresponding original scheme's data processing formula (i.e. code) is: b'100…00+(1 / 3)S(PAM4), where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, and S is the single-end swing of the PAM4 signal; at this time, through calculation, it can be obtained that in the original scheme, the DAC output is: (2 n-1 + )*L / (2 n -1).

[0060] Assuming the target swing of a certain PAM4 signal is L, then for the second scheme provided by this invention, the corresponding resolution is L / (2). n -1-m), the corresponding data processing formula (i.e. code) of the second scheme provided by the present invention is: b'100…00+(1 / 3)S'PAM4+m / 2 (or it can be set to b'100…00+(1 / 3)S'PAM4-m / 2); where b'100…00 is the preset center point of the PAM4 signal, PAM4 is the set value of the PAM4 signal, S is the single-end swing of the PAM4 signal, and S'=S*(2 n -1-m) / (2 n -1); where m is an integer, m≤M; at this time, the highest bit in b'10…00 is 2. n-1 -m; In the second scheme provided by this invention, the derivation formula for the DAC output is as follows:

[0061] (2 n-1 -m + + ) * L / (2n -1-m)

[0062] = [2 n-1 - + * (2) n -1-m) / (2 n -1) ]* L / (2 n -1-m)

[0063] = [(2 n-1 - )*( 2 n -1) + * (2) n -1-m) ] * L / (2 n -1-m) / (2 n -1)

[0064] = [(2 n - * ( 2 n -1) / 2 / (2 n -1-m) + ] * L / (2 n -1)

[0065] Because of 2 n - >>1, therefore (2) n - / (2 n -1-m) =1; and because 2 n >>1,

[0066] Therefore, the DAC output in the second scheme provided by this invention is:

[0067] (2 n-1 + ) * L / (2 n -1).

[0068] In summary, the DAC output (voltage) in the second solution provided by this invention is consistent with the output (voltage) of the original solution. Therefore, although the design logic of the second solution provided by this invention is simple, it can still achieve the same effect as the original solution that does not require resistor correction.

[0069] Compared with existing technologies, the above-mentioned SST driving structure based on multi-pulse amplitude modulation signals and its pre-processing system have the following advantages:

[0070] By designing a resistor adjustment scheme for the SST drive structure of multi-pulse amplitude modulation signal, the linearity of the circuit can be maintained without affecting the circuit linearity when correcting the resistor, and the output SST swing will not be reduced. In addition, the information digital logic module in the front-end process system provided by this invention can eliminate the setting of the remapping module by optimizing the data processing flow formula, further reducing the logic overhead of the entire circuit and further reducing signal latency.

[0071] As referred above Figures 1 to 9 The SST driving structure for multi-pulse amplitude modulation signals and its pre-processing system according to the present invention are described by way of example. However, those skilled in the art should understand that various modifications can be made to the SST driving structure for multi-pulse amplitude modulation signals and its pre-processing system proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A SST drive structure of a multi-pulse amplitude modulation signal; characterized by, The DAC module is constructed based on n-bit, including 2n-1 standard units, wherein the multi-pulse amplitude modulation signal is a PAM4 signal, all the standard units are divided into n groups, and the number of standard units in the kth group is 2k-1; wherein n and k are integers, n≥2, and k≤n; and the first group is defined as the LSB group, and the nth group is defined as the MSB group; wherein M standard units in the MSB group are divided for resistance correction; wherein M is an integer, and M≤2n-1; when the resistance is corrected, m standard units are taken from the M standard units in the MSB group for high resistance.

2. A pre-processing system for the SST drive structure applied to the multi-pulse amplitude modulation signal of claim 1, characterized by, The signal input module, the digital logic module, and the remapping module are included; wherein The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The digital logic module is used to process the set value of the PAM4 signal; The remapping module is used to remap the signal generated by the digital logic module, and the remapped signal is used as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal; wherein the data processing flow formula of the digital logic module is: b'100...00+(1 / 3)S'PAM4; wherein b'100...00 is a preset center point of the PAM4 signal, PAM4 is a set value of the PAM4 signal, S'=S*(2n-1-m) / (2n-1), and S is a single-ended swing of the PAM4 signal; wherein m is an integer, and m≤M.

3. A pre-processing system for the SST drive structure applied to the multi-pulse amplitude modulation signal of claim 1, characterized by, The signal input module and the new digital logic module are included; wherein The signal input module is used to generate a PAM4 signal and configure a set value for the PAM4 signal; The new digital logic module is used to process the set value of the PAM4 signal; The signal generated by the new digital logic module is directly used as the input signal of the SST driving structure of the multi-pulse amplitude modulation signal; wherein When the four set values of the PAM4 signal take 0 as the median value, the data processing flow formula of the new digital logic module is: b'100...00+(1 / 3)S'PAM4+sgn(PAM4)*m / 2; wherein b'100...00 is a preset center point of the PAM4 signal, PAM4 is a set value of the PAM4 signal, S'=S*(2n-1-m) / (2n-1), and S is a single-ended swing of the PAM4 signal; wherein m is an integer, and m≤M; When the four set values of the PAM4 signal do not take 0 as the median value, the data processing flow formula of the new digital logic module is: b'100...00+(1 / 3)S'PAM4+sgn(PAM4-Q)*m / 2; wherein b'100...00 is a preset center point of the PAM4 signal, PAM4 is a set value of the PAM4 signal, S'=S*(2n-1-m) / (2n-1), and S is a single-ended swing of the PAM4 signal; wherein m is an integer, and m≤M, and Q is the median value of the four set values of the PAM4 signal.

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