Multichannel video processing system capable of sharing memory

Abstract

The invention discloses a multichannel video processing system capable of sharing a memory, and relates to the technical field of video processing. The multi-channel video processing system comprises an item register, a global register, an image processing circuit and a video coding circuit. The image processing circuit processes input image data to generate first image frame data, writes the first image frame data into a shared memory, and updates the global register when the first image frame data is written into the shared memory. And the item register is updated after the first image frame data is written into the shared memory. The video coding circuit reads second image frame data from the shared memory according to the item register for coding, updates the global register when reading the second image frame data, and judges whether an abnormal state occurs between the image processing circuit and the video coding circuit according to the global register.

Description

Technical Field

[0001] The present application relates to the field of video processing technology, and in particular to a multi-channel video processing system capable of sharing a memory. Background Art

[0002] In traditional video processing systems, each channel of the scaling controller circuit needs to be independently configured with a set of memory buffers (including two memory blocks) to support write and read operations during the processing process. For example, when the scaling controller circuit uses a double-buffer setting, if the system includes N channels, at least 2N memory blocks need to be configured. The size of the memory block usually depends on the image resolution of the channel output. Therefore, when supporting high-resolution or multi-channel output scenarios, the overall memory usage will increase significantly. In addition, this memory management method fails to effectively share resources, resulting in a large amount of memory in the system being statically bound to individual channels. Even if some channels are not currently enabled or the data update frequency is low, the corresponding memory blocks cannot be released, resulting in low overall memory utilization efficiency, which in turn affects the overall image processing performance and system scalability. Summary of the Invention

[0003] In some embodiments, one of the objectives of the present application, but not limited to, is to provide a multi-channel video processing system with a shared memory to improve the problems of the prior art.

[0004] In some embodiments, a multi-channel video processing system includes an entry register, a global register, a processing circuit, and a video encoding circuit. The image processing circuit processes input image data to generate first frame data and writes the first frame data to a shared memory. The global register is updated when the first frame data is written to the shared memory, and an entry register is updated after the first frame data is written to the shared memory. The video encoding circuit reads second frame data from the shared memory for encoding based on the entry register, updates the global register when reading the second frame data, and determines whether an abnormal state occurs between the image processing circuit and the video encoding circuit based on the global register.

[0005] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1 A schematic diagram of a multi-channel video processing system according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application Figure 1 A schematic diagram of multiple channels of an image processing circuit and multiple channels of a video encoding circuit sharing a common memory;

[0009] Figure 3 According to some embodiments of the present application Figure 1 Operation flow chart of the image processing circuit;

[0010] Figure 4 According to some embodiments of the present application Figure 1 Operation flow chart of the video encoding circuit;

[0011] Figure 5 According to some embodiments of the present application Figure 4 A flowchart of the steps of an operation in FIG.

[0012] Figure 6 According to some embodiments of the present application Figure 4 A flowchart of the steps of an operation in FIG.

[0013] Figure 7 According to some embodiments of the present application Figure 4 A flowchart of the steps of an operation in

[0014] Figure 8 The following is a schematic diagram illustrating an operation of a 2-channel image processing circuit using a shared memory according to some embodiments of the present application.

[0015] Reference numerals:

[0016] 100: Multi-channel video processing system;

[0017] 110: image sensor;

[0018] 120: Image signal processor;

[0019] 130: memory;

[0020] 140: image processing circuit;

[0021] 141, 142, 143, 144: processing module;

[0022] 150: shared memory;

[0023] 160: video encoding circuit;

[0024] 161, 162, 163, 164: encoding module;

[0025] 170: Project register;

[0026] 180: global register;

[0027] 190: CPU;

[0028] 801: Last address;

[0029] 802: initial address;

[0030] CH0, CH1, CH2, CH3: channels;

[0031] DIN, DIN': input image data;

[0032] ENA1, ENA2: end address;

[0033] F1, F2, F3: image frame data;

[0034] S310, S320, S330, S340, S350, S360, S370, S380: operation;

[0035] S410, S420, S430, S440, S450, S460, S470, S480: operation;

[0036] S510, S520, S530, S610, S620, S630, S640, S710, S720, S730: steps;

[0037] SO: video streaming;

[0038] STA1, STA2: starting address. DETAILED DESCRIPTION

[0039] All terms used in this application have their ordinary meanings. The definitions of the aforementioned terms in commonly used dictionaries, including any examples of their use in this application, are intended to be illustrative only and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments described herein.

[0040] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action of two or more components. As used herein, the term "circuit" may refer to a device comprised of at least one transistor and / or at least one active or passive component connected in a specific manner to process signals.

[0041] Figure 1 FIG1 is a schematic diagram of a multi-channel video processing system 100 according to some embodiments of the present application. The multi-channel video processing system 100 includes an image sensor 110, an image signal processor 120, a memory 130, an image processing circuit 140, a shared memory 150, a video encoding circuit 160, an entry register 170, a global register 180, and a central processing unit 190.

[0042] Image sensor 110 may be, but is not limited to, a camera, and may capture a frame of image data as input image data DIN. Image processing circuit 140 may perform primary image processing on input image data DIN to generate input image data DIN′, which is then stored in memory 130. In some embodiments, the primary image processing may include, but is not limited to, one or more of the following operations: black level correction, noise suppression, lens distortion compensation, high dynamic range imaging, color correction, brightness correction, edge enhancement, etc. In some embodiments, memory 130 may be, but is not limited to, dynamic random access memory (DRAM).

[0043] In some embodiments, when an application program wishes to perform one or more image (or video) processing tasks, the application program may request the operating system or system kernel executed by the CPU 190 to allocate a storage space in the memory 130, which is the shared memory 150. In other words, the shared memory 150 is a storage space provided by the memory 130. Multiple channels of the image processing circuit 140 and multiple channels of the video encoding circuit 160 may share this shared memory 150 to perform the one or more image (or video) processing tasks described above. Each of the image processing circuit 140 and the video encoding circuit 160 may update the global register 180 during the execution of the image (or video) processing task and update the entry register 170 after the image (or video) processing task is completed. In this way, the image processing circuit 140 and the video encoding circuit 160 can coordinate with each other based on the project register 170 and the global register 180 to jointly use the shared memory 150. Furthermore, the video encoding circuit 160 can also determine whether an abnormality has occurred between the image processing circuit 140 and the video encoding circuit 160 based on the global register 180 during the execution of a task. If an abnormality is determined to have occurred, the video encoding circuit 160 can discard the currently processed frame data.

[0044] For example, when a channel of the image processing circuit 140 determines that it has received input image data DIN' to be processed, the image processing circuit 140 may perform image processing on the input image data DIN' through the channel to generate image frame data F1, and write the image frame data F1 to the shared memory 150. When writing the image frame data F1 to the shared memory 150, the image processing circuit 140 may update the global register 180. After writing the image frame data F1 to the shared memory 150, the image processing circuit 140 may update the project register 170. In some embodiments, the image processing performed by the image processing circuit 140 may include, but is not limited to, image magnification, reduction, cropping, flipping, etc. That is, in some embodiments, the image processing circuit 140 may be a scaler circuit. In some embodiments, the image processing performed by the image processing circuit 140 may also include one or more operations in the aforementioned primary image processing. The relevant operations of the image processing circuit 140 will be referred to below. Figure 3 illustrate.

[0045] When one channel of the video encoding circuit 160 determines that it has received the frame data F2 to be processed, the video encoding circuit 160 can read the frame data F2 from the shared memory 150 according to the entry register 170 to encode and generate the video stream SO. When reading the frame data F2, the video encoding circuit 160 can update the global register 180 and determine whether an abnormal state occurs between the image processing circuit 140 and the video encoding circuit 160 according to the global register 180. The relevant operations of the video encoding circuit 160 will be referred to below. Figures 4 to 7 illustrate.

[0046] Figure 2 According to some embodiments of the present application Figure 1FIG1 is a schematic diagram illustrating a shared memory 150 shared by multiple channels of an image processing circuit 140 and multiple channels of a video encoding circuit 160. In some embodiments, the image processing circuit 140 includes multiple processing modules 141, 142, 143, and 144, which sequentially correspond to the multiple channels CH0, CH1, CH2, and CH3. Each of the multiple processing modules 141, 142, 143, and 144 may store generated frame data (e.g., the aforementioned frame data F1) in the shared memory 150. Similarly, in some embodiments, the video encoding circuit 160 includes multiple encoding modules 161, 162, 163, and 164, which sequentially correspond to the multiple channels CH0, CH1, CH2, and CH3. Each of the multiple encoding modules 161, 162, 163, and 164 may read corresponding frame data (e.g., the aforementioned frame data F2) from the shared memory 150 and encode the data to generate a video stream SO. In some embodiments, the video stream SO outputted via channels CH0 and CH1 may be the main stream, while the video stream SO outputted via channels CH2 and CH3 may be the sub-stream. Users may choose whether to use or view the sub-stream based on actual needs.

[0047] In some related technologies, when adding a new channel for outputting video streams, two additional storage spaces need to be applied to the system memory. In other words, in these technologies, if there are N channels for image processing and encoding, 2N storage spaces need to be applied. This will occupy too much system memory space. Compared with the above-mentioned related technologies, in some embodiments of the present application, such as Figure 1 and Figure 2 As shown, multiple channels of the image processing circuit 140 and multiple channels of the video encoding circuit 160 can share a common memory 150 based on the project register 170 and the global register 180, thereby improving the utilization efficiency of the system memory (such as the memory 130) and reducing the occupation of the system memory.

[0048] In some embodiments, Table 1 below is an example of a configuration of the project register 170 .

[0049] Table 1 An example of setting of the project register 170

[0050]

[0051]

[0052] In Table 1 above, multiple item numbers Entry[0] to Entry[3] correspond to multiple item information and different frame data. That is, in this example, the image processing circuit 140 can store up to four frames of image data in the shared memory 150, but this application is not limited to this. In the item information, the starting address represents the starting storage address of the frame data written by a certain channel of the image processing circuit 140 in the shared memory 150, the ending address represents the last storage address of the frame data written by a certain channel of the image processing circuit 140 in the shared memory 150, the data size represents the amount of frame data written by a certain channel of the image processing circuit 140, the operating status represents the status of the frame data processed by the image processing circuit 140, the channel index value is the index value of a certain channel of the image processing circuit 140, and the frame index value is the index value of the frame data currently being processed by the image processing circuit 140. In some embodiments, the operating status may have three values, including an initial value, a first preset value, and a second preset value, wherein the initial value indicates the status after hardware initialization, the first preset value indicates that the image processing circuit 140 is processing the frame data corresponding to this project information, and the second preset value indicates that the image processing circuit 140 has completed processing the frame data corresponding to this project information.

[0053] In some embodiments, Table 2 below is an example of a configuration of the global register 180 .

[0054] Table 2 An example of setting the global register 180

[0055] information Curr_w_entry_idx Curr_r_entry_idx Curr_w_addr Overflow_status LineCnt

[0056] In Table 2 above, Curr_w_entry_index is the write entry index value, indicating that the image processing circuit 140 is currently processing a frame of data corresponding to a corresponding entry in the entry register 170. Curr_r_entry_idx is the read entry index value, indicating that the video encoding circuit 160 is currently reading corresponding frame data (e.g., the aforementioned frame data F2) from the shared memory 150 based on the corresponding entry in the entry register 170. Curr_w_addr is the write address, indicating the storage address of the frame data currently being processed by the image processing circuit 140 in the shared memory 150 (which is updated in real time by the image processing circuit 140). Overflow_status is used to indicate whether an abnormal state, such as overflow, occurs during encoding by the video encoding circuit 160. For example, the write address of the current frame data of the image processing circuit 140 exceeds the storage address of the shared memory 150. The video encoding circuit 160 can determine whether the currently processed frame data has overflowed based on the status of Overflow_status. If so, it determines that an abnormal situation has occurred and discards the currently processed frame data accordingly. LineCnt is used to indicate the number of rows of frame data currently being written by the image processing circuit 140 and is updated in real time by the image processing circuit 140. LineCnt can be used to prevent the processing progress of the video encoding circuit 160 from exceeding that of the image processing circuit 140. For example, if the image processing circuit 140 and the video encoding circuit 160 are processing the same frame data, the video encoding circuit 160 can, based on the value reflected in the LineCnt information, read the data of a coding block from the shared memory 150 for encoding after the image processing circuit 140 has completed writing all rows of the coding block required for encoding.

[0057] As can be seen from the above description, in some embodiments, while the image processing circuit 140 is writing frame data to the shared memory 150, the video encoding circuit 160 can simultaneously read frame data (which can be the same frame data or different frame data) from the shared memory 150 for encoding. To avoid usage conflicts, in addition to setting the aforementioned Overflow_status and LineCnt information, in some embodiments, the operating speed (or clock frequency) of the video encoding circuit 160 can be configured to be lower than the operating speed (or clock frequency) of the image processing circuit 140.

[0058] Figure 3 According to some embodiments of the present application Figure 1FIG3 is a flowchart of the operation of the image processing circuit 140. In this example, it is assumed that the image processing circuit 140 has N channels and the current channel index value is n. In operation S310, information about the shared memory 150 and a command to start image processing are received from the central processing unit 190. For example, when a system application wants to perform a task related to image processing, the application may request the operating system or system kernel running on the central processing unit 190 to configure a specific storage space in the memory 130 as the shared memory 150. The central processing unit 190 sends information about the shared memory 150 (e.g., the starting address and ending address, etc.) to the image processing circuit 140 and sends a start command to the image processing circuit 140.

[0059] In operation S320, confirm whether the input image data DIN' is received and whether the current channel index value n is less than the number of channels N. If it is confirmed that the input image data DIN' is received and the channel index value n is less than the number of channels N, execute operation S330. If one of them is no, end this operation. In operation S330, obtain the current frame index value and the address information of the shared memory 150. In operation S340, perform image processing on the input image data DIN' to generate frame data F1 and write the frame data F1 to the shared memory 150, and update the global register 180 at the same time. In operation S350, determine whether one frame data has been written. If so, execute operation S360. If not, execute operation S370. In operation S360, update the project register 170. In operation S370, report that an abnormal situation has occurred.

[0060] For example, after receiving a command from the central processing unit 190, if channel n of the image processing circuit 140 confirms receipt of the input image data DIN' to be processed, the image processing circuit 140 may obtain the current channel index value n, the frame index value, and the relevant address information of the shared memory 150. When the current channel index value n is not greater than the number of channels N, the image processing circuit 140 may begin image processing on the input image data DIN' to generate the frame data F1. While writing the frame data F1 to the shared memory 150, the image processing circuit 140 will simultaneously update the information in the global register 180 (e.g., including the write entry index value Curr_w_entry_index, the write address Curr_w_addr, and the information LineCnt). After writing a frame of data, the image processing circuit 140 will update the relevant information within the corresponding entry information in the entry register 170 accordingly. For example, after writing frame data F1, image processing circuit 140 will update the entry information corresponding to entry [0], including the start address, end address, data size, operation status, channel index, and frame index. Alternatively, if writing a frame of data fails, indicating a possible image processing error, image processing circuit 140 will report an error to the software or system layer.

[0061] In operation S380, the current channel index value n is updated to n+1, and operation S320 is continued to be performed. In this way, the image processing circuit 140 can switch to the next channel to continue processing the subsequent input image data DIN'.

[0062] Figure 4 According to some embodiments of the present application Figure 1 , which is a flow chart of the operation of the video encoding circuit 160. In this example, it is assumed that the video encoding circuit 160 has M channels, and the current channel index value is m. In operation S410, after receiving the encoding task issued by the central processing unit 190, it is confirmed whether the image frame data to be encoded is received, and whether the current channel index value m is less than the number of channels M. If it is confirmed that the image frame data to be encoded is received, and the current channel index value m is less than the number of channels M, operation S420 is performed. If either of them is no, the operation is terminated. In operation S420, the project register 170 is searched according to the current channel index value m to confirm whether a corresponding project information can be found. If so, operation S430 is performed. If not, the operation is terminated.

[0063] For example, if the CPU 190 has not issued an encoding task, or the current channel index value m exceeds the number of channels M, the video encoding circuit 160 will terminate the task accordingly. If the CPU 190 has issued an encoding task (including pending project information) to the video encoding circuit 160, and the current channel index value m does not exceed the number of channels M, the video encoding circuit 160 will search the multiple project information in the project register 170 based on the channel index value m to select a corresponding project information having the channel index value m.

[0064] In operation S430, determine whether overflow occurs. If not, execute operation S440. If yes, execute operation S480. In operation S440, read out the frame data (for example, the frame data F2) according to the corresponding project information, and encode the frame data to generate the video stream SO, and update the global register 180 at the same time. In operation S450, confirm whether the encoding is completed. If yes, execute operation S460. If no, execute operation S480. In operation S460, confirm whether overflow occurs. If no, execute operation S470. If yes, execute operation S480. In operation S470, update the current channel index value m to m+1, and continue to execute operation S410. In this way, the video encoding circuit 160 can switch to the next channel to continue processing the subsequent frame data. In operation S480, report the occurrence of an abnormal situation.

[0065] For example, if channel m of the video encoding circuit 160 confirms that it has received the frame data F2 to be encoded, and the index value of channel m is not greater than the number of channels M, the video encoding circuit 160 may retrieve the corresponding entry information (including the channel index value m) from the multiple entry information in the entry register 170 and determine whether an overflow has occurred based on the corresponding entry information. The video encoding circuit 160 may determine whether an overflow has occurred based on the Overflow_status information in the corresponding entry information (operation S430). Alternatively, the video encoding circuit 160 may determine whether the start address indicated by the encoding task exceeds the address range of the shared memory 150 (operation S430). If an overflow has occurred, the video encoding circuit 160 terminates the encoding operation. If an overflow has not occurred, the video encoding circuit 160 may read the frame data F2 from the shared memory 150 based on the start and end addresses recorded in the corresponding entry information and encode the frame data F2. During this process, the video encoding circuit 160 may simultaneously update the read entry index value Curr_r_entry_idx in the global register 180. After encoding is complete, the video encoding circuit 160 can determine whether an overflow or other abnormality has occurred between the image processing circuit 140 and the video encoding circuit 160 based on the project register 170 and the global register 180. If an abnormality has occurred, or if encoding cannot be completed, the video encoding circuit 160 will report the abnormality to the software layer or application layer and discard the currently processed frame data F2, thus ending the current operation.

[0066] As can be seen from the above operation process, the image processing circuit 140 simultaneously updates the global register 180 while writing the frame data F1 and, after writing the frame data F1, updates the corresponding entry information in the project register 170. Furthermore, when encoding the frame data F2, the video encoding circuit 160 retrieves the corresponding frame data from the shared memory 150 based on the corresponding entry information in the project register 170 and simultaneously updates the global register 180. In this way, the multiple channels in the image processing circuit 140 and the multiple channels in the video encoding circuit 160 can coordinate with each other based on the global register 180 to share the shared memory 150. Furthermore, the video encoding circuit 160 can also determine whether an abnormality has occurred based on the multiple information in the global register 180 (and / or the project register 170).

[0067] Figure 3 and Figure 4 The description of the multiple operations can refer to the above multiple embodiments, so they will not be repeated here. The above multiple operations are only examples and are not limited to being executed in the order shown in this example. Without violating the operation mode and scope of each embodiment of this application, Figure 3 and Figure 4The various operations in can be appropriately added, replaced, omitted or performed in a different order. Figure 3 and Figure 4 One or more operations may be performed concurrently or with partial concurrence.

[0068] Figure 5 According to some embodiments of the present application Figure 4 Flowchart of the steps of operation S460 in . In step S510, the write item index value and the read item index value are obtained from the global register 180, wherein the write item index value indicates that the image processing circuit 140 is writing the frame data F1, and the frame data F1 corresponds to the first item information, and the read item index value indicates that the video encoding circuit 160 is reading the frame data F2 according to the second item information. In step S520, it is confirmed whether the write item index value becomes the same as the read item index value during the process of encoding the frame data F2 by the video encoding circuit 160. If so, step S530 is executed. In step S530, it is determined whether an abnormal situation occurs, that is, an overflow occurs. If not, it is determined that no abnormality occurs, that is, no overflow occurs, and operation S470 is executed.

[0069] In this example, the image processing circuit 140 and the video encoding circuit 160 are using different entry information. During the encoding of frame data F2, if the write entry index value Curr_w_entry_index in the global register 180 suddenly becomes the same as the read entry index value Curr_r_entry_idx in the global register 180 (i.e., the entry information corresponding to the frame data F1 being written by the image processing circuit 140 becomes the same as the entry information corresponding to the frame data F2 being encoded by the image processing circuit 140), this indicates that the frame data F1 being written by the image processing circuit 140 is overwriting the frame data F2 being read by the video encoding circuit 160. Therefore, the video encoding circuit 160 can determine that an abnormality has occurred.

[0070] Figure 6 According to some embodiments of the present application Figure 4Flowchart of the steps of operation S460 in . In step S610, the write item index value and the read item index value are obtained from the global register 180, wherein the write item index value indicates that the image processing circuit 140 is writing the frame data F1, and the frame data F1 corresponds to the first item information, and the read item index value indicates that the video encoding circuit 160 is reading the frame data F2 according to the second item information. In step S620, it is confirmed whether the first item information and the second item information are the same corresponding item information. If so, step S630 is executed. If not, it is determined that no abnormality has occurred and operation S470 is executed. In step S630, it is confirmed whether the operating state of the corresponding item information has changed to the initial value during the process of the video encoding circuit 160 encoding the frame data F2. If so, step S640 is executed. In step S640, it is determined whether an abnormal situation has occurred. If not, it is determined that no abnormality has occurred and operation S470 is executed.

[0071] In this example, the image processing circuit 140 and the video encoding circuit 160 are using the same project information. For example, the image processing circuit 140 and the video encoding circuit 160 are operating using the project information corresponding to Entry[0]. Normally, during the process of the video encoding circuit 160 encoding the image frame data corresponding to this project information, the operating state in this project information should be the first preset value or the second preset value mentioned above. If, during the above process, the operating state in this project information suddenly switches to the initial value, it means that an abnormality may have occurred in the hardware operation, causing the project register 170 to be initialized again. Under this condition, the video encoding circuit 160 can determine that an abnormal situation has occurred.

[0072] Figure 7 According to some embodiments of the present application Figure 4 Flowchart of the steps of operation S460 in . In step S710, a read item index value is obtained from the global register 180, wherein the read item index value indicates that the video encoding circuit 160 is reading the frame data F2 according to the corresponding item information in the item register 170. In step S720, it is confirmed whether the operation status of the corresponding item information has changed to an initial value or a preset value during the process of encoding the frame data F2 by the video encoding circuit 160, wherein the preset value indicates that the image processing circuit 140 is updating the frame data corresponding to the corresponding item information. If so, step S730 is executed. If not, it is determined that no abnormality has occurred, and operation S470 is executed. In step S730, it is determined that an abnormal situation has occurred.

[0073] In this example, while the video encoding circuit 160 reads and encodes the frame data F2 according to the corresponding project information, the operating state of the corresponding project information should remain at the aforementioned second preset value. If the operating state switches to the initial value or the aforementioned first preset value during this process, this indicates that a hardware abnormality (e.g., the image processing circuit 140) has occurred, causing the project register 170 to be initialized, or that the image processing circuit 140 is updating the frame data F1 of the corresponding project information (equivalent to the aforementioned data overwriting). Under these conditions, the video encoding circuit 160 can determine that an abnormality has occurred.

[0074] Figure 8 The following is a schematic diagram illustrating the operation of a two-channel image processing circuit 140 using a shared memory 150 according to some embodiments of the present application. In this example, the first channel of the image processing circuit 140 generates frame data F1, and the second channel of the image processing circuit 140 generates frame data F3. Frame data F1 is stored between the start address STA1 and the end address ENA1 of the shared memory 150. Frame data F3 is stored between the start address STA2 and the end address ENA2 of the shared memory 150. In this example, the start address STA2 and the end address ENA1 are consecutive memory addresses. For example, the start address STA2 can be the end address ENA1 plus 1. This allows the second channel of the image processing circuit 140 to continue using the remaining storage space of the shared memory 150 after the image processing circuit 140 receives frame data F1.

[0075] Furthermore, in this example, because the amount of frame data F3 is relatively large, the sum of the start address STA2 and the amount of data exceeds the last address 801 of the shared memory 150. Under this condition, the image processing circuit 140 can return to the initial address 802 of the shared memory 150 to continue writing frame data F3. In other words, in this example, a portion of the frame data F1 will be overwritten with a portion of the frame data F3.

[0076] Through the above-described operation method, the image processing circuit 140 having two channels can use the common memory 150 with different channels, thereby achieving the technology of multiple channels sharing the same memory. The above example is only described with two channels, but the present application is not limited to this. The above-described memory management mechanism can be extended and applied to image processing circuits 140 and video encoding circuits 160 having more channels. In summary, the multi-channel video processing system provided by some embodiments of the present application can allow the image processing circuit and encoding circuit with multiple channels to share the same storage space in a time-division multiplexing manner. In this way, unnecessary loss of system memory can be greatly reduced and memory utilization efficiency can be improved.

[0077] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit content of the present application. All such changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application defined in this specification.

Claims

1. A multi-channel video processing system, characterized in that: include: a project register; a global register; an image processing circuit that processes input image data to generate first frame data and writes the first frame data to a shared memory, updates the global register when writing the first frame data to the shared memory, and updates the entry register after writing the first frame data to the shared memory; as well as A video encoding circuit reads a second frame of data from the shared memory for encoding according to the entry register, updates the global register when reading the second frame of data, and determines whether an abnormal state occurs between the image processing circuit and the video encoding circuit according to the global register.

2. The multi-channel video processing system according to claim 1, wherein: The project register stores a plurality of project information, and the image processing circuit updates a corresponding piece of project information among the plurality of project information after writing the first image frame data into the shared memory.

3. The multi-channel video processing system according to claim 1, wherein: The image processing circuit includes a plurality of first channels, and the video encoding circuit includes a plurality of second channels. The plurality of first channels and the plurality of second channels share the common memory based on the project register and the global register to process the input image data.

4. The multi-channel video processing system according to claim 1, wherein: The project register stores multiple project information, the global register stores a write project index value and a read project index value, the write project index value indicates that the image processing circuit is writing the first frame data, and the first frame data corresponds to a first project information among the multiple project information, the read project index value indicates that the video encoding circuit is reading the second frame data according to a second project information among the multiple project information, and if the write project index value becomes the same as the read project index value during the process of the video encoding circuit encoding the second frame data, the video encoding circuit determines that the abnormal state has occurred.

5. The multi-channel video processing system according to claim 1, wherein: The project register stores multiple project information, each of the multiple project information includes an operation status, the global register stores a write project index value and a read project index value, the write project index value indicates that the image processing circuit is writing the first frame data, and the first frame data corresponds to a first project information among the multiple project information, the read project index value indicates that the video encoding circuit is reading the second frame data according to a second project information among the multiple project information, and if the first project information and the second project information are both corresponding project information among the multiple project information, and the operation status of the corresponding project information becomes an initial value during the process of the video encoding circuit encoding the second frame data, the video encoding circuit determines that the abnormal state has occurred.

6. The multi-channel video processing system according to claim 1, wherein: The project register stores multiple project information, each of the multiple project information includes an operation status, the global register stores a read project index value, the read project index value indicates that the video encoding circuit is reading the second frame data according to a corresponding project information among the multiple project information, and if the operation status of the corresponding project information becomes an initial value or a preset value during the process of the video encoding circuit encoding the second frame data, the video encoding circuit determines that the abnormal state has occurred, and the preset value indicates that the image processing circuit is updating the frame data corresponding to the corresponding project information.

7. The multi-channel video processing system according to claim 1, wherein: An operating speed of the video encoding circuit is lower than an operating speed of the image processing circuit.

8. The multi-channel video processing system according to claim 1, wherein: A first channel of the image processing circuit processes the input image data to generate the first frame data, and a second channel of the image processing circuit processes the input image data to generate the third frame data, the first frame data is stored between a first starting address and a first ending address of the shared memory, the third frame data is stored between a second starting address and a second ending address of the shared memory, and the first ending address and the second starting address are consecutive addresses.

9. The multi-channel video processing system according to claim 1, wherein: A first channel of the image processing circuit processes the input image data to generate the first frame data, and a second channel of the image processing circuit processes the input image data to generate the third frame data. If the sum of a first starting address of the third frame data in the shared memory and a data size of the third frame data exceeds a last address of the shared memory, the image processing circuit returns to an initial address of the shared memory to continue writing the third frame data.

10. The multi-channel video processing system according to claim 1, wherein: When the video encoding circuit determines that the abnormal state occurs, the video encoding circuit discards the second image frame data.

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