Semiconductor device etching method and semiconductor process equipment

Abstract

The invention provides an etching method of a semiconductor device and semiconductor process equipment, relates to the field of semiconductor manufacturing, and is designed for solving the problem that the uniformity becomes poor from top to bottom when a high aspect ratio structure is formed by a dry etching process provided by the related technology. The etching method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a substrate and a patterned mask layer; controlling the semiconductor device to enter the process chamber; gas introduced into the process chamber comprises fluorine-based gas, dissociation promoting gas and diluent gas, the dissociation promoting gas comprises oxygen and nitrogen and is used for promoting dissociation of fluorine ions in the fluorine-based gas, the flow of the oxygen is 30 sccm to 60 sccm, and the flow of the nitrogen is 40 sccm to 70 sccm; and the radio frequency power range of the upper electrode assembly is 800W-1500W. According to the invention, the etching rate difference between the top and the bottom of the hole structure can be reduced, so that the uniformity from top to bottom during etching of the high aspect ratio structure is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an etching method for a semiconductor device and semiconductor process equipment. Background Art

[0002] In 3D DRAM (Dynamic Random Access Memory) architectures, word lines (WLs) serve as the core electrodes that control the conduction of memory cells and the reading and writing of data. Their morphology accuracy directly impacts the performance and reliability of semiconductor devices. As the number of 3D stacked layers increases, WLs often require dry etching to form high-aspect-ratio vertical trenches or vias.

[0003] However, when the dry etching process provided by the relevant technology is used to form the above-mentioned high aspect ratio structure, there is a situation where the transmission efficiency of the etching gas at the bottom of the deep trench decreases, resulting in nonlinear attenuation of the etching rate, and causing the uniformity of the formed high aspect ratio structure from top to bottom to deteriorate, not only forming abnormal morphologies such as "bottle-shaped" or "trumpet-shaped", increasing the risk of uneven WL resistance distribution, but also causing sidewall roughness and the formation of micro-grooves. Summary of the Invention

[0004] The first object of the present invention is to provide an etching method for a semiconductor device to solve the technical problem that the dry etching process provided by the related art has poor uniformity from top to bottom when forming a high aspect ratio structure.

[0005] The present invention provides a method for etching a semiconductor device, comprising:

[0006] Providing a semiconductor device, the semiconductor device comprising a substrate and a patterned mask layer;

[0007] Controlling the semiconductor device to enter the process chamber;

[0008] Etching to form a pore structure on the substrate, wherein the gas introduced into the process chamber includes a fluorine-based gas, a dissociation-promoting gas and a dilution gas, the dissociation-promoting gas is used to promote the dissociation of fluorine ions in the fluorine-based gas, and the dissociation-promoting gas includes oxygen and nitrogen, the flow rate of the oxygen is between 30sccm and 60sccm, and the flow rate of the nitrogen is between 40sccm and 70sccm; the RF power range of the upper electrode assembly of the process chamber is 800W to 1500W.

[0009] Furthermore, the fluorine-based gas includes a combination of one or more of nitrogen trifluoride, carbon tetrafluoride and sulfur hexafluoride.

[0010] Furthermore, the flow rate of the fluorine-based gas is between 17 sccm and 25 sccm.

[0011] Furthermore, the dilution gas includes helium, and the flow rate of the helium is between 1200 sccm and 1700 sccm.

[0012] Furthermore, the pressure of the process chamber is between 150 mTorr and 250 mTorr.

[0013] Furthermore, the etching is maintained for a time between 16s and 25s.

[0014] Furthermore, the substrate is made of silicon.

[0015] Furthermore, the mask layer is made of silicon oxide.

[0016] Furthermore, the aspect ratio of the hole structure is greater than 10:1.

[0017] The beneficial effects brought about by the etching method of the semiconductor device of the present invention are:

[0018] After placing a semiconductor device having a substrate and a patterned mask layer in a process chamber, a fluorine-based gas is introduced into the process chamber, and the substrate can be etched using fluorine ions in the fluorine-based gas to form a pore structure with a high aspect ratio. Furthermore, by introducing a dissociation-promoting gas into the process chamber, the dissociation of fluorine ions in the fluorine-based gas can be promoted, so that as many fluorine ions in the fluorine-based gas as possible can be dissociated. Simultaneously, the introduction of a dilution gas can increase the mean free path of the fluorine ions, allowing the fluorine ions in the process chamber to smoothly reach the bottom of the pore structure, thereby reducing the difference in etching rate between the top and bottom of the pore structure. This ensures top-down uniformity when etching the high aspect ratio structure, making the etching morphology between word lines nearly vertical, thereby reducing the risk of current leakage due to the generation of a "V"-shaped morphology between word lines and also reducing parasitic capacitance.

[0019] In the above-mentioned etching method, oxygen and nitrogen can weaken the bonding energy of the fluorine groups in the fluorine-based gas through collision energy transfer and electron excitation, reducing the energy required for direct dissociation. By setting the oxygen flow rate between 30 sccm and 60 sccm, not only can sufficient collision frequency be provided to promote chemical bond breakage and fluorine group dissociation, but it can also prevent the fluorine-based gas from being diluted by excessive oxygen, which would lead to a decrease in etching rate. By setting the nitrogen flow rate to be greater than the oxygen flow rate, on the one hand, the plasma impedance of the process chamber can be balanced, avoiding discharge fluctuations caused by excessive oxygen. On the other hand, the excess nitrogen can also balance the fluorine ion concentration, avoiding excessive fluorine ion consumption caused by excessive oxygen, thereby achieving a balance between oxidation and fluorination.

[0020] By setting the RF power range of the upper electrode assembly of the process chamber to 800W to 1500W, the fluorine ions in the fluorine-based gas can be more fully dissociated, so that more fluorine ions can participate in the reaction to etch the material to be removed, thereby increasing the etching rate.

[0021] The second object of the present invention is to provide a semiconductor process equipment to solve the technical problem that the dry etching process provided by the related art has poor uniformity from top to bottom when forming a high aspect ratio structure.

[0022] The semiconductor process equipment provided by the present invention includes a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, and is characterized in that the controller includes at least one processor and at least one memory, and the memory stores a computer program, and when the computer program is executed by the processor, it implements the etching method of the semiconductor device as described above.

[0023] The beneficial effects brought about by the semiconductor process equipment of the present invention are:

[0024] The semiconductor device etching method mentioned above is implemented by utilizing the semiconductor process equipment. Accordingly, the semiconductor process equipment has all the technical effects that can be achieved by the semiconductor device etching method mentioned above, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0026] Figure 1 A schematic flow chart of an etching method for a semiconductor device according to an embodiment of the present invention;

[0027] Figures 2 to 3 A cross-sectional view of a device structure in each step of an etching method for a semiconductor device according to an embodiment of the present invention;

[0028] Figure 4 A microstructure diagram of a semiconductor device etched by an etching method for a semiconductor device according to an embodiment of the present invention;

[0029] Figure 5 It is a structural schematic diagram of a semiconductor process equipment provided according to an embodiment of the present invention.

[0030] Description of reference numerals:

[0031] 101-substrate; 102-mask layer; 103-hole structure;

[0032] 100-plasma; 200-semiconductor process equipment; 20-process chamber; 20A-gas inlet assembly; 20B-upper electrode assembly; 20C-lower electrode assembly; 20D-exhaust assembly;

[0033] 21 - RF coil; 22 - wafer carrier; 23 - upper RF power supply; 24 - lower RF power supply; 25 - upper matcher; 26 - lower matcher. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] like Figure 1 As shown, this embodiment provides a method for etching a semiconductor device, comprising:

[0036] Step S100: providing a semiconductor device, such as Figure 2 As described above, the semiconductor device includes a substrate 101 and a patterned mask layer 102 .

[0037] In this step, the substrate 101 is used as the material to be etched; after the mask layer 102 is patterned, it has a pattern corresponding to the structure required by the substrate 101, so that after the etching process, the pattern of the mask layer 102 can be transferred to the substrate 101 to form the required structure on the substrate 101.

[0038] Specifically, the substrate 101 may be a semiconductor material, and semiconductor materials include but are not limited to single crystal silicon, polycrystalline silicon, amorphous silicon, and silicon carbide. Specifically, in this embodiment, the substrate 101 is a silicon substrate 101. The mask layer 102 is made of silicon and oxygen, and may be a silicon-oxygen compound, more specifically, silicon dioxide.

[0039] Step S200 : controlling the semiconductor device in step S100 to enter a process chamber.

[0040] In this step, the semiconductor device having the substrate 101 and the patterned mask layer 102 is transported into the process chamber for an etching process, wherein the transport of the semiconductor device can be achieved by a robot.

[0041] Step S300: etching to form a hole structure 103 on the substrate 101, such as Figure 3As shown. The gases introduced into the process chamber include a fluorine-based gas, a dissociation-promoting gas, and a dilution gas. The dissociation-promoting gas is used to promote the dissociation of fluorine ions in the fluorine-based gas. The dissociation-promoting gas includes oxygen and nitrogen. The flow rate of oxygen is between 30 sccm and 60 sccm (inclusive), and the flow rate of nitrogen is between 40 sccm and 70 sccm (inclusive). The RF power range of the upper electrode assembly in the process chamber is 800 W to 1500 W (inclusive).

[0042] After placing a semiconductor device having a substrate 101 and a patterned mask layer 102 in a process chamber, a fluorine-based gas is introduced into the process chamber to etch the substrate 101 using fluorine ions in the fluorine-based gas to form a high-aspect-ratio pore structure 103. In particular, the introduction of a dissociation-promoting gas into the process chamber can promote the dissociation of fluorine ions in the fluorine-based gas, allowing as many fluorine ions in the fluorine-based gas as possible to be dissociated. Simultaneously, the introduction of a diluent gas can increase the mean free path of the fluorine ions, allowing the fluorine ions in the process chamber to smoothly reach the bottom of the pore structure 103, thereby reducing the difference in etching rate between the top and bottom of the pore structure 103. This ensures top-to-bottom uniformity when etching high-aspect-ratio structures, making the etching profile between word lines nearly vertical. This not only reduces the risk of current leakage caused by the formation of a "V"-shaped profile between word lines, but also reduces parasitic capacitance.

[0043] By selecting fluorine-based gas as the etching gas, it can be ensured that the etching in the above step S300 is substantially isotropic etching.

[0044] In the above-mentioned etching method, oxygen and nitrogen can weaken the bonding energy of the fluorine groups in the fluorine-based gas through collision energy transfer and electron excitation, reducing the energy required for direct dissociation. By setting the oxygen flow rate between 30 sccm and 60 sccm, not only can sufficient collision frequency be provided to promote chemical bond breakage and fluorine group dissociation, but it can also prevent the fluorine-based gas from being diluted by excessive oxygen, which would lead to a decrease in etching rate. By setting the nitrogen flow rate to be greater than the oxygen flow rate, on the one hand, the plasma impedance of the process chamber can be balanced, avoiding discharge fluctuations caused by excessive oxygen. On the other hand, the excess nitrogen can also balance the fluorine ion concentration, avoiding excessive fluorine ion consumption caused by excessive oxygen, thereby achieving a balance between oxidation and fluorination.

[0045] By setting the RF power range of the upper electrode assembly of the process chamber to 800W to 1500W, the fluorine ions in the fluorine-based gas can be more fully dissociated, so that more fluorine ions can participate in the reaction to etch the material to be removed, thereby increasing the etching rate.

[0046] In this embodiment, the aspect ratio of the hole structure 103 is greater than 10:1. In other words, the ratio of the depth to the width of the hole structure 103 formed by the etching method is greater than 10:1.

[0047] In this embodiment, the fluorine-based gas includes one or more of nitrogen trifluoride, carbon tetrafluoride and sulfur hexafluoride.

[0048] When nitrogen trifluoride is used as a fluorine-based gas to participate in etching the substrate 101, the chemical reaction between it and the substrate 101 can be:

[0049] 4NF3 + Si → SiF4↑+ 2N2↑ (1)

[0050] When nitrogen trifluoride is used as the main etching gas, the generation of carbon-containing polymers can be reduced, thus preventing the etching reaction from being hindered, thereby facilitating rapid etching of the substrate 101 and increasing the etching rate. Furthermore, the nitrogen gas generated as a byproduct during the etching process can be further used as a dissociation-promoting gas to promote the dissociation of fluorine in the fluorine-based gas.

[0051] When carbon tetrafluoride is used as a fluorine-based gas to participate in etching the substrate 101, the chemical reaction between it and the substrate 101 can be:

[0052] CF4+Si→SiF4↑+C(2)

[0053] When carbon tetrafluoride is used as the main etching gas, by-product carbon can be generated and deposited on the sidewalls of the hole structure 103 to protect the sidewalls.

[0054] When sulfur hexafluoride is used as a fluorine-based gas to participate in etching the substrate 101, the chemical reaction between sulfur hexafluoride and the substrate 101 may be:

[0055] SF6+Si→SiF4↑+S(3)

[0056] S + 2SF6 → 3SF4↑ (4)

[0057] When sulfur hexafluoride is used as the main etching gas, silicon tetrafluoride gas and intermediate sulfur are first generated. The silicon tetrafluoride gas is used to remove by-products to achieve etching of the substrate 101; the intermediate sulfur further reacts with sulfur hexafluoride to generate sulfur tetrafluoride gas.

[0058] As can be seen, the fluorine-based gases can react with the substrate 101, converting the silicon substrate 101 into gaseous SiF4 and removing it, thereby achieving the etching purpose. The gaseous SiF4 is eventually pumped away and sent to the fab system for processing.

[0059] Specifically, in this embodiment, the fluorine-based gas involved in etching the substrate 101 is one of nitrogen trifluoride, carbon tetrafluoride and sulfur hexafluoride.

[0060] In this embodiment, the flow rate of the fluorine-based gas is between 17 sccm and 25 sccm (both inclusive).

[0061] In practical applications, by controlling the flow rate of the fluorine-based gas within the above range, on the one hand, it is possible to avoid a situation where the etching rate of the substrate 101 is too low due to a too low flow rate of the fluorine-based gas; on the other hand, it is possible to avoid a situation where the selectivity of the mask layer 102 is reduced due to an excessive flow rate of the fluorine-based gas, resulting in insufficient etching of the substrate 101.

[0062] In this embodiment, the dilution gas includes helium, wherein the flow rate of the helium is between 1200 sccm and 1700 sccm (including the end points).

[0063] By allowing a large flow of helium to enter the process chamber, the helium can quickly fill the process chamber and flow in the process chamber to carry the dissociated fluorine ions to the bottom of the pore structure 103, thereby etching the bottom of the pore structure 103 instead of just etching the top of the pore structure 103.

[0064] In this embodiment, the pressure of the process chamber is between 150 mTorr and 250 mTorr (both inclusive). A lower pressure can maximize the mean free path of fluoride ions, so that the fluoride ions can reach the bottom of the pore structure 103 more smoothly.

[0065] In this embodiment, the etching time is maintained between 16 seconds and 25 seconds. By controlling the etching time within this range, it is possible to ensure that the fluorine ions in the fluorine-based gas fully etch the substrate 101 and also prevent over-etching.

[0066] Figure 4 The microstructure of the semiconductor device obtained by etching using the above-mentioned semiconductor device etching method is shown, and some of the key dimensions are represented by data. Figure 4 As shown, in this semiconductor device, at a position 10nm from the substrate 101 to its top surface, the critical dimension of the word line is 9.46nm; at a position 30nm from the substrate 101 to its top surface, the critical dimension of the word line is 14.16nm; and at a position 165nm from the substrate 101 to its top surface, the critical dimension of the word line is 15.58nm. This shows that when using the above etching method to form a high-aspect-ratio word line structure, the width difference from the top to the bottom of the word line is small, and the uniformity from top to bottom is good.

[0067] Please continue to refer to Figure 4The distance between the upper surface of the substrate 101 and the bottom of the hole structure 103 is 174.38 nm; the thickness of the remaining mask layer 102 is 6.17 nm.

[0068] As a specific embodiment of the present application, after a semiconductor device having a substrate 101 and a patterned mask layer 102 is introduced into a process chamber, a mixture of nitrogen trifluoride, oxygen, nitrogen, and helium can be introduced into the process chamber. The RF power of the upper electrode assembly is adjusted to 1000 W, and the pressure of the process chamber is adjusted to 200 mTorr to generate plasma. Simultaneously, the etching time is controlled to 20 seconds. The flow rate of nitrogen trifluoride is 20 sccm, the flow rate of oxygen is 50 sccm, the flow rate of nitrogen is 50 sccm, and the flow rate of helium is 1500 sccm.

[0069] like Figure 5 As shown, this embodiment also provides a semiconductor process equipment 200, including a process chamber 20, an air inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C and a controller, wherein the controller includes at least one processor and at least one memory, and a computer program is stored in the memory. When the computer program is executed by the processor, the etching method of the semiconductor device as described above is implemented.

[0070] For example, the controller can be either a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the exhaust assembly 20D to exhaust the interior of the process chamber 20, for example, by controlling the valve opening of the exhaust assembly 20D or the speed of the exhaust pump, thereby controlling the pressure inside the process chamber 20 and exhausting reaction byproducts.

[0071] The upper electrode assembly 20B may include an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide RF power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0072] The lower electrode assembly 20C may include a wafer carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide RF power to the wafer carrier 22 via the lower matcher 26 to provide an RF bias. The wafer carrier 22 may be an electrostatic chuck, a mechanical chuck, or a vacuum chuck.

[0073] The semiconductor process equipment 200 in the embodiment of the present application may be an inductively coupled plasma device or a capacitively coupled plasma device. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0074] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

[0075] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0076] In the above embodiments, the descriptions of directions such as “upper” and “lower” are all based on the drawings.

[0077] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for etching a semiconductor device, characterized in that: include: Providing a semiconductor device, the semiconductor device comprising a substrate and a patterned mask layer; Controlling the semiconductor device to enter the process chamber; Etching to form a pore structure on the substrate, wherein the gas introduced into the process chamber includes a fluorine-based gas, a dissociation-promoting gas, and a dilution gas, the dissociation-promoting gas is used to promote the dissociation of fluorine ions in the fluorine-based gas, the dissociation-promoting gas includes oxygen and nitrogen, the flow rate of the oxygen is between 30 sccm and 60 sccm, and the flow rate of the nitrogen is between 40 sccm and 70 sccm; The radio frequency power range of the upper electrode assembly of the process chamber is 800W to 1500W.

2. The etching method of a semiconductor device according to claim 1, wherein: The fluorine-based gas includes one or more of nitrogen trifluoride, carbon tetrafluoride and sulfur hexafluoride.

3. The etching method of a semiconductor device according to claim 1, wherein: The flow rate of the fluorine-based gas is between 17 sccm and 25 sccm.

4. The etching method of a semiconductor device according to claim 1, wherein: The dilution gas includes helium, and the flow rate of the helium is between 1200 sccm and 1700 sccm.

5. The etching method of a semiconductor device according to claim 1, wherein: The pressure of the process chamber is between 150 mTorr and 250 mTorr.

6. The etching method of a semiconductor device according to claim 1, wherein: The etching is maintained for a time between 16s and 25s.

7. The etching method of a semiconductor device according to claim 1, wherein: The substrate is made of silicon.

8. The etching method of a semiconductor device according to claim 1, wherein: The mask layer is made of silicon oxide.

9. The etching method of a semiconductor device according to claim 1, wherein: The aspect ratio of the hole structure is greater than 10:

1.

10. A semiconductor process equipment comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the etching method of the semiconductor device according to any one of claims 1 to 9 is implemented.

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