Transistor device

Abstract

The present disclosure provides a transistor device including a semiconductor stack including a drift layer having a first conductivity type, a first doped region over the drift layer and having the first conductivity type, and a second doped region over the drift layer and having a second conductivity type, wherein the depth of the second doped region is greater than that of the first doped region. The transistor device includes a trench gate embedded in the semiconductor stack and interposed between the first doped region and the second doped region. The trench gate has a hexagonal structure in a cross-sectional view, wherein a plurality of sides of the hexagonal structure includes a first side parallel to a top surface of the semiconductor stack, a second side connected to the first side and contacting the first doped region, and a third side connected to the second side and contacting the drift layer. The trench gate contacts the doped region and the drift layer with different edges of the hexagonal structure respectively, so that the resistance of the doped region and the drift layer can be reduced, and the on resistance of the transistor device is reduced.

Description

Technical Field

[0001] The present disclosure relates to transistor devices, and in particular to transistor devices including trench gates. Background Art

[0002] To meet the demand for faster processing systems and higher performance, the semiconductor industry continues to increase the current of transistor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), to increase the power conversion efficiency of the devices. In transistor devices, the magnitude of the current is affected by the overall on-state resistance (Ron), where the on-state resistance depends on multiple resistance values, such as drift resistance, channel resistance, and contact resistance. As the size of transistor devices continues to shrink, these resistance values ​​tend to increase, resulting in a limited reduction in the on-state resistance. In order to meet the current development trends in the semiconductor field, it is necessary to overcome the above problems to improve the performance of semiconductor devices. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a transistor device includes a semiconductor stack and a trench gate embedded in the semiconductor stack. The semiconductor stack includes a drift layer located above a substrate and having a first conductivity type, a first doped region located above the drift layer and having the first conductivity type, and a second doped region located above the drift layer and having a second conductivity type different from the first conductivity type. The depth of the second doped region is greater than the depth of the first doped region. The trench gate is interposed between the first doped region and the second doped region. The trench gate has a hexagonal structure in a cross-sectional view, wherein the multiple sides of the hexagonal structure include a first side parallel to the top surface of the semiconductor stack, a second side connected to the first side and contacting the first doped region, and a third side connected to the second side and contacting the drift layer.

[0004] In some embodiments, the cross-sectional view includes a trench gate, a first doped region, a second doped region, a source contact above the first doped region, and a drain contact below the substrate.

[0005] In some embodiments, a width of a top surface of the first doped region is greater than a width of a bottom surface of the first doped region.

[0006] In some embodiments, the transistor device further includes a base region between the drift layer and the first doped region, wherein the base region has the second conductivity type, and the second side of the hexagonal structure contacts the base region.

[0007] In some embodiments, the drift layer has a gradually widening profile from the bottom surface of the base region toward the substrate.

[0008] In some embodiments, a first side and a second side of the hexagonal structure in a cross-sectional view intersect with a top surface of the first doped region, and a second side and a third side of the hexagonal structure intersect with a bottom surface of the base region.

[0009] In some embodiments, the transistor device further includes a source contact overlying the first doped region and the second doped region, wherein the first side of the hexagonal structure directly contacts the source contact.

[0010] In some embodiments, the multiple sides of the hexagonal structure include a fourth side connected to the third side and parallel to the first side, a fifth side connected to the fourth side and contacting the second doped region, and a sixth side connected to the fifth side and contacting the second doped region, wherein the fourth side contacts the drift layer.

[0011] In some embodiments, the second side and the third side of the hexagonal structure in the cross-sectional view intersect with the interface formed by the base region and the drift layer, and the third side and the fourth side of the hexagonal structure intersect in the drift layer.

[0012] In some embodiments, the trench gate includes a gate electrode layer and a gate dielectric layer conformally surrounding the gate electrode layer.

[0013] According to an embodiment of the present disclosure, the trench gate in the transistor device has a hexagonal structure, and the trench gate contacts the first doped region and the drift layer with different sides of the hexagonal structure, thereby reducing the contact resistance of the first doped region and the drift resistance in the drift layer, thereby reducing the on-resistance of the transistor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0015] Figure 1 A cross-sectional view of a transistor device according to some embodiments of the present disclosure is shown.

[0016] Figures 2A to 2E Cross-sectional views illustrating various stages of fabricating a trench gate according to some embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0017] In order to implement the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. In the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, for the purpose of simplicity and clarity, the present disclosure may repeat reference numbers and / or letters in various examples, but does not indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe one element or feature in relation to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] The present disclosure provides a transistor device including a trench gate embedded in a semiconductor stack. The trench gate has a hexagonal structure in a cross-sectional view, with different sides of the hexagonal structure contacting a first doped region and a drift layer in the semiconductor stack, respectively. This reduces the contact resistance of the first doped region and the drift resistance in the drift layer, thereby reducing the on-resistance of the transistor device.

[0020] According to some embodiments of the present disclosure, Figure 1 A cross-sectional view of a transistor device 100 is shown. The transistor device 100 includes a substrate 110, a drift layer 120, a base region 130, a first doped region 140, and a second doped region 150, forming a semiconductor stack 200. The transistor device 100 also includes a trench gate 160 embedded in the semiconductor stack 200, and a source contact 170 and a drain contact 180 located on opposite sides of the semiconductor stack 200. The source contact 170 overlies the first doped region 140 and the second doped region 150, while the drain contact 180 is located below the substrate 110, thereby forming a vertical conductive path in the transistor device 100.

[0021] Specifically, the substrate 110 may include an elemental semiconductor material, a compound semiconductor material, or a base material suitable for the semiconductor stack 200, such as silicon (Si), silicon carbide (SiC), silicon germanium (SiGe), or the like. The drift layer 120 is located above the substrate 110 and may include the same or a different base material as the substrate 110. For example, in the example where the substrate 110 is a silicon substrate, the drift layer 120 may be a silicon layer or a silicon carbide layer doped with a first conductivity type dopant, such as nitrogen (N), phosphorus (P), arsenic (As), or other n-type dopants.

[0022] The base region 130 is located above the drift layer 120, and the first doped region 140 is located above the base region 130. In other words, the base region 130 is sandwiched between the first doped region 140 and the drift layer 120. In some embodiments, the first doped region 140 can be formed directly on the base region 130, such that the top surface of the base region 130 directly contacts the bottom surface of the first doped region 140. The base region 130 and the first doped region 140 can include the same base material as the drift layer 120, but have different doping characteristics than the drift layer 120.

[0023] For example, when the drift layer 120 includes a first conductivity type dopant, the base region 130 includes a second conductivity type dopant, where the second conductivity type is different from the first conductivity type. The first doped region 140 includes the first conductivity type dopant, but the doping concentration of the first doped region 140 is higher than the doping concentration of the drift layer 120. The doping concentration of the first doped region 140 may also be higher than the doping concentration of the base region 130. In an example where the drift layer 120 is a silicon carbide layer with an n-type dopant, the base region 130 may be a silicon carbide layer doped with boron (B), gallium (Ga), or other p-type dopants, while the first doped region 140 may be a silicon carbide layer doped with an n-type dopant and have a higher doping concentration than the drift layer 120.

[0024] The second doped region 150 is located above the drift layer 120, and the trench gate 160 is interposed between the first doped region 140 and the second doped region 150. The depth of the second doped region 150 can be greater than the depth of the first doped region 140, so that the distance between the bottom surface of the second doped region 150 and the top surface of the semiconductor stack 200 is greater than the distance between the bottom surface of the first doped region 140 and the top surface of the semiconductor stack 200.

[0025] The second doped region 150 may include the same base material as the drift layer 120, but the second doped region 150 has a different conductivity type than the drift layer 120, and the second doped region 150 has a higher doping concentration than the drift layer 120. The doping concentration of the second doped region 150 may also be higher than the doping concentration of the base region 130. In an example where the drift layer 120 is a silicon carbide layer having an n-type dopant, the second doped region 150 may be a silicon carbide layer having a p-type dopant and have a higher doping concentration than the drift layer 120.

[0026] The trench gate 160 extends into the drift layer 120 between the first doped region 140 and the second doped region 150, so that the trench gate 160 is embedded in the semiconductor stack 200. In a cross-sectional view (e.g., FIG. 1 ) including the trench gate 160, the first doped region 140, the second doped region 150, the source contact 170, and the drain contact 180, FIG. Figure 1 ), the trench gate 160 has a hexagonal structure, wherein at least one edge of the hexagonal structure is parallel to the top surface of the semiconductor stack 200. In some embodiments where the semiconductor stack 200 exposes the trench gate 160, at least one edge of the trench gate 160 parallel to the top surface of the semiconductor stack 200 may be flush with the top surface of the semiconductor stack 200.

[0027] More specifically, trench gate 160 includes a first side 160-1, a second side 160-2 connected to first side 160-1, a third side 160-3 connected to second side 160-2, a fourth side 160-4 connected to third side 160-3, a fifth side 160-5 connected to fourth side 160-4, and a sixth side 160-6 connected to fifth side 160-5. The other end of sixth side 160-6 is connected to first side 160-1. In other words, first side 160-1 to sixth side 160-6 are arranged in sequence to form a hexagonal structure of trench gate 160.

[0028] The first side 160-1 is parallel to the top surface of the semiconductor stack 200, and the trench gate 160 extends from the first side 160-1 into the semiconductor stack 200. In some embodiments where the first doped region 140 and the second doped region 150 are the topmost layers of the semiconductor stack 200, the first side 160-1 may be flush with the top surfaces of the first doped region 140 and the second doped region 150. When the source contact 170 overlies the semiconductor stack 200 and directly contacts the first doped region 140 and the second doped region 150, the first side 160-1 may directly contact the source contact 170.

[0029] Second edge 160-2 connects first edge 160-1 and third edge 160-3, and second edge 160-2 contacts base region 130 and first doped region 140. In some embodiments, second edge 160-2 may directly contact the sidewalls of base region 130 and first doped region 140. Second edge 160-2 forms an obtuse angle with first edge 160-1, and thus, compared to first edge 160-1, which is parallel to the top surface of semiconductor stack 200, second edge 160-2 may be referred to as a tilted edge. Because second edge 160-2 contacts first doped region 140 at an oblique angle, the width of the top surface of first doped region 140 may be greater than the width of the bottom surface of first doped region 140, thereby increasing the contact area between first doped region 140 and source contact 170. This reduces the contact resistance between first doped region 140 and source contact 170, thereby reducing the overall on-resistance of transistor device 100.

[0030] Furthermore, the second side 160 - 2 contacts the base region 130 in an oblique manner, such that an effective channel length is increased between the second side 160 - 2 and the base region 130 . Therefore, the thickness and doping concentration of the base region 130 can be flexibly adjusted to meet the requirements of the transistor device 100 .

[0031] The third side 160-3 connects the second side 160-2 and the fourth side 160-4, and the third side 160-3 contacts the drift layer 120. In some embodiments, the third side 160-3 may directly contact the drift layer 120. The fourth side 160-4 connects the third side 160-3 and the fifth side 160-5, and the fourth side 160-4 may be parallel to the first side 160-1. Similar to the relationship between the second side 160-2 and the first side 160-1, the third side 160-3 and the fourth side 160-4 form an obtuse angle, and thus the third side 160-3 can be referred to as a hypotenuse compared to the fourth side 160-4. Because the third side 160-3 contacts the drift layer 120 in a hypotenuse manner, the drift layer 120 has a gradually widening profile from the bottom surface of the base region 130 toward the substrate 110, thereby increasing the spreading area in the drift layer 120. This can reduce the drift resistance in the drift layer 120 , so that the overall on-resistance of the transistor device 100 is correspondingly reduced.

[0032] Fifth side 160-5 connects fourth side 160-4 and sixth side 160-6, and fifth side 160-5 may be parallel to second side 160-2. Sixth side 160-6 connects fifth side 160-5 and first side 160-1, and sixth side 160-6 may be parallel to third side 160-3. In some embodiments, a portion of fourth side 160-4 adjacent to third side 160-3 may contact drift layer 120, while another portion of fourth side 160-4 adjacent to fifth side 160-5, fifth side 160-5, and sixth side 160-6 may contact second doped region 150. In the above embodiment, a portion of trench gate 160 adjacent to fifth side 160-5 and sixth side 160-6 may be embedded in second doped region 150.

[0033] The trench gate 160 generally has a convex hexagonal structure, such that any two adjacent sides of the hexagonal structure form an obtuse angle. Depending on the configuration of the semiconductor stack, the trench gate 160 can have different convex hexagonal structures, including but not limited to a regular hexagon with equal sides and equal angles, or a narrow hexagon with the second side 160-2 and the third side 160-3 being larger than the first side 160-1.

[0034] In some embodiments, the hexagonal structure of the trench gate 160 may correspond to the location of the doped regions in the semiconductor stack 200. For example, Figure 1 In the cross-sectional view of FIG, the first side 160-1 and the second side 160-2 may intersect with the top surface of the first doped region 140, and the second side 160-2 and the third side 160-3 may intersect with the bottom surface of the substrate region 130, so that the second side 160-2 is in entirety in contact with the substrate region 130 and the first doped region 140. Similarly, the second side 160-2 and the third side 160-3 may intersect with the interface formed by the substrate region 130 and the drift layer 120, and the third side 160-3 and the fourth side 160-4 may intersect in the drift layer 120, so that the third side 160-3 is in entirety in contact with the drift layer 120. The first side 160 - 1 and the second side 160 - 2 may intersect the top surface of the first doped region 140 , and the first side 160 - 1 and the sixth side 160 - 6 may intersect the top surface of the second doped region 150 , so that the first side 160 - 1 entirely contacts the bottom surface of the source contact 170 .

[0035] The trench gate 160 may include a gate electrode layer 162 and a gate dielectric layer 164. Specifically, the gate electrode layer 162 includes a conductive material extending into the drift layer 120 to control a conductive path in the transistor device 100. For example, the gate electrode layer 162 may include polysilicon, a metal nitride, a metal silicide, a metal oxide, a single metal, an alloy, combinations thereof, or the like. The gate dielectric layer 164 surrounds the gate electrode layer 162 to isolate the gate electrode layer 162 from the semiconductor stack 200. The gate dielectric layer 164 may include an oxide such as silicon oxide, a nitride such as silicon nitride, a composite structure (e.g., a stack of oxide / nitride / oxide), combinations thereof, or the like.

[0036] like Figure 1 As shown in FIG, the gate dielectric layer 164 conformally surrounds the gate electrode layer 162 to cover all surfaces of the gate electrode layer 162. As a result, the gate electrode layer 162 has a hexagonal structure that is a scaled-down version of the trench gate 160, while the gate dielectric layer 164 has a hexagonal ring structure. Because the hexagonal ring structure of the gate dielectric layer 164 is close to a circular ring, the reliability of the gate dielectric layer 164 can be improved. In some embodiments, the gate dielectric layer 164 can have a uniform thickness, so that each side of the gate dielectric layer 164 has an equal shortest distance from a corresponding side of the gate electrode layer 162.

[0037] It is worth noting that in some embodiments where the trench gate 160 directly contacts the source contact 170, a portion of the gate dielectric layer 164 (eg Figure 1 A gate dielectric layer 164 (located adjacent to the first side 160-1) is located between the gate electrode layer 162 and the source contact 170 to isolate the gate electrode layer 162 from the source contact 170 and prevent short circuits. The gate dielectric layer 164 may include an opening in the region not covered by the source contact 170 to expose the gate electrode layer 162, allowing the gate contact to connect to the gate electrode layer 162.

[0038] According to some embodiments of the present disclosure, Figures 2A to 2E The cross-sectional views of the multiple stages of manufacturing the trench gate are shown to exemplify the method of manufacturing the trench gate. Figures 2A to 2E The steps shown are simplified. Figures 2A to 2E However, those skilled in the art will appreciate that Figures 2A to 2E The method shown can be used to form transistor devices including hexagonal trench gates within the scope of the present disclosure, such as Figure 1 transistor device 100 .

[0039] refer to Figures 2A to 2B The method for manufacturing a trench gate may begin by forming a hexagonal trench 202o in the semiconductor stack 200. For example, Figure 2A As shown, a mask 210 may be formed on the semiconductor stack 200, wherein the mask 210 includes an opening 210o that exposes the semiconductor stack 200. After the mask 210 is formed, a first etching process is performed on the semiconductor stack 200 through the opening 210o to form a rectangular trench 200o in the semiconductor stack 200. Figure 2B A second etching process is performed on the semiconductor stack 200 through the opening 210o to expand the trench 200o into a hexagonal trench 202o. The extended plane (shown as a dotted line 220) of the interface formed by the mask 210 and the semiconductor stack 200 is considered to be one side of the hexagonal trench 202o, and the exposed surface of the semiconductor stack 200 in the trench 202o is considered to be the remaining five sides of the hexagonal trench 202o.

[0040] In some embodiments, the first etching process and the second etching process may be anisotropic etching processes using the same etchant, such as a dry etching process using plasma or the like. After the second etching process is completed, the trench 202o will serve as a space for subsequently accommodating the trench gate, so the trench 202o may have an appropriate depth to expose the drift layer (e.g., Figure 1 The drift layer 120 is exposed in the embodiment of the present invention, but the substrate below the drift layer is not exposed.

[0041] refer to Figure 2C A first portion 166 of the gate dielectric layer 164 is formed in the trench 202o, where the first portion 166 covers the exposed surface of the semiconductor stack 200 in the trench 202o and does not completely fill the trench 202o. The first portion 166 conformally covers the exposed surface in the trench 202o, forming five sides of the hexagonal structure of the gate dielectric layer 164. For example, a wet oxidation process can be performed on the semiconductor stack 200 exposed by the trench 202o, thereby forming an oxide layer growing from the bottom surface and four side surfaces of the trench 202o to form the first portion 166.

[0042] The first portion 166 may include two exposed edges 167 connected to the sidewalls of the mask 210. Since the first portion 166 conforms to the exposed surface of the semiconductor stack 200 in the trench 202o, the trench 202o remaining on the first portion 166 and below the edges 167 may have a hexagonal structure. Figure 2CAs shown, the shortest connecting line (shown as a dashed line 230) between the two edges 167 is considered to be one side of the hexagonal groove 202o, and the other exposed surfaces of the first portion 166 in the groove 202o are considered to be the remaining five sides of the hexagonal groove 202o. In some embodiments, the two edges 167 may be non-parallel to the sidewalls of the mask 210, such that the length of the shortest connecting line between the two edges 167 is less than the width of the opening 210o, and the length of the shortest connecting line is greater than 0, thereby keeping the two edges 167 separated.

[0043] refer to Figure 2D , a gate electrode layer 162 is formed in the trench 202o, covering the first portion 166. For example, a conductive material may be first deposited in the remaining space of the trench 202o, such that the top surface of the conductive material is flush with or higher than the interface formed by the mask 210 and the semiconductor stack 200 (i.e., the location of the dotted line 220). Next, the conductive material is etched back to form the gate electrode layer 162, such that the top surface of the gate electrode layer 162 is lower than the interface formed by the mask 210 and the semiconductor stack 200. Because the trench 202o remaining on the first portion 166 has a hexagonal structure, the gate electrode layer 162 deposited on the first portion 166 also has a hexagonal structure.

[0044] refer to Figure 2E A second portion 168 of the gate dielectric layer 164 is formed on the gate electrode layer 162, such that the gate dielectric layer 164 surrounds the gate electrode layer 162 to form the trench gate 160. For example, an oxide can be deposited on the gate electrode layer 162 using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition methods to form the second portion 168 covering the gate electrode layer 162 and directly contacting the first portion 166. After depositing the second portion 168, the first portion 166, the second portion 168, and the gate electrode layer 162 can completely fill the trench 202o, resulting in the trench gate 160 having a hexagonal structure. The top surface of the second portion 168 can be flush with or lower than the interface formed by the mask 210 and the semiconductor stack 200, such that the trench gate 160 is embedded in the semiconductor stack 200.

[0045] In some embodiments, the first portion 166 and the second portion 168 may be formed of the same material using different process steps, such that a subtle or no observable interface exists between the first portion 166 and the second portion 168. For example, the first portion 166 may be formed of silicon oxide using a wet oxidation process, and the second portion 168 may be formed of silicon oxide using a chemical vapor deposition process. The separately formed first portion 166 and second portion 168 may have the same thickness, thereby forming a gate dielectric layer 164 that uniformly surrounds the gate electrode layer 162.

[0046] According to the above embodiment, the transistor device disclosed herein includes a trench gate having a hexagonal structure embedded in a semiconductor stack. The first doped region contacts the second side of the hexagonal structure, thereby increasing the contact area between the first doped region and the source contact, thereby reducing the contact resistance of the first doped region. The drift layer contacts the third side of the hexagonal structure and has a gradually widening profile, thereby reducing the drift resistance of the drift layer. Therefore, the hexagonal trench gate can reduce the overall on-resistance of the transistor device, thereby improving the performance of the transistor device.

[0047] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

[0048]

Explanation of symbols

[0049] 100: Transistor device

[0050] 110:Substrate

[0051] 120: Drift layer

[0052] 130: Base area

[0053] 140: first doped region

[0054] 150: second doped region

[0055] 160: Trench gate

[0056] 160-1: First side

[0057] 160-2: Second side

[0058] 160-3: The third side

[0059] 160-4: The fourth side

[0060] 160-5: The Fifth Side

[0061] 160-6: The Sixth Side

[0062] 162: Gate electrode layer

[0063] 164: Gate dielectric layer

[0064] 166: Part 1

[0065] 167: Edge

[0066] 168: Part 2

[0067] 170: Source contact

[0068] 180: Drain contact

[0069] 200:Semiconductor stacking

[0070] 200o, 202o: groove

[0071] 210:Mask

[0072] 210°: Opening

[0073] 220,230: dotted line.

Claims

1. A transistor device, characterized in that: include: Semiconductor stacks, including: a drift layer located above the substrate and having a first conductivity type; a first doped region located above the drift layer and having the first conductivity type; and a second doped region located above the drift layer and having a second conductivity type different from the first conductivity type, wherein a depth of the second doped region is greater than a depth of the first doped region; and A trench gate is embedded in the semiconductor stack, wherein the trench gate is interposed between the first doped region and the second doped region, The trench gate has a hexagonal structure in a cross-sectional view, and the multiple sides of the hexagonal structure include: a first side parallel to the top surface of the semiconductor stack; a second side connected to the first side and contacting the first doped region; and The third side is connected to the second side and contacts the drift layer. 2 . The transistor device according to claim 1 , wherein the cross-sectional view includes the trench gate, the first doped region, the second doped region, a source contact above the first doped region, and a drain contact below the substrate. 3 . The transistor device of claim 1 , wherein a width of a top surface of the first doped region is greater than a width of a bottom surface of the first doped region.

4. The transistor device according to claim 1 , further comprising: The base region is located between the drift layer and the first doped region, wherein the base region has the second conductivity type, and the second side of the hexagonal structure contacts the base region. The transistor device according to claim 4 , wherein the drift layer has a gradually widening profile from a bottom surface of the base region toward the substrate. 6 . The transistor device according to claim 4 , wherein in the cross-sectional view, the first side and the second side of the hexagonal structure intersect with the top surface of the first doped region, and the second side and the third side of the hexagonal structure intersect with the bottom surface of the base region.

7. The transistor device according to claim 1, wherein Further including: A source contact covers the first doped region and the second doped region, wherein the first side of the hexagonal structure directly contacts the source contact.

8. The transistor device according to claim 1 , wherein the plurality of sides of the hexagonal structure comprise: a fourth side connected to the third side and parallel to the first side, wherein the fourth side contacts the drift layer; a fifth side connected to the fourth side and contacting the second doped region; and The sixth side is connected to the fifth side and contacts the second doped region. 9 . The transistor device according to claim 8 , wherein in the cross-sectional view, the second side and the third side of the hexagonal structure intersect with an interface formed by the base region and the drift layer, and the third side and the fourth side of the hexagonal structure intersect in the drift layer.

10. The transistor device according to claim 1, wherein the trench gate comprises: a gate electrode layer; as well as The gate dielectric layer conformally surrounds the gate electrode layer.

Images