Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a silicon carbide substrate, a silicon carbide buffer layer and an epitaxial layer. The silicon carbide buffer layer is disposed on the silicon carbide substrate. The epitaxial layer is disposed on the silicon carbide buffer layer, wherein the ratio of the number of moles of carbon to the number of moles of silicon in the silicon carbide buffer layer is gradually increased along the direction from the silicon carbide substrate to the epitaxial layer. The silicon carbide buffer layer with the ratio of the carbon mole number to the silicon mole number (C / Si Ratio) in gradient change is formed before the epitaxial layer is formed, so that the conversion efficiency of converting BPD into TED in the subsequent silicon carbide epitaxial growth process can be improved, and the epitaxial quality is further improved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Silicon carbide (SiC) is a special semiconductor material with characteristics such as wide bandwidth, high critical breakdown electric field, high thermal conductivity, and high carrier saturation drift velocity. It is suitable for the manufacture of high-temperature, high-voltage, high-power, and radiation-resistant semiconductor devices. Although SiC materials have many advantages, there are often a large number of defects in SiC materials, such as basal plane dislocations (BPDs). These defects will further extend from the substrate to the epitaxial layer, causing the reverse leakage current of the semiconductor device to increase or the breakdown voltage to decrease, resulting in reduced reliability of the semiconductor device. Compared with BPDs, threading edge dislocations (TEDs) have less impact on the performance of semiconductor devices. Therefore, how to increase the ratio of BPDs converted to TEDs during SiC epitaxial growth and prevent BPDs in the substrate from extending into the epitaxial layer is very important for improving the performance of semiconductor devices. Summary of the Invention

[0003] According to one or more embodiments of the present disclosure, a semiconductor structure includes a silicon carbide substrate, a silicon carbide buffer layer, and an epitaxial layer. The silicon carbide buffer layer is disposed on the silicon carbide substrate. The epitaxial layer is disposed on the silicon carbide buffer layer, wherein the ratio of molar carbon to molar silicon in the silicon carbide buffer layer increases gradually along the direction from the silicon carbide substrate to the epitaxial layer.

[0004] In one or more embodiments of the present disclosure, the doping concentration of the silicon carbide buffer layer decreases gradually along the direction from the silicon carbide substrate to the epitaxial layer.

[0005] In one or more embodiments of the present disclosure, the centerline average roughness of the silicon carbide buffer layer decreases gradually along a direction from the silicon carbide substrate to the epitaxial layer.

[0006] In one or more embodiments of the present disclosure, the thickness of the silicon carbide buffer layer is 0.5 micrometers to 3.0 micrometers.

[0007] According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: placing a silicon carbide substrate in a reaction chamber and setting an initial temperature of the reaction chamber; introducing a growth source and a doping source into the reaction chamber, wherein the growth source includes a carbon source and a silicon source, and the doping source includes a nitrogen source; continuously introducing the growth source and the doping source at an operating temperature to form a silicon carbide buffer layer, wherein during the formation of the silicon carbide buffer layer, the operating temperature gradually decreases with the initial temperature as the starting value.

[0008] In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor structure further includes: continuously introducing a growth source and a doping source at an epitaxial temperature to form an epitaxial layer on the silicon carbide buffer layer, wherein the epitaxial temperature is less than or equal to the operating temperature.

[0009] In one or more embodiments of the present disclosure, during the formation of the silicon carbide buffer layer, the ratio of the carbon mole number to the silicon mole number in the growth source is gradually increased.

[0010] In one or more embodiments of the present disclosure, during the formation of the silicon carbide buffer layer, the concentration of the dopant source supplied is gradually reduced.

[0011] According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a first silicon carbide buffer layer on a silicon carbide substrate at a first temperature; and forming a second silicon carbide buffer layer on the first silicon carbide buffer layer at a second temperature, wherein the second temperature is lower than the first temperature.

[0012] In one or more embodiments of the present disclosure, the centerline average roughness of the second silicon carbide buffer layer is less than the root mean square roughness of the first silicon carbide buffer layer.

[0013] According to the above-mentioned embodiment of the present disclosure, by forming a silicon carbide buffer layer with a gradient carbon molar ratio to silicon molar ratio (C / Si Ratio) before forming the epitaxial layer, the conversion efficiency of BPD to TED during the subsequent silicon carbide epitaxial growth process can be improved, thereby improving the epitaxial quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying drawings are described as follows:

[0015] Figure 1 is a schematic side view of a semiconductor structure according to some embodiments of the present disclosure; and

[0016] Figure 2 The present invention is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following drawings illustrate various embodiments of the present disclosure. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not essential and therefore should not be construed as limiting the present disclosure. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form. Furthermore, for ease of viewing, the dimensions of the components in the drawings are not drawn to scale.

[0018] It should be understood that although the terms "first," "second," and "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the "first element," "component," "region," "layer," or "portion" described below may also be referred to as a second element, component, region, layer, or portion without departing from the teachings of this document.

[0019] On the other hand, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the drawings. For example, if the device in a drawing is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in a drawing is turned over, the element described as being "lower" or "below" other elements will be oriented as being "above" the other elements. Thus, the exemplary terms "lower" or "below" can include both "lower" and "upper" orientations.

[0020] The present disclosure relates to a method for improving the reliability of a semiconductor structure. Specifically, the present disclosure improves the structure of the silicon carbide buffer layer in a gradient manner so that the ratio of the carbon molar number to the silicon molar number (C / SiRatio) of the silicon carbide buffer layer gradually increases along the direction of its stacking thickness, thereby improving the conversion efficiency of BPD to TED during the subsequent silicon carbide epitaxial growth process, thereby reducing the probability of killer defects and improving the epitaxial quality. On the other hand, the probability of large defects (e.g., triangle defects and carrot defects) during the subsequent silicon carbide epitaxial growth process can be further reduced by gradually decreasing the doping concentration of the silicon carbide buffer layer along the direction of its stacking thickness. In this way, the semiconductor structure disclosed in the present disclosure can meet the performance and reliability requirements of high-voltage and high-current electronic devices.

[0021] See also Figure 1, which is a side view schematic diagram of a semiconductor structure 100 according to some embodiments of the present disclosure. Specifically, the semiconductor structure 100 of the present disclosure includes a silicon carbide substrate 110, a silicon carbide buffer layer 120, and an epitaxial layer 130. The silicon carbide buffer layer 120 is disposed on the silicon carbide substrate 110, and the epitaxial layer 130 is disposed on the silicon carbide buffer layer 120, that is, the silicon carbide buffer layer 120 and the epitaxial layer 130 are sequentially disposed on the silicon carbide substrate 110. In other words, the silicon carbide buffer layer 120 has a first surface 121 and a second surface 123 relative to each other, and the epitaxial layer 130 and the silicon carbide substrate 110 are respectively disposed on the first surface 121 and the second surface 123 of the silicon carbide buffer layer 120. It should be understood that the silicon carbide substrate 110 of the present disclosure has a 4H-SiC crystal structure, and the present disclosure expects to perform 4H-SiC homogeneous epitaxy, and the semiconductor structure 100 of the present disclosure is an N-type semiconductor structure.

[0022] For the sake of clarity and convenience of description, the following will first describe the manufacturing method of the semiconductor structure 100, and present the structural features of the semiconductor structure 100 disclosed in the present disclosure through this manufacturing method. Figure 2 , which is a flow chart of a method for manufacturing a semiconductor structure 100 according to some embodiments of the present disclosure. Specifically, the method for manufacturing the semiconductor structure 100 includes steps S10 to S30, wherein steps S10 to S30 can be performed sequentially. After completing step S30, a silicon carbide buffer layer 120 on the silicon carbide substrate 110 is obtained.

[0023] In some embodiments, the silicon carbide substrate 110 may be etched before forming the silicon carbide buffer layer 120. In detail, the silicon carbide substrate 110 may be placed in a reaction chamber (not shown), and the reaction chamber gas may be replaced multiple times with argon gas, followed by the introduction of hydrogen into the reaction chamber, and the hydrogen flow rate is gradually increased to 250 liters / minute to 350 liters / minute, and the temperature of the reaction chamber is gradually increased to 1400 degrees Celsius to 1600 degrees Celsius. After reaching the set temperature, the silicon carbide substrate 110 is subjected to in-situ hydrogen etching for 5 minutes to 20 minutes. By etching the silicon carbide substrate 110 under high temperature conditions in advance, not only can the dust particles on the surface of the silicon carbide substrate 110 be removed, but also the effect of effectively suppressing 2D island nucleation in the early stage of epitaxy can be achieved, thereby effectively preventing the formation of unexpected 3C-SiC crystal structures.

[0024] In some embodiments, the etching step can be selectively omitted and the silicon carbide buffer layer 120 can be directly prepared. Specifically, after the silicon carbide substrate 110 is placed in the reaction chamber, the initial temperature T of the reaction chamber can be directly set. i, to prepare for forming the silicon carbide buffer layer 120, wherein the initial temperature T i The temperature may be 1620° C. to 1680° C. This step is referred to as step S10 in the present disclosure.

[0025] Then, proceed to step S20. At the initial temperature T i While maintaining the hydrogen flow, a growth source and a doping source are introduced into the reaction chamber, wherein the growth source includes a carbon source and a silicon source, and the doping source includes a nitrogen source. In some embodiments, the carbon source may include propane, ethylene, or a combination thereof, the silicon source may include monosilane, dichlorosilane, trichlorosilane, or a combination thereof, and the nitrogen source may include nitrogen, ammonia, or a combination thereof.

[0026] Then, step S30 is performed. w Under the condition of continuous introduction of growth source and doping source, a silicon carbide buffer layer 120 is formed by epitaxy. During the formation of the silicon carbide buffer layer 120, the operating temperature T w With the initial temperature T i Specifically, after step S20, the temperature of the reaction chamber is still the initial temperature T set in step S10. i At this time, hydrogen, growth source and doping source are continuously introduced into the reaction chamber for a period of time to epitaxially grow a first silicon carbide buffer layer 120a containing dopant (nitrogen) from the silicon carbide substrate 110. That is, in the initial stage of forming the silicon carbide buffer layer 120, the working temperature T w This is the initial temperature T set in step S10. i ; Then, gradually reduce the operating temperature T w , and continue to introduce hydrogen, growth source and doping source into the reaction chamber, and then continue to epitaxially grow a second silicon carbide buffer layer 120b containing dopants on the grown first silicon carbide buffer layer 120a, ..., an nth silicon carbide buffer layer 120n.

[0027] It should be understood that although Figure 1 The silicon carbide buffer layer 120 is drawn as a first silicon carbide buffer layer 120a, ..., nth silicon carbide buffer layer 120n neatly stacked on each other, but this drawing method is only for the convenience of explaining the epitaxial process and the structural features produced after epitaxial growth. Since the silicon carbide buffer layer 120 is formed by continuous epitaxial growth, the silicon carbide buffer layer 120 as a whole is actually a continuous structure without a clear interface R. However, due to process factors, the silicon carbide buffer layer 120 as a whole still has a gradient structural feature change, so the silicon carbide buffer layer 120 can still be disassembled into Figure 1The first silicon carbide buffer layer 120a, ..., nth silicon carbide buffer layer 120n have different structural properties.

[0028] Because the SiC buffer layer 120 is formed by epitaxial deposition, and a lower epitaxial deposition temperature allows the formed SiC buffer layer 120 to have a higher C / Si ratio, the gradual cooling method used to form the SiC buffer layer 120 allows the SiC buffer layer formed later and located at an upper layer (i.e., farther from the SiC substrate 110) (e.g., the nth SiC buffer layer 120n) to have a higher C / Si ratio. In other words, the top of the SiC buffer layer 120 (i.e., farther from the SiC substrate 110) has a higher C / Si ratio than the bottom of the SiC buffer layer 120 (i.e., closer to the SiC substrate 110). This design promotes lateral growth at the top of the SiC buffer layer 120 while suppressing step flow growth at the top of the SiC buffer layer 120. This improves the conversion efficiency of BPD to TED during the subsequent epitaxial growth of the silicon carbide buffer layer 120 to form the epitaxial layer 130, thereby enhancing epitaxial growth quality. Furthermore, epitaxially growing the silicon carbide buffer layer 120 using a gradual cooling method improves the conversion efficiency of BPD to TED during epitaxial growth and reduces the likelihood of other defects.

[0029] In some embodiments, the operating temperature T w Linearly decrease, that is, the operating temperature T w The relationship between the operating time (ie, the total time of forming the silicon carbide buffer layer 120) and the operating time is a linear function. w In some embodiments, the operating temperature T w The temperature is gradually reduced at a rate of 0.1°C / s to 0.4°C / s. This gentle cooling method allows for stable crystal growth and improves the conversion efficiency of BPD to TED. In some embodiments, the operating temperature T w Continue to decrease, but not lower than the epitaxial temperature T used to form the epitaxial layer 130 e For example, when the present disclosure is used to form the epitaxial layer 130 at an epitaxial temperature T e When the operating temperature T for forming the silicon carbide buffer layer 120 is 1550 degrees Celsius to 1650 degrees Celsius, during the formation of the silicon carbide buffer layer 120, the operating temperature T for forming the silicon carbide buffer layer 120 is 1550 degrees Celsius to 1650 degrees Celsius. wThe temperature may be continuously lowered to a temperature greater than or equal to 1550 degrees Celsius to 1650 degrees Celsius (eg, greater than or equal to 1550 degrees Celsius, greater than or equal to 1600 degrees Celsius, greater than or equal to 1650 degrees Celsius).

[0030] In some embodiments, during the formation of the silicon carbide buffer layer 120 (i.e., during step S30), the epitaxial growth quality can be further improved by adjusting the C / Si ratio in the growth source. Specifically, during the formation of the silicon carbide buffer layer 120, the carbon source concentration can be gradually increased, while the silicon source concentration can be correspondingly decreased, so that the overall C / Si ratio in the growth source gradually increases. In this way, the silicon carbide buffer layer formed later and located at the uppermost layer (e.g., the nth silicon carbide buffer layer 120n) can have a higher C / Si ratio, thereby promoting lateral growth at the top of the silicon carbide buffer layer 120 and suppressing step flow growth at the top of the silicon carbide buffer layer 120. This improves the conversion efficiency of BPD to TED during the subsequent formation of the epitaxial layer 130. In some embodiments, the C / Si ratio in the growth source used to form the silicon carbide buffer layer 120 continues to increase, but does not exceed the C / Si ratio in the growth source used to subsequently form the epitaxial layer 130. For example, when the C / Si ratio of the growth source used to form the epitaxial layer 130 is at least 1.3, the C / Si ratio of the growth source used to form the silicon carbide buffer layer 120 can be continuously increased to less than or equal to 1.3. Furthermore, it should be understood that the C / Si ratio of the growth source disclosed herein is measured at the gas inlet end of the reaction chamber.

[0031] In some embodiments, the C / Si ratio in the growth source is gradually increased. This helps to gradually increase the C / Si ratio of the silicon carbide buffer layer 120, further improving the epitaxial quality. In some embodiments, by gradually increasing the C / Si ratio in the growth source, stable crystal growth can be promoted, defect formation can be reduced, and the conversion efficiency of BPD to TED can be improved.

[0032] In some embodiments, during the formation of the silicon carbide buffer layer 120 (i.e., during step S30), the epitaxial quality can be further improved by adjusting the supply concentration of the doping source. Specifically, during the formation of the silicon carbide buffer layer 120, the supply concentration of the doping source can be gradually reduced. Thereby, in the early stage of forming the silicon carbide buffer layer 120, a high concentration of dopants can be used to suppress two-dimensional island nucleation, effectively preventing the formation of unexpected 3C-SiC crystal structure, and in the later stage of forming the silicon carbide buffer layer 120, a low concentration of dopants can be used to reduce the probability of generating large defects (e.g., triangle defects, carrot defects). In some embodiments, the supply concentration of the doping source can be increased from 5E18 atoms / cm3 (atom / cm 3 ) gradually decreases to 3E17 atoms / cm3. In some embodiments, the supply concentration of the dopant source used to form the silicon carbide buffer layer 120 is less than the supply concentration of the dopant source used to form the silicon carbide substrate 110, and greater than the supply concentration of the dopant source used to form the epitaxial layer 130. For example, the supply concentration of the dopant source used to form the silicon carbide substrate 110 may be approximately 1E19 atoms / cm3, and the supply concentration of the dopant source used to form the epitaxial layer 130 may be 2E15 atoms / cm3 to 2E16 atoms / cm3. It should be understood that the supply concentration of the dopant source is measured at the gas inlet end of the reaction chamber.

[0033] Generally speaking, in step S30, the pressure of the reaction chamber is 100 mbar to 200 mbar, the flow rate of the carbon source in the growth source is 300 standard cubic centimeters per minute (sccm) to 600 sccm, the flow rate of the silicon source in the growth source is 300 sccm to 500 sccm, the flow rate of the dopant source is 200 sccm to 500 sccm, and the total epitaxial growth time is 1 minute to 5 minutes. After completing step S30, a silicon carbide buffer layer 120 is obtained on the silicon carbide substrate 110.

[0034] Then, the epitaxial temperature T e The growth source and the doping source are continuously introduced to form the epitaxial layer 130 on the silicon carbide buffer layer 120. The epitaxial temperature T for forming the epitaxial layer 130 is e Less than or equal to the working temperature T for forming the silicon carbide buffer layer 120 w , and the C / Si Ratio in the growth source used to form the epitaxial layer 130 is greater than or equal to the C / Si Ratio in the growth source used to form the silicon carbide buffer layer 120. In general, the present disclosure provides a method for forming the silicon carbide buffer layer 120 by adjusting the operating temperature Tw By performing gradient control and improvement on the C / Si ratio in the growth source and the concentration of the doping source, the epitaxial quality of the epitaxial layer 130 can be effectively improved.

[0035] Please return Figure 1 After forming the epitaxial layer 130, the following can be obtained: Figure 1 The semiconductor structure 100 is shown. Based on the gradient (gradual) operating temperature T used during the formation of the silicon carbide buffer layer 120 w The silicon carbide buffer layer 120 has a gradient C / Si Ratio, wherein the C / Si Ratio of the silicon carbide buffer layer 120 gradually increases along a direction D from the silicon carbide substrate 110 to the epitaxial layer 130 (i.e., a direction D of the stacking thickness of the silicon carbide buffer layer 120). In some embodiments, the C / Si Ratio of the silicon carbide buffer layer 120 is less than the C / Si Ratio of the epitaxial layer 130. Specifically, the C / Si Ratio of the epitaxial layer 130 may be, for example, 1.3, and the C / Si Ratio of the silicon carbide buffer layer 120 may be, for example, 0.9 to 1.1, and the C / Si Ratio of the silicon carbide buffer layer 120 gradually increases along the direction D from the silicon carbide substrate 110 to the epitaxial layer 130. It should be understood that the C / Si Ratio of the silicon carbide buffer layer 120 is obtained by destructive analysis and measurement using a secondary ion mass spectrometer (SIMS).

[0036] In addition, based on the gradient working temperature T used during the formation of the silicon carbide buffer layer 120 w The structural roughness of the silicon carbide buffer layer 120 decreases gradually along the direction D from the silicon carbide substrate 110 to the epitaxial layer 130. Specifically, the lower the epitaxial temperature, the smaller the structural roughness of the formed silicon carbide buffer layer 120. Therefore, the structural roughness of the top position of the silicon carbide buffer layer 120 is smaller than that of the bottom position. Figure 1 , the structural roughness at position B in the silicon carbide buffer layer 120 is less than the structural roughness at position A in the silicon carbide buffer layer 120. The "structural roughness" disclosed herein refers specifically to the "centerline average roughness," which is measured / observed using a destructive analysis using a secondary ion mass spectrometer coupled with an atomic force microscope (AFM).

[0037] On the other hand, based on the gradient doping source supply concentration used when forming the silicon carbide buffer layer 120, the doping concentration of the silicon carbide buffer layer 120 gradually decreases along the direction D from the silicon carbide substrate 110 to the epitaxial layer 130. In some embodiments, the doping concentration of the silicon carbide buffer layer 120 is less than the doping concentration of the silicon carbide substrate 110 and greater than the doping concentration of the epitaxial layer 130. In some embodiments, the doping concentration of the silicon carbide buffer layer 120 may be 3E17 atoms / cm3 to 5E18 atoms / cm3, and gradually decreases along the direction D from the silicon carbide substrate 110 to the epitaxial layer 130. It should be understood that the doping concentration of the silicon carbide buffer layer 120 is obtained by destructive analysis and measurement using a secondary ion mass spectrometer.

[0038] In some embodiments, the thickness H1 of the silicon carbide buffer layer 120 may be 0.5 microns to 3.0 microns (e.g., 1.0 microns, 1.5 microns, 2.0 microns, 2.5 microns). Compared to the thickness of buffer layers commonly found in the art, the silicon carbide buffer layer 120 disclosed herein has a relatively large thickness H1. This design allows for more room for gradient (gradual) improvement, increasing the chances of BPDs converting to TEDs during the formation of the silicon carbide buffer layer 120. This improves the conversion efficiency of BPDs to TEDs, reduces the probability of fatal defects, and improves epitaxial quality. In some embodiments, the thickness H2 of the silicon carbide substrate 110 may be 300 microns to 400 microns (e.g., 350 microns), and the thickness H3 of the epitaxial layer may be 5.5 microns to 30 microns (e.g., 10 microns, 15 microns, 20 microns, 25 microns).

[0039] In general, the present disclosure forms a first silicon carbide buffer layer 120a on a silicon carbide substrate 110 at a first temperature, and forms a second silicon carbide buffer layer 120b on the first silicon carbide buffer layer 120a at a second temperature, wherein the second temperature is lower than the first temperature, so that the C / Si ratio of the second silicon carbide buffer layer 120b is greater than that of the first silicon carbide buffer layer 120a. Furthermore, by gradually increasing the C / Si ratio in the growth source during epitaxial growth, the C / Si ratio of the second silicon carbide buffer layer 120b can be increased relative to that of the first silicon carbide buffer layer 120a. Furthermore, by gradually decreasing the temperature during epitaxial growth, the structural roughness of the second silicon carbide buffer layer 120b can be reduced relative to that of the first silicon carbide buffer layer 120a. Furthermore, by gradually decreasing the supply concentration of the doping source, the doping concentration of the second silicon carbide buffer layer 120b can be reduced relative to that of the first silicon carbide buffer layer 120a. The above design can improve the conversion efficiency of BPD to TED and reduce the probability of large defects, thereby improving the epitaxial quality.

[0040] Although the present disclosure has been disclosed above in the form of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0041]

Explanation of symbols

[0042] 100:Semiconductor structure

[0043] 110: Silicon carbide substrate

[0044] 120: Silicon carbide buffer layer

[0045] 120a: first silicon carbide buffer layer

[0046] 120b: second silicon carbide buffer layer

[0047] 120n: nth silicon carbide buffer layer

[0048] 121: first surface

[0049] 123: Second surface

[0050] 130: epitaxial layer

[0051] R: Interface

[0052] H1,H2,H3:Thickness

[0053] D: Direction

[0054] A,B: Position

[0055] S10~S30: steps.

Claims

1. A semiconductor structure, characterized in that include: Silicon carbide substrate; a silicon carbide buffer layer, disposed on the silicon carbide substrate; as well as The epitaxial layer is disposed on the silicon carbide buffer layer, wherein the ratio of the carbon mole number to the silicon mole number of the silicon carbide buffer layer increases gradually along the direction from the silicon carbide substrate to the epitaxial layer. 2 . The semiconductor structure according to claim 1 , wherein the doping concentration of the silicon carbide buffer layer decreases gradually along a direction from the silicon carbide substrate to the epitaxial layer. 3 . The semiconductor structure according to claim 1 , wherein a centerline average roughness of the silicon carbide buffer layer decreases gradually along a direction from the silicon carbide substrate to the epitaxial layer. The semiconductor structure according to claim 1 , wherein the silicon carbide buffer layer has a thickness of 0.5 μm to 3.0 μm.

5. A method for manufacturing a semiconductor structure, characterized in that: include: placing the silicon carbide substrate into a reaction chamber and setting an initial temperature of the reaction chamber; introducing a growth source and a doping source into the reaction chamber, wherein the growth source comprises a carbon source and a silicon source, and the doping source comprises a nitrogen source; and The growth source and the doping source are continuously introduced at a working temperature to form a silicon carbide buffer layer. During the formation of the silicon carbide buffer layer, the working temperature is gradually reduced starting from the initial temperature.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: Also includes: The growth source and the doping source are continuously introduced at an epitaxial temperature to form an epitaxial layer on the silicon carbide buffer layer, wherein the epitaxial temperature is less than or equal to the operating temperature. 7 . The method for manufacturing a semiconductor structure according to claim 5 , wherein during the formation of the silicon carbide buffer layer, a ratio of carbon moles to silicon moles in the growth source is gradually increased. 8 . The method for manufacturing a semiconductor structure according to claim 5 , wherein during the formation of the silicon carbide buffer layer, the supply concentration of the doping source is gradually reduced.

9. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first silicon carbide buffer layer on the silicon carbide substrate at a first temperature; as well as A second silicon carbide buffer layer is formed on the first silicon carbide buffer layer at a second temperature, wherein the second temperature is lower than the first temperature. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein a centerline average roughness of the second silicon carbide buffer layer is smaller than a root mean square roughness of the first silicon carbide buffer layer.

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