Integrated circuit design state checking method and device, readable medium and electronic equipment
By automatically checking the simulation intermediate and result data of the integrated circuit design simulation system, the problems of low efficiency and poor accuracy of manual self-checking are solved, and efficient and accurate design verification is achieved.
Patent Information
- Application Number
- CN202510854558.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-24
- Publication Date
- 2025-09-23
AI Technical Summary
In the existing integrated circuit design and verification process, manual self-inspection is tedious and prone to missing problems, resulting in low verification efficiency and low quality.
By obtaining the simulation intermediate data and result data generated by the simulation module of the integrated circuit design simulation system, the target signal is screened out according to the list of signals to be checked, and input into the inspection module for automated inspection, thereby improving verification efficiency and accuracy.
It realizes the automated inspection of integrated circuit design simulation system, improves the efficiency and accuracy of design verification, and avoids the tediousness and omissions of manual inspection.
Smart Images
Figure CN120688412A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit design status checking method, device, readable medium, and electronic device. Background Art
[0002] During the design and verification of integrated circuits (ICs), signal checking is a core step in ensuring design correctness and reliability. However, in some existing IC design and verification processes, manual self-checking is often performed. Complex IC designs may involve checking multiple types of signals, which is tedious and prone to missing potential issues, impacting IC verification efficiency and quality. Therefore, achieving automated checking of various signals and modules to improve the efficiency and accuracy of IC design verification has become a pressing technical challenge. Summary of the Invention
[0003] In light of this, the present invention provides an integrated circuit design status inspection method, apparatus, readable medium, and electronic device. The present invention obtains simulation intermediate data and simulation result data generated by a simulation module of an integrated circuit design simulation system, then filters target signals to be inspected from the simulation intermediate data and simulation result data according to a list of signals to be inspected. The target signals to be inspected are then input into an inspection module for inspection, thereby achieving automated inspection of the intermediate data and result data generated by the integrated circuit design simulation system, thereby improving the efficiency and accuracy of integrated circuit design verification.
[0004] In a first aspect, the present invention provides an integrated circuit design status checking method, which is applied to an integrated circuit design simulation system. The integrated circuit design simulation system includes a simulation module and a checking module. The method includes: Determine the type of signal to be checked; Acquire multiple to-be-checked signal lists corresponding to respective signal categories in the to-be-checked signal categories; Obtain simulation intermediate data and simulation result data of the simulation module; Filtering target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected, wherein the signal identifiers of the target signals to be inspected are identical to identifiers of at least some of the signals to be inspected in the list of signals to be inspected; The target signal to be inspected is input into the inspection module, and the inspection module is controlled to inspect the target signal to be inspected to obtain an inspection result.
[0005] In a possible implementation of the first aspect, selecting a target signal to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected includes: Determining identification information of each signal to be checked in the list of signals to be checked; Using identification information of each signal to be checked to filter simulation intermediate data and simulation result data; The signal with the same identification as the signal to be inspected, which is screened out from the simulation intermediate data and the simulation result data, is used as the target signal to be inspected.
[0006] In a possible implementation of the first aspect, the target signal to be inspected includes at least one of the following signals: General signals, handshake signals, state machine signals, clock signals, storage enable signals, cache signals and specified signals, Among them, general signals are used to characterize the validity of data, module status, and transmission status of control information in the integrated circuit design simulation system; designated signals are used to characterize the working status of the integrated circuit design simulation system.
[0007] In a possible implementation of the first aspect above, the general signal includes at least one of the following signals: a signal with a data valid status flag, a signal with an enable flag, a signal with a busy / idle status flag, and a signal with an interrupt flag.
[0008] In a possible implementation of the first aspect above, the designated signal includes at least one of the following signals: a control signal, a system status flag signal, a system performance monitoring signal, a data integrity check signal, a configuration parameter, and an event trigger signal.
[0009] In a possible implementation of the first aspect, the inspection module inspects the target signal to be inspected in the following manner: In the case where the target signal to be inspected includes a universal signal, the inspection module inspects whether the value of each signal in the universal signal is a first value, and if the value of each signal in the universal signal is the first value, determines that the universal signal meets the requirements; or, In the case where the target signal to be inspected includes a handshake signal, the inspection module inspects whether the value of the handshake request signal in the handshake signal is the second value, and counts whether the first triggering number of the handshake request signal and the second triggering number of the confirmation signal in the handshake signal are consistent; if the value of the handshake request signal is not the second value, and the first triggering number and the second triggering number are the same, it is determined that the handshake signal meets the requirements; or, In the case where the target signal to be inspected includes a state machine signal, the inspection module inspects whether the value of the state machine signal is a third value, and if the value of the state machine signal is the third value, determines that the state machine signal meets the requirements; or, In a case where the target signal to be inspected includes a clock signal, the inspection module inspects whether a value of the clock signal remains at a fourth value within a set time period, and if the value of the clock signal remains at the fourth value within the set time period, determines that the clock signal meets the requirements; or In the case where the target signal to be checked includes a storage enable signal, the checking module checks whether the value of the storage enable signal is a fifth value, and checks whether an overflow or underflow occurs in a memory of the integrated circuit design simulation system. If the value of the storage enable signal is the fifth value and the memory does not overflow or underflow, it is determined that the storage enable signal meets the requirements; or In the case where the target signal to be checked includes a cache signal, the checking module checks whether the cache status of the integrated circuit design simulation system is empty, and if the cache status is empty, determines that the cache signal meets the requirements; or When the target signal to be inspected includes a specified signal, the inspection module checks whether the numerical value or state of each signal in the specified signal is respectively the same as the expected value or expected state corresponding to each signal in the specified signal. If the numerical value or state of each signal in the specified signal is respectively the same as the expected value or expected state corresponding to each signal in the specified signal, it is determined that the specified signal meets the requirements.
[0010] In a second aspect, the present invention provides an integrated circuit design simulation device, comprising: A signal category determination module, used to determine the category of the signal to be checked; A first acquisition module is used to acquire a plurality of to-be-checked signal lists corresponding to each signal category in the to-be-checked signal category; The second acquisition module is used to obtain simulation intermediate data and simulation result data of the simulation module; a screening module, configured to screen target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected, wherein the signal identifier of the target signal to be inspected is the same as the identifiers of at least some of the signals to be inspected in the list of signals to be inspected; The control module is used to input the target signal to be inspected into the inspection module, and control the inspection module to inspect the target signal to be inspected to obtain an inspection result.
[0011] In a third aspect, the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed on an electronic device, causes the electronic device to execute the integrated circuit design status checking method of the first aspect and any possible implementation of the first aspect.
[0012] In a fourth aspect, the present invention provides a computer program product, which includes instructions, and when the instructions are executed by one or more processors, they are used to implement the integrated circuit design status checking method as described in the first aspect and any possible implementation of the first aspect.
[0013] In a fifth aspect, the present invention provides an electronic device, comprising: memory for storing instructions, and One or more processors, when the instruction is executed by the one or more processors, the processors execute the integrated circuit design status checking method as described in the first aspect and any possible implementation of the first aspect.
[0014] Compared with the prior art, the beneficial effect of the present invention is that: the present invention obtains the simulation intermediate data and simulation result data generated by the simulation module of the integrated circuit design simulation system, and then filters out the target signal to be checked from the simulation intermediate data and simulation result data according to the list of signals to be checked, and then inputs the target signal to be checked into the inspection module for inspection, thereby realizing the automated inspection of the intermediate data and result data generated by the integrated circuit design simulation system, and improving the design verification efficiency and accuracy of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 According to some embodiments of the present application, a structural block diagram of an integrated circuit design simulation system is shown; Figure 2 According to some embodiments of the present application, a flow chart of a method for checking an integrated circuit design status is shown; Figure 3 According to some embodiments of the present application, a structural block diagram of an integrated circuit design simulation device is shown; Figure 4 According to some embodiments of the present application, a structural block diagram of an electronic device is shown. DETAILED DESCRIPTION
[0016] The illustrative embodiments of the present application include, but are not limited to, an integrated circuit design status checking method, apparatus, readable medium, and electronic device.
[0017] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.
[0018] Figure 1 According to some embodiments of the present application, a structural block diagram of an integrated circuit design simulation system is shown. Figure 1In the embodiment shown, the integrated circuit design simulation system includes a simulation module and an inspection module. The design file is input into the simulation module for simulation to obtain simulation result data. After the simulation is completed, the target signal to be inspected is screened out from the simulation intermediate data involved in the simulation process of the simulation module and the above-mentioned simulation result data according to a predetermined list of signals to be inspected, and then the target signal to be inspected is input into the inspection module, and the inspection module is controlled to inspect the target signal to be inspected to obtain the inspection result. Since the inspection module is integrated into the integrated circuit design simulation system, after the simulation module of the integrated circuit design simulation system completes the simulation of the design file each time, the inspection module can automatically perform the inspection of the target signal to be inspected, thereby avoiding the workload of manually writing the inspection code after each simulation is performed. In addition, the automatic inspection is not likely to miss the inspection of some key signals, which can improve the comprehensiveness and accuracy of the inspection, thereby helping to improve the design verification efficiency and accuracy of the integrated circuit.
[0019] It should be understood that the integrated circuit design simulation system provided in this application may include other modules, such as a post-processing module, in addition to the above-mentioned simulation module and inspection module, and this application does not limit this.
[0020] Figure 2 According to some embodiments of the present application, a flow chart of a method for checking the design status of an integrated circuit is shown, which is applied to Figure 1 The integrated circuit design simulation system shown in Figure 1 is a reference to the Figure 2 The present invention provides an integrated circuit design status checking method comprising the following steps: S10: Determine the type of the signal to be checked.
[0021] In some embodiments, the signal categories to be checked are determined based on the register transfer level (RTL) specifications of the integrated circuit to be designed and the designer's previous experience. By analyzing the RTL specifications, it is possible to identify which signal categories have a significant impact on the IC's functionality or timing, thereby reducing redundant IC checks and focusing resources on verifying the core logic. Combined with the designer's previous experience, signal categories that have been prone to errors can be identified and designated as part of the signal categories to be checked. This can avoid missing error-prone signals and thus prevent functional defects in the designed IC.
[0022] For example, in some embodiments, based on RTL specifications and designers' past experience, the signal categories to be checked include: general signals, handshake signals, state machine signals, clock signals, storage enable signals, cache signals, and specified signals.
[0023] Among them, general signals are used to characterize the validity of data, the status of modules, and the transmission status of control information in the integrated circuit design simulation system. The status of these signals is crucial to the normal operation of the integrated circuit.
[0024] In some embodiments, the general signal includes at least one of the following signals: a signal with a data valid status flag, a signal with an enable flag, a signal with a busy status flag, and a signal with an interrupt flag. For example, in some embodiments, the data valid status flag is vld or valid, the enable flag is _en or enable, the busy status flag is busy, and the interrupt flag is int or irq.
[0025] In some embodiments, to enhance the anti-interference capability of the integrated circuit and the stability of the system, the default state of the general signals can be set to a low level. If 0 represents a low level and 1 represents a high level, then for many of the general signals, the default value is 0. For example, for a general signal with the word vld or valid, the default value is 0, indicating the validity of the data or operation; for a general signal with the word _en or enable, the default value is 0, indicating a low-level enable; for a general signal with the word busy, the default value is 0, indicating whether the device is in an idle state; for a general signal with the word int or irq, the default value is 0, indicating no interrupt request.
[0026] It should be noted that the default value of the above-mentioned general signal can be determined according to actual conditions, and this application does not limit this.
[0027] Since handshake signals play an important role in the correct data transmission between the sender and the receiver, by checking the above handshake signals, it is possible to determine whether the communicating parties in the integrated circuit have correctly completed the data exchange process, thereby avoiding data loss or system deadlock problems caused by communication failures.
[0028] Since the state machine signal is one of the core components in digital circuit design, it is used to implement complex control logic and can indicate the current state stage of the logic operation. Therefore, by checking the above state machine signal, it can be determined whether the operating state of the state machine of the simulation module after the simulation is completed is the expected value, thereby avoiding system hangs and ensuring the correctness and stability of the integrated circuit function.
[0029] Since the correct timing relationship is the basis for the coordinated operation of various modules in the integrated circuit, the correctness of the integrated circuit timing and the integrity of its functions are ensured by checking the clock signal.
[0030] Since the memory and cache are used for data storage and buffering respectively, they play a bridging role in the data transmission process. Therefore, by checking the storage enable signal and cache signal, problems such as overflow and underflow of the memory and cache can be discovered in time, so that a defense mechanism can be built to prevent the aforementioned overflow and underflow problems in advance. This not only helps to improve the continuity and integrity of the data flow, but also effectively avoids the risk of data congestion and significantly improves the robustness and reliability of the system.
[0031] In some embodiments, the aforementioned designated signals include at least one of the following signals: a control signal, a system status flag signal, a system performance monitoring signal, a data integrity check signal, a configuration parameter, and an event trigger signal. Because the aforementioned designated signals are used to characterize the operating status of the integrated circuit design simulation system, they are also critical to the normal operation of the integrated circuit. Specifically inspecting each of the designated signals can help identify potential problems. For example, inspecting the designated signals can reveal residual signals such as residual voltage, signal reflections, and residual electromagnetic interference that have not been completely eliminated. If not detected and processed in a timely manner, these residual signals may cause abnormalities in subsequent operations.
[0032] Among them, the above-mentioned control signals are used to implement the control of certain specific operations, such as signals for starting or stopping a specific operation. The above-mentioned system status flag signal is used to indicate the flag bit of the current state of the system, especially in complex state management logic. The above-mentioned system performance monitoring signal is used to monitor key indicators of system performance, such as the output of the temperature sensor, power consumption level, etc. The above-mentioned data integrity check signal is used to verify the signal generated by the check code or similar mechanism for data integrity. The above-mentioned configuration parameters include some dynamically adjustable configuration parameters, which determine the working mode or characteristics of each module in the integrated circuit. The above-mentioned event trigger signal is used to mark the occurrence of specific events, such as the occurrence of events such as the expiration of the marking timer and the external interrupt request.
[0033] S20: Acquire multiple to-be-checked signal lists corresponding to each signal category in the to-be-checked signal category.
[0034] The signal categories to be checked determined in S10 include: general signals, handshake signals, state machine signals, clock signals, storage enable signals, cache signals, and designated signals. It is understood that corresponding to the signals in each category of the signal categories to be checked, a signal list, a handshake signal list, a state machine signal list, a clock signal list, a storage enable signal list, a cache signal list, and a designated signal list need to be obtained.
[0035] In some embodiments, the general signal list and handshake signal list can be generated by script analysis of the output of the design file. In some embodiments, the state machine signal list is generated by a coverage analysis tool. In some embodiments, the specified signal list is generated by user input. In some embodiments, the storage enable signal list is obtained from the design documentation of the integrated circuit. In some embodiments, the cache signal list is derived using a waveform display tool. In some embodiments, the clock signal is generated by user input.
[0036] Furthermore, in some embodiments, users can create a text document (txt format) in a specified format to describe the specific information for the specified signal list. For example, the document format might be: signal hierarchy path + signal value to be checked. In other words, the signal path and correct value of each signal to be checked are written into the document.
[0037] In some embodiments, users can also create a text document (txt format) in a specified format to describe the clock signal list. For example, the document format might be: gated clock signal name + corresponding clock hierarchy path. In other words, the clock signal names and corresponding clock paths are recorded in the text document.
[0038] Because the signal paths and expected values in these documents can be parsed by scripts, they can be used to automate checks based on the data in the text. Furthermore, since these documents record signal-level or clock-level paths, if the IC design document code is modified, such as a change in the signal-level path, only the path information in the document needs to be updated, without having to adjust the underlying verification code.
[0039] By obtaining multiple lists of signals to be inspected corresponding to each signal category in the signal category to be inspected, structured input is provided for subsequent automated inspection. By adopting corresponding inspection strategies according to different signal types, the most suitable inspection method can be used for each type of signal, thereby improving the efficiency and accuracy of verification.
[0040] In some embodiments, the list of signals to be checked not only contains the categories of the signals to be checked, but also contains the correct values (also referred to as default values, reference values, or expected values) or correct states (also referred to as default states, reference states, or expected states) of the signals to be checked. It should be understood that since the list of signals to be checked records the correct values of the signals to be checked, the correct values of the signals to be checked can be used as reference values for subsequent checking modules when checking the actually obtained target signals to be checked.
[0041] For example, for general signals, the reference value is set to the first value; for handshake signals, the reference value is set to the second value; for state machine signals, the reference value is set to the third value; for clock signals, the reference value is set to the fourth value; for storage enable signals, the reference value is set to the fifth value; for cache signals, the reference state is set to empty; for specified signals, the corresponding expected value is set for each of the signals.
[0042] The first to fifth values and the expected value of each signal in the specified signal can be determined according to actual conditions, and this application does not limit this. For example, in some embodiments, the first to fifth values are all set to 0.
[0043] S30: Acquire simulation intermediate data and simulation result data of the simulation module.
[0044] Among them, simulation intermediate data is the real-time signal status or temporary results dynamically generated by the simulation module during the simulation process; simulation result data is the final verification conclusion or statistical information generated by the simulation module after the simulation is completed, which is used to evaluate the correctness of the design.
[0045] S40: Filtering out target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected, wherein the signal identifier of the target signal to be inspected is the same as the identifiers of at least some of the signals to be inspected in the list of signals to be inspected.
[0046] In some embodiments, target signals to be checked are screened out from simulation intermediate data and simulation result data according to a list of signals to be checked, including: determining identification information of each signal to be checked in the list of signals to be checked; screening the simulation intermediate data and simulation result data using the identification information of each signal to be checked; and using the signal with the same identification as the signal to be checked screened out from the simulation intermediate data and simulation result data as the target signal to be checked.
[0047] In some embodiments, the target signal to be checked includes at least one of the following signals: a general signal, a handshake signal, a state machine signal, a clock signal, a storage enable signal, a cache signal, and a designated signal.
[0048] By screening the simulation intermediate data and simulation result data, the target signal to be checked is obtained, thereby reducing the processing of redundant data. While ensuring the correct function of the integrated circuit, the efficiency of integrated circuit simulation verification can also be improved.
[0049] S50: Inputting the target signal to be inspected into the inspection module, and controlling the inspection module to inspect the target signal to be inspected to obtain an inspection result.
[0050] The check module, also known as a checker, can implement check logic through scripts. Adding these scripts to the Testbench (an integrated circuit verification platform) enables automated checking. For example, using a scripting language like Python to generate the checker's hardware description language, then compiling it into the Testbench, allows for automated checking of the IC's design status.
[0051] In some embodiments, the inspection module inspects the target signal to be inspected in the following manner: When the target signal to be inspected includes a universal signal, the inspection module inspects whether the value of each signal in the universal signal is a first value. If the value of each signal in the universal signal is the first value, it is determined that the universal signal meets the requirements.
[0052] For example, assuming that the first value is 0, for the signal with the data valid status flag vld or valid in the general signal, when the inspection module determines that the actual value of the signal is 0, since the reference value of the signal is also 0, it can be determined that the actual value of the signal with the valid status flag vld or valid is correct, and it is determined that the signal with the data valid status flag vld or valid meets the requirements.
[0053] For the signal with the enable flag _en or enable in the general signal, when the inspection module determines that the actual value of the signal is 0, since the reference value of the signal is also 0, it can be determined that the actual value of the signal with the enable flag _en or enable is correct, and it is determined that the signal with the enable flag _en or enable meets the requirements.
[0054] For the signal with the busy status flag busy in the general signal, when the inspection module determines that the actual value of the signal is 0, since the reference value of the signal is also 0, it can be determined that the actual value of the signal with the busy status flag busy is correct, and it is determined that the signal with the busy status flag busy meets the requirements.
[0055] For a general signal with an interrupt flag int or irq, when the inspection module determines that the actual value of the signal is 0, since the reference value of the signal is also 0, it can be determined that the actual value of the signal with the interrupt flag int or irq is correct, and it is determined that the signal with the interrupt flag int or irq meets the requirements.
[0056] In some embodiments, when the target signal to be checked includes a handshake signal, the inspection module checks whether the value of the handshake request signal in the handshake signal is the second value, and counts whether the first triggering number of the handshake request signal and the second triggering number of the confirmation signal in the handshake signal are consistent. If the value of the handshake request signal is not the second value, and the first triggering number and the second triggering number are the same, it is determined that the handshake signal meets the requirements.
[0057] For example, assuming the second value is 0, the checking module checks whether the value of the handshake request signal in the handshake signal is 0, and counts the first triggering number of the handshake request signal and the second triggering number of the confirmation signal in the handshake signal. If they are consistent, it is determined that the handshake signal meets the requirements.
[0058] In some embodiments, when the target signal to be inspected includes a state machine signal, the inspection module inspects whether the value of the state machine signal is a third value. If the value of the state machine signal is the third value, it is determined that the state machine signal meets the requirements.
[0059] For example, assuming that the third value is 0, the checking module checks that the value of the state machine signal is 0, and then determines that the state machine signal meets the requirements.
[0060] In some embodiments, when the target signal to be checked includes a clock signal, the inspection module checks whether the value of the clock signal remains at a fourth value within a set time period. If the value of the clock signal remains at the fourth value within the set time period, it is determined that the clock signal meets the requirements.
[0061] For example, assuming that the fourth value is also 0, the checking module checks whether the value of the clock signal remains 0, that is, remains low, within a set time period, and then determines that the clock signal meets the requirements. The set time period can be determined according to actual needs and is not limited in this application.
[0062] In some embodiments, when the target signal to be checked includes a storage enable signal, the inspection module checks whether the value of the storage enable signal is the fifth value, and checks whether the memory of the integrated circuit design simulation system has overflowed or underflowed. If the value of the storage enable signal is the fifth value and the memory has not overflowed or underflowed, it is determined that the storage enable signal meets the requirements.
[0063] For example, assuming that the fifth value is also 0, the checking module checks that the value of the storage enable signal is 0, and the memory does not overflow or underflow, and then determines that the storage enable signal meets the requirements.
[0064] In some embodiments, when the target signal to be checked includes a cache signal, the checking module checks whether the cache status of the integrated circuit design simulation system is empty. If the cache status is empty, it is determined that the cache signal meets the requirements.
[0065] For example, assuming that the reference state of the buffered signal is empty, if the buffered state is empty, it is determined that the buffered signal meets the requirements.
[0066] In some embodiments, when the target signal to be inspected includes a specified signal, the inspection module checks whether the numerical value or state of each signal in the specified signal is respectively the same as the expected value or expected state corresponding to each signal in the specified signal. If the numerical value or state of each signal in the specified signal is respectively the same as the expected value or expected state corresponding to each signal in the specified signal, it is determined that the specified signal meets the requirements.
[0067] For example, in some embodiments, when a line in a designated signal (in a document entered by a user) contains the keyword "CLK_GATE," the signal containing that keyword is identified as a clock gating signal (Gate Clock), and further verification is required to determine whether the gated clock conforms to the expected logic. In other embodiments, when a line in a designated signal does not contain "CLK_GATE," the signal recorded in that line is identified as a normal signal, such as a data bus. Verification is then required to determine whether the value or state of that signal is identical to the expected value or state corresponding to each signal in the designated signal. If so, the designated signal is determined to meet the requirements.
[0068] The present invention obtains simulation intermediate data and simulation result data generated by a simulation module of an integrated circuit design simulation system, then filters out target signals to be checked from the simulation intermediate data and simulation result data according to a list of signals to be checked, and then inputs the target signals to be checked into the inspection module for inspection, thereby realizing automated inspection of the intermediate data and result data generated by the integrated circuit design simulation system and improving the design verification efficiency and accuracy of the integrated circuit.
[0069] It can be understood that the execution order of the above steps S10 to S50 is only an illustration. In other embodiments, other execution orders may be adopted, and some steps may be split or combined, which is not limited here.
[0070] In addition, the embodiment of the present invention further provides an integrated circuit design simulation device 200. Figure 3 , the integrated circuit design simulation device 200 includes: A signal category determination module 201 is used to determine the category of the signal to be checked; A first acquisition module 202 is configured to acquire a plurality of lists of signals to be checked, each corresponding to each signal category in the signal category to be checked; The second acquisition module 203 is used to acquire simulation intermediate data and simulation result data of the simulation module; A screening module 204 is configured to screen target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected, wherein the signal identifier of the target signal to be inspected is the same as the identifiers of at least some of the signals to be inspected in the list of signals to be inspected; The control module 205 is configured to input the target signal to be inspected into the inspection module, and control the inspection module to inspect the target signal to be inspected to obtain an inspection result.
[0071] An embodiment of the present invention further provides an electronic device 300, such as Figure 4 As shown, the electronic device 300 includes a memory 301 and a processor 302. The memory 301 is used to store computer programs executable by the processor 302; the processor 302 is used to execute the computer program in the memory 301 to implement the integrated circuit design status inspection method provided in any one of the above embodiments.
[0072] Figure 4 The electronic device 300 shown further includes a communication interface 303. The processor 302, the memory 301 and the communication interface 303 are connected via a communication bus and communicate with each other.
[0073] The processor 302 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above-mentioned programs.
[0074] The communication interface 303 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.
[0075] The memory 301 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory can be independent and connected to the processor via a bus. The memory can also be integrated with the processor.
[0076] An embodiment of the present invention further provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed on an electronic device, the electronic device executes the integrated circuit design status checking method provided by any of the above embodiments.
[0077] An embodiment of the present invention further provides a computer program product, which includes instructions. When the instructions are executed by one or more processors, they are used to implement the integrated circuit design status checking method provided by any of the above embodiments.
[0078] The various embodiments of the mechanisms disclosed in the present invention can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present invention can be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.
[0079] It should be noted that the various units / modules mentioned in the various device embodiments of the present invention are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by the present invention. In addition, in order to highlight the innovative part of the present invention, the above-mentioned device embodiments of the present invention do not introduce units / modules that are not closely related to solving the technical problems raised by the present invention. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.
[0080] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "including a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.
[0081] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims
1. A method for checking the design status of an integrated circuit, characterized in that: Applied to an integrated circuit design simulation system, the integrated circuit design simulation system includes a simulation module and a checking module, and the method includes: Determine the type of signal to be checked; Acquire multiple lists of signals to be checked that correspond to respective signal categories in the signal categories to be checked; Acquiring simulation intermediate data and simulation result data of the simulation module; Filtering target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected, wherein the signal identifier of the target signal to be inspected is the same as the identifiers of at least some of the signals to be inspected in the list of signals to be inspected; The target signal to be inspected is input into the inspection module, and the inspection module is controlled to inspect the target signal to be inspected to obtain an inspection result.
2. The integrated circuit design status checking method according to claim 1, wherein: The step of screening out target signals to be inspected from the simulation intermediate data and the simulation result data according to the list of signals to be inspected comprises: Determining identification information of each signal to be checked in the list of signals to be checked; Filtering the simulation intermediate data and the simulation result data using the identification information of each signal to be checked; A signal having the same identifier as the signal to be inspected, which is screened out from the simulation intermediate data and the simulation result data, is used as a target signal to be inspected.
3. The integrated circuit design status checking method according to claim 1, wherein: The target signal to be inspected includes at least one of the following signals: General signals, handshake signals, state machine signals, clock signals, storage enable signals, cache signals and specified signals, Among them, the general signal is used to characterize the validity of data, the status of modules and the transmission status of control information in the integrated circuit design simulation system; the specified signal is used to characterize the working status of the integrated circuit design simulation system.
4. The integrated circuit design status checking method according to claim 3, wherein: The general signal includes at least one of the following signals: a signal with a data valid status flag, a signal with an enable flag, a signal with a busy / idle status flag, and a signal with an interrupt flag.
5. The integrated circuit design status checking method according to claim 4, characterized in that: The designated signal includes at least one of the following signals: a control signal, a system status flag signal, a system performance monitoring signal, a data integrity check signal, a configuration parameter, and an event trigger signal.
6. The integrated circuit design status checking method according to claim 5, characterized in that: The inspection module inspects the target signal to be inspected in the following manner: In the case where the target signal to be inspected includes a universal signal, the inspection module inspects whether the value of each signal in the universal signal is a first value, and if the value of each signal in the universal signal is the first value, determines that the universal signal meets the requirements; or In the case where the target signal to be inspected includes a handshake signal, the inspection module inspects whether the value of the handshake request signal in the handshake signal is the second value, and counts whether a first triggering number of the handshake request signal and a second triggering number of the confirmation signal in the handshake signal are consistent; if the value of the handshake request signal is not the second value, and the first triggering number and the second triggering number are the same, it is determined that the handshake signal meets the requirements; or, In a case where the target signal to be checked includes a state machine signal, the checking module checks whether the value of the state machine signal is a third value, and if the value of the state machine signal is the third value, determines that the state machine signal meets the requirements; or In a case where the target signal to be inspected includes a clock signal, the inspection module inspects whether a value of the clock signal remains at a fourth value within a set time period, and if the value of the clock signal remains at the fourth value within the set time period, determines that the clock signal meets the requirements; or In the case where the target signal to be checked includes a storage enable signal, the checking module checks whether the value of the storage enable signal is a fifth value, and checks whether an overflow or underflow occurs in the memory of the integrated circuit design simulation system; if the value of the storage enable signal is the fifth value and the memory does not overflow or underflow, it is determined that the storage enable signal meets the requirements; or In the case where the target signal to be checked includes a cache signal, the checking module checks whether the cache status of the integrated circuit design simulation system is empty, and if the cache status is empty, determines that the cache signal meets the requirements; or When the target signal to be inspected includes a designated signal, the inspection module checks whether the numerical value or state of each signal in the designated signal is respectively the same as the expected value or expected state corresponding to each signal in the designated signal; if the numerical value or state of each signal in the designated signal is respectively the same as the expected value or expected state corresponding to each signal in the designated signal, it is determined that the designated signal meets the requirements.
7. An integrated circuit design simulation device, characterized in that: include: A signal category determination module, used to determine the category of the signal to be checked; A first acquisition module is used to acquire a plurality of to-be-checked signal lists corresponding to each signal category in the to-be-checked signal category; A second acquisition module is used to acquire simulation intermediate data and simulation result data of the simulation module; a screening module, configured to screen out target signals to be checked from the simulation intermediate data and the simulation result data according to the list of signals to be checked, wherein the signal identifier of the target signal to be checked is the same as the identifiers of at least some of the signals to be checked in the list of signals to be checked; The control module is configured to input the target signal to be inspected into the inspection module, and control the inspection module to inspect the target signal to be inspected to obtain an inspection result.
8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, which, when executed on an electronic device, enable the electronic device to execute the integrated circuit design status checking method according to any one of claims 1 to 6.
9. A computer program product, characterized in that The computer program product includes instructions, which are used to implement the integrated circuit design status checking method according to any one of claims 1 to 6 when executed by one or more processors.
10. An electronic device, characterized in that: include: memory for storing instructions, and One or more processors, when the instructions are executed by the one or more processors, the processors perform the integrated circuit design status checking method according to any one of claims 1 to 6.