Packaging structure and forming method thereof

Abstract

The method includes: placing the integrated voltage regulator in a first package component; placing the RC component in a second packaging component; electrically connecting the RC component to the integrated voltage regulator; and electrically connecting the device die to the RC component. The RC component is located in an electrical path connecting the integrated voltage regulator to the device die. The embodiment of the invention also relates to a packaging structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure and a method for forming the same. Background Art

[0002] Voltage regulators are used to provide power in integrated circuits. A voltage regulator regulates the voltage of a power supply. Within a package, the voltage regulator can be formed as a discrete die that is bonded to a printed circuit board (PCB). The voltage generated by the voltage regulator is then supplied to the integrated circuit assembly, which is also bonded to the PCB. Summary of the Invention

[0003] Some embodiments of the present application provide a method for forming a packaging structure, comprising: placing an integrated voltage regulator in a first packaging component; placing an RC component in a second packaging component; electrically connecting the RC component to the integrated voltage regulator; and electrically connecting a first device die to the RC component, wherein the RC component is located in an electrical path connecting the integrated voltage regulator to the first device die.

[0004] Other embodiments of the present application provide a packaging structure including: an integrated voltage regulator; an RC component located above the integrated voltage regulator and electrically coupled to the integrated voltage regulator; a first device die located above the integrated voltage regulator and the RC component; a first electrical connection path connecting the integrated voltage regulator to the input end of the RC component; and a second electrical connection path connecting the output end of the RC component to the first device die.

[0005] Some other embodiments of the present application provide a packaging structure, comprising: a packaging substrate, comprising: a first redistribution structure; a dielectric core, located above the first redistribution structure; a second redistribution structure, located above the dielectric core; a plurality of through-holes, located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator, located in the dielectric core; and an RC component, located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a packaging component, located above the packaging substrate and bonded to the packaging substrate, wherein the packaging component includes a device die electrically connected to the RC component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 9A cross-sectional view illustrates an intermediate stage in the formation of a package including an integrated voltage regulator (IVR) and a resistor-capacitor (RC) component, in accordance with some embodiments.

[0008] Figure 10 An enlarged view of a portion of a package is shown, according to some embodiments.

[0009] Figure 11 and Figure 12 A package and an enlarged portion of the package are respectively shown, according to some embodiments.

[0010] Figure 13 and Figure 14 A package and an enlarged portion of the package are respectively shown, according to some embodiments.

[0011] Figures 15 to 18 Some packages including IVR and RC components are shown according to some embodiments.

[0012] Figure 19 and Figure 20 A circuit diagram of an IVR and RC component is shown according to some embodiments.

[0013] Figure 21 The effect of IVR and RC components in a package according to some embodiments is shown.

[0014] Figure 22 A process flow for forming a package is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] A package including an integrated voltage regulator (IVR) and a resistor-capacitor (RC) assembly and a method for forming the same are provided. According to some embodiments of the present disclosure, the IVR and RC assembly are embedded in the package. The IVR and RC assembly can be embedded in a core of a package substrate, a build-up structure of the package substrate, an underfill, a redistribution structure, a layer for distributing local silicon interconnect (LSI) dies, or the like. The RC assembly is located near the IVR. Furthermore, the RC assembly can be located in the path between the IVR and an electrical device powered by a regulated voltage, so that the resistance of the connecting line can be reduced. By employing the IVR and RC assembly, the transient overshoot of the IVR can be reduced.

[0018] The embodiments discussed herein are intended to provide examples of how the subject matter of the disclosed embodiments can be made or used, and those skilled in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to denote like elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0019] Figures 1 to 9 1 shows a diagram of an intermediate stage in the formation of a package including IVR and RC components according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Figure 22 In the process flow shown in .

[0020] Figure 1 A carrier 20 and a release film 22 formed on the carrier 20 are shown. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 22 may be formed of a polymer-based material (such as a light-to-heat conversion (LTHC) material) that can be decomposed under heat radiation (such as a laser beam) so that the carrier 20 can be peeled off from the upper structure to be formed in a subsequent process.

[0021] An accumulation structure 24 (also referred to as a redistribution structure 24 or an interconnect structure 24) is formed over the carrier 20. The corresponding process is shown as follows. Figure 22202 in the process flow 200 shown in FIG. The build-up structure 24 includes a plurality of dielectric layers 26 and a plurality of redistribution lines (RDLs) 28 formed over the release film 22. The dielectric layer 26 may be formed of a polymer, which may also be a photosensitive material that can be patterned using a photolithography process including an exposure process and a development process, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.

[0022] The RDL 28 may be formed by plating. The formation of the RDL 28 may include forming a metal seed layer (not shown); forming a patterned mask (not shown), such as a photoresist, over the metal seed layer; and then performing a metal plating process on the exposed seed layer. The patterned mask and the portion of the metal seed layer covered by the patterned mask are then removed, leaving the RDL 28. According to some embodiments, the metal seed layer includes a titanium layer and a copper layer over the titanium layer. The metal seed layer may be formed using, for example, physical vapor deposition (PVD) or a similar process. Plating may be performed using, for example, an electrochemical plating process or an electroless plating process. The plating material may include copper.

[0023] Next, as Figure 2 As shown in FIG, a metal rod 30 is formed. The corresponding process is shown as follows Figure 22 The process 204 in the process flow 200 shown in FIG. The formation process may include forming a metal seed layer; forming a plating mask (not shown, which may be a photoresist) over the metal seed layer; patterning the plating mask to expose the underlying metal seed layer; and then plating a metal material in the openings of the plating mask. The plating mask is then removed, followed by an etching process to remove portions of the metal seed layer previously covered by the plating mask.

[0024] The metal rods 30 are optionally referred to as through-holes because they penetrate a subsequently formed sealing material (which may be a molding compound). The metallization material may be copper or a copper alloy. The metal rods 30 may have substantially vertical and straight edges. According to an alternative embodiment, a conductive tube (also known as a plated through-hole (PTH)) is formed. The formation of the PTH may be substantially the same as the formation of the metal rods 30.

[0025] Figure 2 Also shown is the placement / attachment of the IVR die 32. The corresponding process is shown as follows Figure 22 200 . The IVR die 32 may be attached to the redistribution structure 24, for example, via a die attach film 34, which may be an adhesive film. The IVR die 32 includes electrical connectors 36A and 36B (collectively, electrical connectors 36), which may include input and output nodes. According to some embodiments, the electrical connectors 36A and 36B may be metal pillars.

[0026] Figure 19FIG. 3 shows a circuit diagram of an exemplary IVR die 32 according to some embodiments. According to some embodiments, the input node 36A of the IVR die 32 is used to receive a high input voltage Vi, such as 15V, 9V, etc. The input voltage Vi is also Figure 2 According to some embodiments, other power supply voltages, such as 5V, 3.3V, 1.2V, 0.9V, and 0.75V, are generated at the output node 36B by the driver IC and other circuits. The output node 36B is also Figure 2 The electrical connector 36B in.

[0027] Next, refer to Figure 3 , the IVR die 32 and the metal rod 30 are sealed in the sealant 38. The corresponding process is shown as follows Figure 22 200. The encapsulant 38 fills the gaps between adjacent metal rods 30 and the IVR die 32. The encapsulant 38 may include fiberglass, prepreg (which includes epoxy, resin, and / or fiberglass), resin-coated copper (RCC), glass, plastic (such as polyvinyl chloride (PVC), acrylonitrile butadiene and styrene (ABS), polypropylene (PP), polyethylene (PE), polystyrene (PS), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyphenylene sulfide (PPS), flexible (polyimide), molding compound, molded underfill, epoxy, resin, or a combination thereof.

[0028] When formed from a molding compound, encapsulant 38 may include a base material (which may be a polymer, resin, epoxy, etc.) and filler particles within the base material. The filler particles may be dielectric particles of SiO2, Al2O3, silicon dioxide, etc., and may have a spherical shape. Furthermore, the spherical filler particles may have a variety of different diameters.

[0029] Then, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to thin the encapsulant 38 until the metal rods 30 and the IVR die 32 are exposed. Due to the planarization process, the top ends of the through-holes 30 are substantially flush (coplanar) with the top surfaces of the electrical connectors 36 and substantially coplanar with the top surface of the encapsulant 38. Throughout the description, the metal rods 30 are also referred to as through-holes 30 because they penetrate the encapsulant 38. The encapsulant 38 serves as a dielectric core (and is also referred to as dielectric core 38) in the corresponding package substrate.

[0030] Figure 4 The formation of a redistribution structure 40 (also referred to as an interconnect structure) is shown, and the redistribution structure 40 includes a dielectric layer 42 and an RDL 44. The corresponding process is shown as follows Figure 22The process 210 in the process flow 200 is shown in FIG. The redistribution structure 40 is alternatively referred to as a build-up structure 40 or an interconnect structure 40. The formation of the redistribution structure 40 can be substantially the same as the formation of the redistribution structure 24. The dielectric layer 42 can be formed of an organic material, such as PBO, polyimide, etc.

[0031] refer to Figure 5 , an opening 46 is formed in the dielectric layer 42 in the redistribution structure 40. The corresponding process is shown as follows Figure 22 212 in the process flow 200 shown in FIG. According to some embodiments, the formation process may include an etching process in which an etching mask (such as a photoresist) is formed to define the size and position of opening 46. According to an optional embodiment, the formation of opening 46 includes a laser ablation process. Metal pad 48 may be formed as an etch stop layer (or a stop layer for laser ablation). Metal pad 48 is also formed in the same process as the corresponding layer of RDL 44. Metal pad 48 may be electrically floating or may have an electrical connection function, for example, where current flows.

[0032] According to an alternative embodiment, opening 46 penetrates dielectric layer 42 , wherein the top surface of encapsulant 38 is exposed and serves as an etch stop layer.

[0033] Figure 5 Also shown is the placement of the RC assembly 50 inside the opening 46. The corresponding process is shown as follows Figure 22 4. In some embodiments, placement is achieved by using a die attach film 54 that bonds RC assembly 50 to metal pad 48. In some embodiments, opening 46 is formed such that RC assembly 50 can be tightly seated in opening 46, with sidewalls of RC assembly 50 in physical contact with sidewalls of dielectric layer 42. In some embodiments, the sidewalls of RC assembly 50 can be spaced apart from RDL 44, or can be in physical contact with RDL 44. For example, RC assembly 50 can include electrical connectors 52 (including 52A and 52B).

[0034] The RC assembly 50 may have various structures. For example, Figure 19 It is shown that the RC component 50 may include a plurality of resistors 58 and a plurality of capacitors 60. The resistors 58 and capacitors 60 may form a cell, and the RC component 50 may include a plurality of cells connected in parallel.

[0035] Figure 20 5. The RC component 50 is shown as a single RC including a single resistor 58 and a single capacitor 60 according to some embodiments. It should be understood that the IVR 32 and the RC component 50 may have other Figure 19 and Figure 20Many applicable forms other than those shown in FIG, and corresponding IVR 32 and RC assembly 50 are also within the scope of the disclosed embodiments.

[0036] According to some embodiments, Figure 6 As shown in FIG, gap filling region 56 is formed to fill the remaining portion of opening 46. The corresponding process is shown as FIG. Figure 22 2. In some embodiments, gapfill region 56 is formed of or includes an underfill, a polymer, a resin, an epoxy, or the like. Gapfill region 56 is dispensed into opening 46 and then cured to a solid state after dispensing, followed by a planarization process to make its top surface flush with the top surfaces of redistribution structure 40 and electrical connector 52. Gapfill region 56 is in physical contact with dielectric layer 42 and may or may not be in physical contact with some of RDL 44 on the opposite side of gapfill region 56. In some embodiments, gapfill region 56 may also be in physical contact with the top surface of metal pad 48.

[0037] According to some embodiments, the structure above the release film 22 is called a (wafer level) package substrate 61, which may include one or more package substrates therein. According to some embodiments, the package substrate 61 may be peeled off from the carrier 20. The corresponding process is shown as follows Figure 22 The debonding process may include projecting radiation (such as a laser beam) onto the release film 22, which penetrates the carrier 20. As a result, the release film 22 decomposes, and the package substrate 61 can be debonded from the carrier 20.

[0038] According to some embodiments, Figure 7 As shown in FIG, an underbump metallurgy 63 and solder regions 62 may be formed on the bottom side of a package substrate 61. One of the solder regions 62 is electrically connected to the IVR die 32 to provide an input voltage to the IVR die 32. The package substrate 61 may include a plurality of identical package substrates 61′, each including an IVR die 32 and an RC assembly 50.

[0039] According to alternative embodiments, the debonding of package substrate 61 from carrier 20 may be performed in a subsequent process, for example, at a time after package assembly 82 (also referred to as package) has been bonded to package substrate 61 .

[0040] According to some embodiments, the package substrate 61 may be singulated during a sawing process, such that a plurality of individual package substrates 61' therein are separated from one another. According to alternative embodiments, sawing the package substrate 61 into individual package substrates 61' may be performed in a subsequent process, for example, after a plurality of package components 82 have been bonded to the package substrate 61'.

[0041] Figure 7 Also shown is a package assembly 82 (also referred to as a package) according to some embodiments. Formation of the package assembly 82 may include forming a redistribution structure 64, which includes a plurality of dielectric layers 66 and redistribution lines 68. The materials and formation processes of the dielectric layers 66 and the redistribution lines 68 may be substantially the same as the materials and formation processes of the dielectric layers 26 and the redistribution lines 28 in the redistribution structure 24, respectively. Solder regions 63 electrically connected to the redistribution lines 68 may be formed beneath the redistribution lines 68.

[0042] Vias 70 electrically connected to redistribution lines 68 are formed over redistribution lines 68. The formation process may be substantially the same as that of vias 30, which may include plating vias 70 directly from metal pads in redistribution lines 68.

[0043] According to some embodiments, device die 72 is bonded to redistribution structure 64. Device die 72 may include an LSI die that is used to electrically interconnect the upper package components 84. Device die 72 may also include a passive device die, such as a deep trench capacitor die. According to some embodiments, LSI die includes a semiconductor substrate 78 and through-substrate vias (TSVs, also known as through-silicon vias) 76. TSVs 76 and vias 70 electrically connect redistribution lines 68 to the upper redistribution lines 80.

[0044] Vias 70 and device die 72 are encapsulated in an encapsulant 74 , which may include a molding compound, a molded underfill, or may include an inorganic material such as a silicon nitride layer and a silicon oxide region over the silicon nitride layer.

[0045] Package assembly 82 may further include a redistribution structure 76 over device die 72. Redistribution structure 76 may include a plurality of dielectric layers 78 and a plurality of redistribution lines 80. The materials and formation processes of dielectric layers 78 and redistribution lines 80 may be substantially the same as those of redistribution structure 24.

[0046] Package assembly 84 (including package assembly 84A and 84B) is bonded to redistribution structure 76. The corresponding process is shown as follows. Figure 22 The process 220 in the process flow 200 is shown in FIG. Bonding the package component 84 to the redistribution structure 76 can be performed by solder bonding, metal-to-metal direct bonding, hybrid bonding (including metal-to-metal direct bonding and fusion bonding), etc.

[0047] Package assembly 84A (also referred to as a device die when including a device die) may be a high-bandwidth memory (HBM) stack. Package assembly 84B may be a discrete device die, a system-on-chip (SoC) die, or the like. Package assembly 84B may also include deep trench capacitors (DTCs), active device dies, and independent passive devices (IPDs).

[0048] In accordance with some embodiments, package assembly 84 may be encapsulated in an encapsulant 86 , which may include a molding compound, a molded underfill, etc. There may also be an underfill in the gap between package assembly 84 and underlying redistribution structure 76 .

[0049] Figure 8 The bonding of package assembly 82 (also referred to as package) to package substrate 61' is shown in accordance with some embodiments. Thus, package 90 is formed. The bonding may be achieved by solder bonding using solder regions 63. Underfill 88 is also dispensed into the gap between package substrate 61' and package assembly 82.

[0050] According to some embodiments where package substrate 61' has been sawn into package substrates 61', die-on-die bonding is performed and individual package components 82 can be bonded to the separate package substrates 61'. According to these embodiments, edges of individual package components 82 can extend laterally beyond corresponding edges of package substrate 61', be vertically aligned with corresponding edges of package substrate 61', or be laterally recessed from corresponding edges of package substrate 61'.

[0051] According to an optional embodiment, a die-bonding process is performed on the wafer in which a plurality of package components 82 are bonded to a package substrate 61 at the wafer level (including a plurality of package substrates 61' that have not been sawn). After the plurality of package components 82 are bonded to the package substrate 61, an additional sealing process may be performed to seal the plurality of package components 82 in an additional sealant 86 that is located above and physically contacts the wafer-level package substrate 61. A sawing process is then performed to saw the resulting package into a plurality of identical packages, each including a package substrate 61' and a package component 82.

[0052] According to an embodiment implementing die-on-wafer bonding, the edges of package assembly 82 are laterally recessed from corresponding edges of underlying package substrate 61 '. The outer edges of an additional encapsulant (not shown) are vertically aligned with the edges of underlying package substrate 61 '.

[0053] Figure 9Package 90 is shown bonded to package assembly 92 to form package 94. Package assembly 92 may include a printed circuit board, another package substrate, etc. In the resulting package 94, an input voltage (which may be a relatively high voltage) may be provided from package assembly 92 to package substrate 61 ′. In accordance with some embodiments, the voltage input path from package assembly 92 to IVR die 32 is shown by arrow 96.

[0054] Arrow 98 shows the voltage conduction path of the output voltage from IVR die 32 to the powered device, which, according to some embodiments, includes package assembly 84. The output voltage (which may be 3.3V, 1.2V, 0.9V, 0.75V, etc.) is conducted through redistribution line 44 to RC assembly 50, and further to solder area 63 and redistribution line 68. The output voltage is further conducted through vias 70 and / or TSVs 76 in device die 74 to redistribution line 80 and to package assembly 84.

[0055] According to some embodiments, the transient overshoot at the IVR output is reduced due to the insertion of the RC component 50 into the path between the IVR die 32 and the package assembly 84. For example, Figure 21 The output voltage of the IVR is shown as a function of time. Line 102 shows the voltage transient before it reaches a steady state when the IVR die 32 is not connected to the RC assembly 50. Line 104 shows the voltage transient before it reaches a steady state when the IVR die 32 is connected to the RC assembly 50. It is observed that the transient overshoot represented by line 102 has a much higher amplitude than the transient overshoot represented by line 104 and lasts longer. Transient overshoot can cause damage to the electrical device and thus cause serious reliability issues. Therefore, the package according to the embodiment of the present disclosure is more reliable.

[0056] In addition, if Figure 19 and Figure 20 As shown in FIG, inductors LP1 and LP2 represent conductive paths 98 ( Figure 9 By inserting an RC component 50 (which is represented as a load resistor Rload) in the path between the IVR die 32 and the package assembly 84, the parasitic inductance is also reduced.

[0057] Figure 10 Shown Figure 9 FIG. 9 is an enlarged view of a portion of package 94 in FIG. 1 , wherein the portion shown includes the IVR die 32 and the RC assembly 50. The redistribution lines 44 are shown as metal vias including metal lines and interconnecting metal lines.

[0058] Figure 11 1 shows a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. Unless otherwise specified, these embodiments (and Figures 13 to 18 The materials, structures, and formation processes of the components in the subsequent embodiments shown in FIG. 1 are substantially the same as the same components denoted by the same reference numerals in the aforementioned embodiments. Throughout the description, details regarding the materials, structures, and formation processes provided in each of the embodiments may be applied to any other embodiment when applicable and may not be repeated.

[0059] exist Figure 11 In the embodiment, the IVR die 32 is not located in the dielectric core 38, but is located in the redistribution structure 40 and may or may not be in contact with the dielectric layer 42. The details of the placement of the IVR die 32 may be as described above. Figure 5 and Figure 6 The placement of RC assembly 50 shown in FIG is substantially the same, and the details are not repeated here. IVR die 32 may be encapsulated in encapsulant 56, or may be tightly seated in an opening in redistribution structure 40 and thus in physical contact with dielectric layer 42. IVR die 32 may or may not be in physical contact with redistribution lines 44.

[0060] RC component 50 is located in redistribution structure 64. According to some embodiments, after redistribution structure 64 is formed, an opening is formed in redistribution structure 64, and RC component 50 is placed in the opening and flip-chip bonded to redistribution line 68. Then, a material such as bottom filler 56 ( Figure 11 Not shown, refer to Figure 12 ) to seal the RC component 50. The bottom filler 56 may have some portions located directly above the RC component 50, such as Figure 12 , or may be removed from the area directly above the RC assembly 50 .

[0061] As shown by voltage conduction path 98 , RC component 50 is also inserted into the path for conducting the voltage output from IVR die 32 to package assembly 84 and can therefore reduce transient overshoot.

[0062] Figure 12 Shown Figure 11 FIG. 9 is an enlarged view of a portion of package 94 in FIG. 1 , wherein the portion shown includes RC component 50 . Redistribution lines 68 are shown as metal vias including metal lines and interconnecting metal lines.

[0063] Figure 13 94 according to an alternative embodiment of the present disclosure. The IVR die 32 is located in the redistribution structure 64 and may or may not be in contact with the dielectric layer 66. The details of the placement of the IVR die 32 may be as described above. Figure 5 and Figure 6 The placement of the RC assembly 50 shown in FIG is substantially the same and the details are not repeated here. The IVR die 32 may be encapsulated in an encapsulant 56 ( Figure 14 ), or may be closely positioned in an opening in redistribution structure 64 and thus in physical contact with dielectric layer 66. IVR die 32 may or may not be in physical contact with redistribution lines 68. In accordance with some embodiments, IVR die 32 may be flip-chip bonded to redistribution lines 68.

[0064] RC assembly 50 is located in encapsulant 74. According to some embodiments, RC assembly 50 is placed over redistribution structure 64 (e.g., via die attach film 54), and then RC assembly 50, device die 72, and via 70 are encapsulated in encapsulant 74. As shown by voltage conduction path 98, RC assembly 50 is also located in the path for conducting the voltage output from IVR die 32 to package assembly 94, and thus can reduce transient overshoot.

[0065] Figure 14 Shown Figure 13 FIG. 9 is an enlarged view of a portion of package 94 in FIG. 1 , wherein the portion shown includes IVR die 32 and RC assembly 50. According to some embodiments, IVR die 32 is surrounded by an encapsulant (such as an underfill) 33. Underfill 33 may have a portion located directly above IVR die 32, such as Figure 14 Optionally, the underfill 33 does not have any portion directly above the IVR die 32 .

[0066] Figure 15 A cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure is shown. Both the IVR die 32 and the RC assembly 50 are located within the encapsulant 74 and are at the same level as the device die 70, which may include an LSI die 70. As shown by the voltage conduction path 98, the RC assembly 50 is also substantially located in the path for conducting the voltage output from the IVR die 32 to the package assembly 90, and thus can reduce transient overshoot.

[0067] Figure 16 A cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure is shown. The IVR die 32 is located within the dielectric core 38, which is similar to the Figure 9 The details of the placement of the IVR die 32 can be the same as those shown in FIG. Figure 2 and Figure 3 The details of the placement shown in are substantially the same and the details will not be repeated here.

[0068] According to these embodiments, RC component 50 is located in underfill 88. RC component 50 can be bonded to redistribution structure 64 before package assembly 82 is bonded to package substrate 61 ′. As shown by voltage conduction path 98, RC component 50 is also located in the path for conducting the voltage output from IVR die 32 to package assembly 84, and thus can reduce transient overshoot.

[0069] Figure 17 1 shows a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. The RC assembly 50 is located within the dielectric core 38. The placement of the RC assembly 50 may be as follows: Figure 2 and Figure 3 The placement of the IVR die 32 shown in FIG. 1 is substantially the same and the details are not repeated here.

[0070] IVR die 32 is bonded to the bottom of package substrate 61' and may be encapsulated in an underfill that fills the gap between package substrate 61' and package assembly 92. As shown by voltage conduction path 98, RC component 50 is also located in the path for conducting the voltage output from IVR die 32 to package assembly 84 and may therefore reduce transient overshoot.

[0071] Figure 18 A cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure is shown. The RC assembly 50 is located in the dielectric core 38, which is Figure 17 The details of the placement of the RC assembly 50 may be the same as shown in FIG. Figure 2 and Figure 3 The placement of the IVR die 32 in FIG. 1 is substantially the same and the details are not repeated here.

[0072] On the other hand, the IVR die 32 is located above the RC assembly 50. According to some embodiments, the IVR die 32 is placed in the redistribution structure 40 and may or may not be located in the underfill. The details of placing the IVR die 32 may be as follows: Figure 5 and Figure 6 The placement of the RC assembly 50 shown in FIG. 5 is substantially the same and the details are not repeated here.

[0073] As shown by voltage conduction path 98, although RC assembly 50 is located below IVR die 32 and thus the path for conducting the output voltage from IVR die 32 to package assembly 84 increases, this embodiment has increased design flexibility and the IVR die 32 and RC assembly 50 have the flexibility to be placed in locations where component density is low and more spacing is available. The increase in conduction path is minimal.

[0074] In the above embodiments, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing can be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in combination with test methods that combine intermediate verification of known good dies to increase yield and reduce costs.

[0075] Embodiments of the present disclosure have several advantageous features. By inserting an RC component into the conduction path between the IVR die and the consumer, voltage transient overshoots can be reduced. There is minimal increase in parasitic inductance because the RC component is located in the voltage conduction path.

[0076] According to some embodiments of the present disclosure, a method includes: placing an integrated voltage regulator in a first package assembly; placing an RC assembly in a second package assembly; electrically connecting the RC assembly to the integrated voltage regulator; and electrically connecting a first device die to the RC assembly, wherein the RC assembly is located in an electrical path connecting the integrated voltage regulator to the first device die. In one embodiment, the RC assembly is located above the integrated voltage regulator, and wherein the first device die is also located above the integrated voltage regulator.

[0077] In an embodiment, the method further includes: forming a first redistribution structure, wherein the integrated voltage regulator is placed above the first redistribution structure; sealing the integrated voltage regulator in a dielectric core, wherein the first redistribution structure and the dielectric core together form a first package component; and forming a second redistribution structure as a second package component, wherein the second package component is located above the integrated voltage regulator and is electrically coupled to the integrated voltage regulator, wherein the first redistribution structure, the sealant, and the second redistribution structure together form a package substrate.

[0078] In one embodiment, the integrated voltage regulator is bonded to the first redistribution structure via a die attach film, and the integrated voltage regulator is electrically connected to the RC component via the second redistribution structure. In one embodiment, the RC component is positioned within the second redistribution structure. In one embodiment, forming the second redistribution structure includes forming a plurality of dielectric layers and a plurality of redistribution lines within the plurality of dielectric layers, and the method further includes forming openings in the plurality of dielectric layers, wherein the RC component is positioned within the openings.

[0079] In an embodiment, the method further includes: disposing a sealant in the opening to seal the RC component therein. In an embodiment, the method further includes: forming a redistribution structure, including forming a plurality of dielectric layers and forming a plurality of redistribution lines in the plurality of dielectric layers; and forming an opening in the plurality of dielectric layers, wherein the integrated voltage regulator is placed in the opening. In an embodiment, the method further includes: disposing a sealant in the opening to seal the integrated voltage regulator therein.

[0080] In an embodiment, the method further includes bonding a local silicon interconnect die over the RC assembly; and bonding a second device die over the local silicon interconnect die, wherein the local silicon interconnect die is configured to electrically bridge the first device die to the second device die.

[0081] According to some embodiments of the present disclosure, a structure includes: an integrated voltage regulator; an RC component located above and electrically coupled to the integrated voltage regulator; a first device die located above the integrated voltage regulator and the RC component; a first electrical connection path connecting the integrated voltage regulator to an input of the RC component; and a second electrical connection path connecting an output of the RC component to the first device die. In some embodiments, the structure further includes a package substrate, wherein both the integrated voltage regulator and the RC component are embedded in the package substrate.

[0082] In an embodiment, the package substrate includes: a first redistribution structure; a dielectric core located above the first redistribution structure, wherein the integrated voltage regulator is located in the dielectric core; and a second redistribution structure located above the dielectric core, wherein the RC component is located in the second redistribution structure.

[0083] In an embodiment, the structure further includes: a packaging substrate comprising: a first redistribution structure, wherein the integrated voltage regulator is attached to a bottom surface of the first redistribution structure; a dielectric core located above the first redistribution structure, wherein the RC component is located in the dielectric core; and a second redistribution structure located above the dielectric core and the RC component.

[0084] In an embodiment, the RC component comprises a plurality of RC units each comprising a resistor and a capacitor connected to the resistor. In an embodiment, the RC component is a single RC component comprising a resistor and a capacitor connected to the resistor.

[0085] According to some embodiments of the present disclosure, a structure includes: a packaging substrate, including: a first redistribution structure; a dielectric core, located above the first redistribution structure; a second redistribution structure, located above the dielectric core; a plurality of through-vias, located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator, located in the dielectric core; and an RC component, located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a packaging component, located above the packaging substrate and bonded to the packaging substrate, wherein the packaging component includes a device die electrically connected to the RC component.

[0086] In one embodiment, the RC component is located in the second redistribution structure. In one embodiment, the second redistribution structure includes: a plurality of dielectric layers, wherein the RC component is located in the plurality of dielectric layers; and a plurality of redistribution lines located in the plurality of dielectric layers. In one embodiment, the structure further includes: an underfill located in the plurality of dielectric layers, wherein the RC component is also located in the underfill.

[0087] Some embodiments of the present application provide a method for forming a packaging structure, comprising: placing an integrated voltage regulator in a first packaging component; placing an RC component in a second packaging component; electrically connecting the RC component to the integrated voltage regulator; and electrically connecting a first device die to the RC component, wherein the RC component is located in an electrical path connecting the integrated voltage regulator to the first device die.

[0088] In some embodiments, the RC assembly is located above the integrated voltage regulator, and wherein the first device die is also located above the integrated voltage regulator. In some embodiments, the method further includes: forming a first redistribution structure, wherein the integrated voltage regulator is located above the first redistribution structure; encapsulating the integrated voltage regulator in a dielectric core, wherein the first redistribution structure and the dielectric core together form the first package assembly; and forming a second redistribution structure as the second package assembly, wherein the second package assembly is located above and electrically coupled to the integrated voltage regulator, wherein the first redistribution structure, the encapsulant, and the second redistribution structure together form a package substrate. In some embodiments, the integrated voltage regulator is bonded to the first redistribution structure via a die attach film, and wherein the integrated voltage regulator is electrically connected to the RC assembly via the second redistribution structure. In some embodiments, the RC assembly is located in the second redistribution structure. In some embodiments, forming the second redistribution structure includes forming a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers, and the method further includes: forming openings in the plurality of dielectric layers, wherein the RC assembly is located in the openings. In some embodiments, the method further comprises: disposing an encapsulant in the opening to seal the RC assembly therein. In some embodiments, the method further comprises: forming a redistribution structure, comprising forming a plurality of dielectric layers and forming a plurality of redistribution lines in the plurality of dielectric layers; and forming an opening in the plurality of dielectric layers, wherein the integrated voltage regulator is positioned in the opening. In some embodiments, the method further comprises: disposing an encapsulant in the opening to seal the integrated voltage regulator therein. In some embodiments, the method further comprises: bonding a local silicon interconnect die over the RC assembly; and bonding a second device die over the local silicon interconnect die, wherein the local silicon interconnect die is configured to electrically bridge the first device die to the second device die.

[0089] Other embodiments of the present application provide a packaging structure including: an integrated voltage regulator; an RC component located above the integrated voltage regulator and electrically coupled to the integrated voltage regulator; a first device die located above the integrated voltage regulator and the RC component; a first electrical connection path connecting the integrated voltage regulator to the input end of the RC component; and a second electrical connection path connecting the output end of the RC component to the first device die.

[0090] In some embodiments, the package structure further comprises: a package substrate, wherein the integrated voltage regulator and the RC component are both embedded in the package substrate. In some embodiments, the package substrate comprises: a first redistribution structure; a dielectric core located above the first redistribution structure, wherein the integrated voltage regulator is located in the dielectric core; and a second redistribution structure located above the dielectric core, wherein the RC component is located in the second redistribution structure. In some embodiments, the package structure further comprises: a package substrate comprising: a first redistribution structure, wherein the integrated voltage regulator is attached to a bottom surface of the first redistribution structure; a dielectric core located above the first redistribution structure, wherein the RC component is located in the dielectric core; and a second redistribution structure located above the dielectric core and the RC component.

[0091] In some embodiments, the RC component includes a plurality of RC units, each including a resistor and a capacitor connected to the resistor. In some embodiments, the RC component is a single RC component including a resistor and a capacitor connected to the resistor.

[0092] Some other embodiments of the present application provide a packaging structure, comprising: a packaging substrate, comprising: a first redistribution structure; a dielectric core, located above the first redistribution structure; a second redistribution structure, located above the dielectric core; a plurality of through-holes, located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator, located in the dielectric core; and an RC component, located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a packaging component, located above the packaging substrate and bonded to the packaging substrate, wherein the packaging component includes a device die electrically connected to the RC component.

[0093] In some embodiments, the RC component is located in the second redistribution structure. In some embodiments, the second redistribution structure includes: a plurality of dielectric layers, wherein the RC component is located in the plurality of dielectric layers; and a plurality of redistribution lines located in the plurality of dielectric layers. In some embodiments, the package structure further includes: an underfill located in the plurality of dielectric layers, wherein the RC component is also located in the underfill.

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a package structure, comprising: placing an integrated voltage regulator in the first package assembly; Place the RC component in the second package component; electrically connecting the RC component to the integrated voltage regulator; as well as A first device die is electrically connected to the RC assembly, wherein the RC assembly is located in an electrical path connecting the integrated voltage regulator to the first device die.

2. The method according to claim 1, wherein The RC component is located above the integrated voltage regulator, and wherein the first device die is also located above the integrated voltage regulator.

3. The method according to claim 1, further comprising: forming a first redistribution structure, wherein the integrated voltage regulator is placed above the first redistribution structure; encapsulating the integrated voltage regulator in a dielectric core, wherein the first redistribution structure and the dielectric core together form the first package assembly; and A second redistribution structure is formed as the second package component, the second package component being located above and electrically coupled to the integrated voltage regulator, wherein the first redistribution structure, the encapsulant, and the second redistribution structure together form a package substrate.

4. The method according to claim 3, wherein: The integrated voltage regulator is bonded to the first redistribution structure through a die attach film, and wherein the integrated voltage regulator is electrically connected to the RC component through the second redistribution structure.

5. The method according to claim 3, wherein The RC component is placed in the second redistribution structure.

6. The method according to claim 3, wherein: Forming the second redistribution structure includes forming a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers, and the method further includes: Openings are formed in the plurality of dielectric layers, wherein the RC component is placed in the openings.

7. The method according to claim 6, further comprising: A sealant is disposed in the opening to seal the RC assembly therein.

8. The method according to claim 1, further comprising: forming a redistribution structure, including forming a plurality of dielectric layers and forming a plurality of redistribution lines in the plurality of dielectric layers; as well as Openings are formed in the plurality of dielectric layers, wherein the integrated voltage regulator is placed in the openings.

9. A packaging structure comprising: Integrated voltage regulator; an RC component located above and electrically coupled to the integrated voltage regulator; a first device die located above the integrated voltage regulator and the RC component; a first electrical connection path connecting the integrated voltage regulator to the input terminal of the RC component; as well as A second electrical connection path connects the output end of the RC component to the first device die.

10. A packaging structure comprising: Package substrate, including: First redistribution structure; a dielectric core located above the first redistribution structure; a second redistribution structure located above the dielectric core; a plurality of through-vias located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator located in the dielectric core; and an RC component located above and electrically connected to the integrated voltage regulator; and A package assembly is located over and bonded to the package substrate, wherein the package assembly includes a device die electrically connected to the RC assembly.

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