Semiconductor device and packaging method of semiconductor device

Abstract

The invention provides a semiconductor device and a packaging method of the semiconductor device, and belongs to the technical field of semiconductor manufacturing processes, the semiconductor device comprises a semiconductor main body, a metal interconnection layer and a dielectric layer which are sequentially arranged from bottom to top, and the dielectric layer is provided with a through hole for wafer manufacturing. And the redistribution layer interconnects signals with the metal interconnection layer through the through holes. According to the invention, the redistribution layer packaged by the wafer is directly interconnected with the metal interconnection layer through the through holes, a top metal layer does not need to be manufactured by the wafer, and the cost of manufacturing a circuit layer by the wafer of the semiconductor is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing processes, and in particular to a semiconductor device and a method for packaging the semiconductor device. Background Art

[0002] The semiconductor manufacturing process covers multiple steps including wafer preparation, photolithography, etching, doping, thin film deposition, chemical mechanical polishing, and wafer packaging. Wafer-Level Packaging (WLP) is a key step in semiconductor manufacturing. The packaging process is completed directly on the wafer and then cut into individual chips. A metal layer is deposited on the wafer surface, and circuit traces are formed through photolithography and etching. The chip's I / O pads are rearranged to obtain a redistribution layer (RDL). Therefore, it is necessary to provide a method to reduce the cost of wafer packaging. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for packaging the semiconductor device, which can reduce the circuit layer cost of semiconductor wafer manufacturing.

[0004] The present invention provides a semiconductor device, comprising: semiconductor body; a metal interconnection layer, provided on the upper surface of the semiconductor body; a dielectric layer, disposed on the upper surface of the metal interconnect layer and provided with wafer-fabricated through-holes; The redistribution layer is arranged on the upper surface of the dielectric layer and interconnects signals with the metal interconnection layer through the through holes.

[0005] As an embodiment, the redistribution layer includes a gate component, a source component, and a drain component, and the gate component, the source component, and the drain component are all disposed above the through hole.

[0006] As an embodiment, the gate component is connected in parallel with the metal interconnection layer through the through hole.

[0007] As an embodiment, the metal interconnection layer includes a gate metal coil and a sealing ring, and the gate metal coil is arranged on the inner ring of the sealing ring.

[0008] As an embodiment, the gate component has an area covering the gate metal coil and the sealing ring.

[0009] As an embodiment, the thickness of the gate assembly is in the range of 8-15 um.

[0010] As an embodiment, the pore size of the through hole is less than 1 micron.

[0011] As an embodiment, the number of layers of the metal interconnection layer is 1.

[0012] As an embodiment, the electrical conductivity of the material of the gate component is higher than that of aluminum.

[0013] As an embodiment, the gate component is made of copper.

[0014] As an embodiment, the semiconductor device is a gallium nitride HEMT.

[0015] The present invention further provides a method for packaging a semiconductor device, for preparing any of the semiconductor devices described above, comprising: Based on the wafer preparation process, a semiconductor body, a metal interconnection layer and a dielectric layer are sequentially arranged, wherein the dielectric layer is provided with a through hole manufactured by the wafer; Based on the wafer packaging process, a redistribution layer is obtained and arranged on the upper surface of the dielectric layer, so that the redistribution layer interconnects signals with the metal interconnection layer through the through holes.

[0016] The present invention provides a semiconductor device and a method for packaging a semiconductor device. The semiconductor device comprises a semiconductor body, a metal interconnect layer, and a dielectric layer, arranged sequentially from bottom to top. The dielectric layer is provided with through-holes fabricated in wafer manufacturing, and a redistribution layer interconnects signals with the metal interconnect layer via the through-holes. This invention utilizes the redistribution layer of the wafer package to directly connect to the metal interconnect layer via the through-holes, eliminating the need for wafer manufacturing of the top metal layer and reducing the cost of semiconductor wafer manufacturing circuit layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a schematic diagram of the structure of a semiconductor device obtained based on wafer manufacturing in the prior art.

[0019] Figure 2 It is a structural schematic diagram of a semiconductor device covered with a redistribution layer obtained based on wafer packaging in the prior art.

[0020] Figure 3 It is a schematic structural diagram of the semiconductor device provided by the present invention.

[0021] Figure 4 It is a local plan view of the metal interconnection layer provided by the present invention.

[0022] Figure 5 This is one of the plan views of the position of the redistribution layer relative to the metal interconnection layer provided by the present invention.

[0023] Figure 6 This is the second plan view of the position of the redistribution layer relative to the metal interconnection layer provided by the present invention.

[0024] Figure 7 It is a flow chart of the semiconductor device packaging method provided by the present invention.

[0025] In the figure, 100 is a semiconductor body, 200 is a metal interconnection layer, 300 is a dielectric layer, 310 is a through hole, and 400 is a redistribution layer. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0027] It should be noted that all actions of acquiring signals, information or data in the present invention are performed in compliance with the corresponding local data protection laws and policies and with authorization from the corresponding device owner.

[0028] The back-end-of-line (BEOL) process in wafer fabrication is a critical stage in integrated circuit manufacturing, achieving internal chip interconnection. It primarily constructs the multi-layer metal interconnect structure between transistor devices. This process begins after the front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes, which involve contact hole fabrication. Its core goal is to use complex micro-nanofabrication techniques to build a three-dimensional interconnect network of metal conductors and dielectric layers layer by layer on the wafer surface, thereby achieving efficient electrical connections for billions of transistors. The BEOL process directly determines a chip's power consumption, signal transmission speed, reliability, and integration density, and is the most challenging stage in modern advanced process nodes (such as 7nm, 5nm, and below). Figure 1 It is a schematic diagram of the structure of a semiconductor device obtained based on wafer manufacturing in the prior art, such as Figure 1 As shown, the existing semiconductor device includes a semiconductor body, a bottom metal layer M1, a dielectric layer, a top metal layer M2 and a passivation layer PASS. The dielectric layer is provided with a plurality of via holes, which connect the bottom metal layer M1 and the top metal layer M2.

[0029] Figure 2Schematic diagram of the structure of a semiconductor device covered with a redistribution layer obtained based on wafer packaging in the prior art, such as Figure 2 As shown, a polyimide layer (PI) is provided on the upper layer of the passivation layer, and a redistribution layer (RDL) is provided above the PI layer. The RDL passes through the polyimide layer and is connected to the bottom metal layer through the top metal layer and through-holes.

[0030] It can be seen that in the existing semiconductor device packaging solutions, a top metal layer needs to be set, and the cost of wafer manufacturing circuit layer has increased. On the other hand, the performance of semiconductor devices is mainly determined by the capabilities of the wafer preparation process. The wafer packaging process is only used to achieve signal interconnection and does not improve the performance of semiconductor devices.

[0031] In this regard, the present invention provides a semiconductor device and a packaging method for a semiconductor device, which does not require a top metal layer, thereby reducing the cost of the wafer manufacturing circuit layer. In a preferred embodiment, it solves the problem that the performance of the semiconductor device is mainly determined based on the capability of the wafer preparation process, and the wafer packaging process is only used to achieve signal interconnection and does not improve the performance of the semiconductor device.

[0032] The technical solution of the present invention is described in detail below with reference to the accompanying drawings. The semiconductor device provided by the present invention may include a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), a high-electron-mobility transistor (HEMT), a modulation-doped field effect transistor (MODFET), etc. HFETs include but are not limited to low-voltage HEMT devices, high-voltage HEMT devices, and radio frequency (RF) HEMT devices.

[0033] Figure 3 Schematic diagram of the structure of the semiconductor device provided by the present invention, such as Figure 3 As shown, the present invention provides a semiconductor device, comprising: a semiconductor body 100; A metal interconnection layer 200 is provided on the upper surface of the semiconductor body 100; The dielectric layer 300 is provided on the upper surface of the metal interconnection layer 200 and is provided with wafer-made through holes 310; The redistribution layer 400 is disposed on the upper surface of the dielectric layer 300 and interconnects signals with the metal interconnection layer 200 through the through-holes 310 .

[0034] Optionally, the semiconductor device is a gallium nitride HEMT, and correspondingly, the semiconductor body 100 includes a gallium nitride substrate, and the substrate is made of Si or SiC.

[0035] The metal interconnect layer 200 is a conductive structure used to connect different transistors and circuit elements in semiconductor devices. It is typically made of metals such as aluminum and copper, or alloys. It is formed into a multi-layered grid through photolithography, deposition, and etching processes. It performs the core functions of transmitting electrical signals and distributing power, reducing signal interference and increasing integration density. Optionally, the metal interconnect layer consists of only one layer, eliminating the need for a top metal layer, reducing the cost of the circuit layer in wafer manufacturing.

[0036] The dielectric layer 300 is an insulating material layer (such as silicon dioxide, silicon nitride, or a low-k dielectric) deposited above the metal interconnect layer 200 in a semiconductor device. It reduces interlayer parasitic capacitance by lowering the dielectric constant (using a low-k dielectric or air gap structure), thereby suppressing signal delay and power consumption. It also provides mechanical stability to support the multi-layer metal stack and prevent metal diffusion from contaminating the device. In advanced manufacturing processes, dielectric layer 300 is formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. Material properties are optimized for different layers (e.g., low-k dielectric for signal layers and high-density dielectric for stress buffering) (e.g., for shallow local interconnects and deep global power layers). This makes it a key packaging element that balances chip speed, power consumption, and reliability.

[0037] The deployment of via holes on the dielectric layer 300 must comprehensively consider signal integrity, process limitations, and reliability: design rules (such as minimum spacing and aperture size) must be used to ensure safe insulation from adjacent wires and the dielectric layer 300 to prevent short circuits or leakage; the via density must be planned based on the circuit function layer, with short straight-through vias 310 preferentially used for high-frequency signal paths to reduce resistance and inductance, while power / ground lines require multiple vias in parallel to reduce impedance and hot spots; the via layout must be optimized through thermomechanical simulation to avoid structural stress cracking caused by differences in material thermal expansion coefficients; a dual damascene process (etching the dielectric hole first and then filling it with metal) or new metals (such as cobalt and ruthenium) must be used to improve step coverage, and redundant hole designs (such as arrayed vias) must be used to enhance yield; and finally, parasitic parameter extraction and electrical verification must be used to balance transmission efficiency and interlayer capacitance / crosstalk.

[0038] In an embodiment of the present invention, the deployment position of the via hole is determined based on the metal interconnection layer 200. Preferably, the aperture of the through hole 310 manufactured by the wafer deployed in the dielectric layer 300 of the present invention is relatively small, at the micron level, less than 1um, preferably 0.6um. Small holes and shorter via paths can reduce parasitic inductance and capacitance, thereby reducing signal interference and noise, which is conducive to improving signal quality. In a preferred embodiment, the present invention adopts a CMP process in terms of IO connection to ensure the flatness of the wafer surface, thereby improving the RDL rewiring capability. The aperture range of traditional RDL through holes is tens of microns, resulting in limited signal layout and inability to bear the Gatebus capability; the present application sets the aperture of the through hole to less than 1 micron, and then fills it through the RDL process. The small size / small pitch through hole 310 can ensure more signals are connected in parallel, realize the RDL Gate bus function, and improve the performance of semiconductor devices.

[0039] The redistribution layer (RDL) 400 deposits metal (such as copper) and dielectric materials (such as polyimide) on the chip surface or package substrate, relocating the chip's originally densely packed I / O pads to locations more suitable for external connections. Using photolithography, electroplating, and etching processes, it forms micron-scale conductors, enabling planar expansion and cross-layer interconnection of signals, power, and ground lines. This optimizes electrical paths, reduces parasitic effects, and supports high-density heterogeneous integration (such as 2.5D / 3D packaging).

[0040] In an embodiment of the present invention, the redistribution layer 400 includes a gate component, a source component and a drain component. The redistribution layer 400 is connected to the metal interconnection layer 200 through the through hole 310, that is, the gate component, the source component and the drain component are directly connected to the metal interconnection layer 200 through the through hole 310, and there is no need to set a top metal layer, which can not only reduce the cost of the wafer manufacturing circuit layer, but also reduce the process steps of preparing the top metal layer.

[0041] It is understood that the semiconductor device provided by the present invention includes, arranged from bottom to top, a semiconductor body 100, a metal interconnect layer 200, and a dielectric layer 300. The dielectric layer 300 is provided with wafer-fabricated vias 310, and the redistribution layer 400 interconnects signals with the metal interconnect layer 200 via the vias 310. The present invention utilizes the wafer-packaged redistribution layer 400 to directly connect to the metal interconnect layer 200 via the vias 310, eliminating the need for wafer-fabricated top metal layers and reducing the cost of semiconductor wafer manufacturing circuit layers.

[0042] Figure 4 is a partial plan view of the metal interconnection layer provided by the present invention, Figure 5 This is one of the plan views of the position of the redistribution layer relative to the metal interconnection layer provided by the present invention. Figure 6This is the second plan view of the position of the redistribution layer relative to the metal interconnection layer provided by the present invention. Figure 4-Figure 6 Preferred embodiments of the present invention are described in detail.

[0043] Based on the above embodiment, as an optional embodiment, the redistribution layer 400 includes a gate component, a source component, and a drain component, and the gate component, the source component, and the drain component are all disposed above the through hole 310 .

[0044] Optionally, the gate assembly is connected in parallel to the metal interconnect layer 200 via the through hole 310. Furthermore, the gate assembly, source assembly, and drain assembly are respectively disposed above their corresponding through holes 310 and electrically connected to the metal layer on the inner surface of the through hole 310.

[0045] The gate assembly includes the gate control bus, a signal line integrated directly with the transistor gate during the front-end-of-line (FEOL) process. It connects multiple gates within the same module. It's typically made of polysilicon (Poly-Si) or metal gate material and fabricated simultaneously with the source / drain (S / D) electrodes. The source assembly includes the source electrode, and the drain assembly includes the drain electrode.

[0046] In an embodiment of the present invention, copper plating is used to route the gate signal, reducing the impedance of the gate signal in parallel. This reduces process costs and improves GaN device performance through wafer packaging and rewiring. Specifically, contact holes are formed on the surface of the gate structure formed in the previous process. The dielectric layer 300 covering the gate is etched through to expose the electrical nodes of the gate polysilicon or metal gate. Subsequently, a low-k dielectric layer 300 is deposited, and photolithography and reactive ion etching (RIE) processes are used to simultaneously define the conductive trenches for the underlying metal layer and the vias 310 connecting to the gate contact holes within the dielectric layer 300. A tantalum / tantalum nitride (Ta / TaN) barrier layer and a copper seed layer are sequentially deposited, followed by photolithographic patterning. Copper is then electrochemically deposited into the vias 310 and trenches. The photoresist and seed layer are then removed, allowing for packaging and rewiring, resulting in a direct interconnection between the underlying metal layer (M1) and the gate.

[0047] Figure 5 and Figure 6 The position of the through hole 310 in FIG is related to the position of the Gate bus. The Gate bus is the gate control bus. S represents the source component and D represents the drain component. According to different design requirements, the gate control bus may or may not wrap around the drain component. If the gate control bus wraps around the drain component (e.g. Figure 5 ), the drain component is flush with the source component. If the gate control bus does not wrap around the drain component (such as Figure 6 ), the drain component crosses the source component.

[0048] It can be understood that the present invention constructs a redistribution layer 400 through a gate component, a source component and a drain component, and the redistribution layer 400 is connected to the metal interconnection layer 200 through a through hole 310, that is, the gate component, the source component and the drain component are directly connected to the metal interconnection layer 200 through the through hole 310, and there is no need to set a top metal layer, which can not only reduce the cost of the wafer manufacturing circuit layer, but also reduce the process steps of preparing the top metal layer.

[0049] Based on the above embodiment, as an optional embodiment, the metal interconnection layer 200 includes a gate metal coil and a sealing ring, and the gate metal coil is arranged on the inner ring of the sealing ring.

[0050] Gate metal coils are metal interconnects used to connect and control the gates of multiple transistors in semiconductor devices. They are typically formed in the back-end-of-line (BEOL) process using low-resistance metals (such as copper or aluminum) and are located within the metal layer. Their core function is to efficiently distribute global signals (such as clocks and enable signals) to gates in different regions, reducing signal latency and power consumption. By optimizing wiring width and spacing, they can achieve a balance between high-density integration and electromigration reliability.

[0051] The sealing ring is a multi-layer metal-dielectric closed structure located at the edge of the semiconductor device. It forms a physical barrier by alternating stacking of metals (such as aluminum and copper) and insulating materials (such as silicon nitride and polyimide). Its core function is to absorb wafer cutting stress, prevent moisture and contaminants from invading the chip, and at the same time relieve the mechanical stress caused by thermal expansion of the package, significantly improving the long-term reliability of the device in harsh environments such as high temperature and high humidity.

[0052] Based on the above embodiment, as an optional embodiment, the area of ​​the gate component covers the gate metal coil and the sealing ring.

[0053] The redistribution layer 400 of the present invention is connected in parallel to the gate metal coil via the through hole 310. The area of ​​the gate component is relatively large and can completely cover the gate metal coil and the seal ring, thereby achieving seal ring position compensation.

[0054] Based on the above embodiment, as an optional embodiment, the thickness of the gate component is in the range of 8-15 μm. Preferably, the thickness of the gate component is 10 μm.

[0055] In the prior art, the thickness of the top metal layer is 3.5 um. The present invention sets the thickness of the gate assembly in the range of 8-15 um, preferably 10 um, which can increase the thickness of the semiconductor device.

[0056] Based on the above embodiment, as an optional embodiment, the material of the gate component has a higher electrical conductivity than aluminum.

[0057] The material of the existing top metal layer is usually aluminum. The present invention sets the material of the gate component to a material with higher electrical conductivity than aluminum, such as copper. The electrical conductivity of copper is higher than that of aluminum, so that the electrical conductivity of the redistribution layer 400 is higher than that of the metal layer, which greatly reduces the resistance of the gate component and improves the performance of the semiconductor device. In addition, since the redistribution layer 400 is obtained based on wafer packaging, this solves the problem that the performance of the semiconductor device is mainly determined by the capability of the wafer preparation process, and the existing wafer packaging process is only used to achieve signal interconnection and does not improve the performance of the semiconductor device.

[0058] The packaging method of the semiconductor device provided by the present invention is described below. The packaging method of the semiconductor device described below and the semiconductor device described above can be referenced to each other.

[0059] Figure 7 Schematic diagram of the process of packaging a semiconductor device provided by the present invention, such as Figure 7 As shown, the present invention also provides a semiconductor device packaging method for preparing any semiconductor device described above, comprising: Step S100 , based on a wafer preparation process, obtain a semiconductor body, a metal interconnection layer and a dielectric layer arranged in sequence, wherein the dielectric layer is provided with a through hole manufactured by the wafer.

[0060] Based on the wafer preparation process, a semiconductor body, a metal interconnect layer and a dielectric layer are arranged in sequence. The dielectric layer is deployed with through-holes for wafer manufacturing. Specifically, the process includes: growing a single crystal silicon ingot by the Czochralski method and cutting and polishing it into wafers; then performing the front-end process, including oxidation to form an insulating layer, photolithography-etching to define the transistor pattern, and ion implantation to dope the source / drain / gate to construct the semiconductor body; then entering the back-end process to stack the metal interconnect layer and the dielectric layer.

[0061] Step S200 : Based on the wafer packaging process, a redistribution layer is obtained and disposed on the upper surface of the dielectric layer, so that the redistribution layer interconnects signals with the metal interconnection layer through the through holes.

[0062] As an embodiment, a semiconductor device includes: Semiconductor body; Optionally, the semiconductor device is a gallium nitride HEMT, and correspondingly, the semiconductor body includes a gallium nitride substrate, and the substrate is made of Si or SiC, which can significantly reduce dislocation defects caused by lattice mismatch and improve the performance and reliability of high-frequency power devices (such as 5G RF chips) and optoelectronic devices (such as blue light lasers).

[0063] The metal interconnect layer is provided on the upper surface of the semiconductor body; the metal interconnect layer is a conductive structure in semiconductor devices used to connect different transistors and circuit elements. It is usually made of metals or alloys such as aluminum and copper. A multi-layer grid is formed through lithography, deposition and etching processes. It undertakes the core functions of transmitting electrical signals and distributing power, which can reduce signal interference and improve integration density.

[0064] The dielectric layer, located on the upper surface of the metal interconnect layer and equipped with wafer-fabricated vias, is an insulating material layer (such as silicon dioxide, silicon nitride, or a low-k dielectric constant material) deposited above the metal interconnect layer in semiconductor devices. It reduces interlayer parasitic capacitance by lowering the dielectric constant (low-k dielectric or air gap structure), thereby suppressing signal delay and power consumption. It also possesses mechanical stability to support multi-layer metal stacks and prevent metal diffusion from contaminating the device. In advanced manufacturing processes, the dielectric layer is formed via chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, with optimized material properties (e.g., low-k dielectric for signal layers and high-density dielectric for stress buffering) for different layers (e.g., shallow local interconnects and deep global power sources). This makes it a key packaging element in balancing chip speed, power consumption, and reliability.

[0065] The deployment of via holes on the dielectric layer must comprehensively consider signal integrity, process limitations and reliability: ensure insulation safety from adjacent wires and dielectric layers through design rules (such as minimum spacing and aperture size) to prevent short circuits or leakage; plan via density based on circuit function layers, and prioritize short straight-through holes for high-frequency signal paths to reduce resistance and inductance, while power / ground lines require multiple holes in parallel to reduce impedance and hot spots; optimize hole layout through thermomechanical simulation to avoid structural stress cracking caused by differences in material thermal expansion coefficients; use dual damascene processes (etching dielectric holes first and then filling them with metal) or new metals (such as cobalt and ruthenium) to improve step coverage, and use redundant hole designs (such as arrayed vias) to enhance yield; and finally, balance transmission efficiency and interlayer capacitance / crosstalk through parasitic parameter extraction and electrical verification.

[0066] The redistribution layer is arranged on the upper surface of the dielectric layer and interconnects signals with the metal interconnection layer through the through holes.

[0067] The redistribution layer (RDL) deposits metal (such as copper) and dielectric materials (such as polyimide) on the chip surface or package substrate, relocating the chip's originally densely packed I / O pads to locations more suitable for external connections. Using photolithography, electroplating, and etching processes, it forms micron-scale conductors, enabling planar expansion and cross-layer interconnection of signals, power, and ground lines. This optimizes electrical paths, reduces parasitic effects, and supports high-density heterogeneous integration (such as 2.5D / 3D packaging).

[0068] In an embodiment of the present invention, the redistribution layer includes a gate component, a source component and a drain component, and the redistribution layer is connected to the metal interconnection layer through a through hole, that is, the gate component, the source component and the drain component are directly connected to the metal interconnection layer through the through hole, and there is no need to set a top metal layer, which can not only reduce the cost of the wafer manufacturing circuit layer, but also reduce the process steps of preparing the top metal layer.

[0069] As an embodiment, the redistribution layer includes a gate component, a source component, and a drain component, and the gate component, the source component, and the drain component are all disposed above the through hole.

[0070] Optionally, the gate component is connected in parallel to the metal interconnect layer via the through hole. Furthermore, the gate component, source component and drain component are respectively arranged above their corresponding through holes and electrically connected to the metal layer on the inner surface of the through hole.

[0071] The gate assembly includes the gate control bus, a signal line directly integrated with the transistor gate during the front-end-of-line (FEOL) process. It connects multiple gates within the same module (such as the word lines of a memory cell). It is typically made of polysilicon (Poly-Si) or metal gate material and is manufactured simultaneously with the source / drain (S / D) electrodes. The source assembly includes the source electrode, and the drain assembly includes the drain electrode.

[0072] As an embodiment, the metal interconnection layer includes a gate metal coil and a sealing ring, and the gate metal coil is arranged on the inner ring of the sealing ring.

[0073] Gate metal coils are metal interconnects used to connect and control the gates of multiple transistors in semiconductor devices. They are typically formed in the back-end-of-line (BEOL) process using low-resistance metals (such as copper or aluminum) and are located within the metal layer. Their core function is to efficiently distribute global signals (such as clocks and enable signals) to gates in different regions, reducing signal latency and power consumption. By optimizing wiring width and spacing, they can achieve a balance between high-density integration and electromigration reliability.

[0074] The sealing ring is a multi-layer metal-dielectric closed structure located at the edge of the semiconductor device. It forms a physical barrier by alternating stacking of metals (such as aluminum and copper) and insulating materials (such as silicon nitride and polyimide). Its core function is to absorb wafer cutting stress, prevent moisture and contaminants from invading the chip, and at the same time relieve the mechanical stress caused by thermal expansion of the package, significantly improving the long-term reliability of the device in harsh environments such as high temperature and high humidity.

[0075] As an embodiment, the gate component has an area covering the gate metal coil and the sealing ring.

[0076] The redistribution layer of the present invention is connected in parallel to the gate metal coil via a through hole. The area of ​​the gate component is relatively large and can completely cover the gate metal coil and the seal ring, thereby achieving seal ring position compensation.

[0077] As an embodiment, the thickness of the gate component is in the range of 8-15 μm. Preferably, the thickness of the gate component is 10 μm.

[0078] In the prior art, the thickness of the top metal layer is 3.5 um. The present invention sets the thickness of the gate assembly in the range of 8-15 um, preferably 10 um, which can increase the thickness of the semiconductor device.

[0079] As an embodiment, the electrical conductivity of the material of the gate component is lower than a preset value.

[0080] The material of the existing top metal layer is usually aluminum. The present invention sets the material of the gate component to a material with lower conductivity than aluminum, such as copper. The electrical conductivity of copper is lower than that of aluminum, so that the electrical conductivity of the redistribution layer is lower than that of the metal layer, which greatly reduces the resistance of the gate component and improves the performance of the semiconductor device. In addition, since the redistribution layer is obtained based on wafer packaging, this solves the problem that the performance of the semiconductor device is mainly determined by the capability of the wafer preparation process, and the existing wafer packaging process is only used to achieve signal interconnection and does not improve the performance of the semiconductor device.

[0081] Spatially relative terms such as "under," "below," "lower," "above," "upper," "lower," "left," "right," etc., as used herein, may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device when in use or in operation in addition to the orientations depicted in the accompanying drawings. The device can be oriented in other ways (rotated 80 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, the component can be directly connected to or coupled to the other component, or there may be intervening components.

[0082] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely as well as instances where the event or situation is close to occurring. As used herein with respect to a given value or a given range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may refer to the positional difference of two surfaces positioned along the same plane being within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of the positional difference positioned along the same plane. When a value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: semiconductor body; a metal interconnection layer, provided on the upper surface of the semiconductor body; a dielectric layer, disposed on the upper surface of the metal interconnect layer and provided with wafer-fabricated through-holes; The redistribution layer is arranged on the upper surface of the dielectric layer and interconnects signals with the metal interconnection layer through the through holes.

2. The semiconductor device according to claim 1, wherein The redistribution layer includes a gate component, a source component and a drain component, and the gate component, the source component and the drain component are all arranged above the through hole.

3. The semiconductor device according to claim 2, wherein The gate component is connected in parallel with the metal interconnection layer through the through hole.

4. The semiconductor device according to claim 2, wherein The metal interconnection layer includes a gate metal coil and a sealing ring, and the gate metal coil is arranged on the inner ring of the sealing ring.

5. The semiconductor device according to claim 4, wherein The gate component has an area covering the gate metal coil and the sealing ring.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that: The thickness of the gate assembly is in the range of 8-15 μm.

7. The semiconductor device according to claim 1, wherein The through hole has a diameter smaller than 1 micron.

8. The semiconductor device according to claim 1, wherein The number of layers of the metal interconnection layer is 1.

9. The semiconductor device according to any one of claims 2 to 5, wherein: The electrical conductivity of the material of the gate component is higher than that of aluminum.

10. The semiconductor device according to any one of claims 2 to 5, characterized in that: The gate component is made of copper.

11. The semiconductor device according to claim 1, wherein The semiconductor device is a gallium nitride HEMT.

12. A method for packaging a semiconductor device, characterized in that: For preparing the semiconductor device according to any one of claims 1 to 11, comprising: Based on the wafer preparation process, a semiconductor body, a metal interconnection layer and a dielectric layer are sequentially arranged, wherein the dielectric layer is provided with a through hole manufactured by the wafer; Based on the wafer packaging process, a redistribution layer is obtained and arranged on the upper surface of the dielectric layer, so that the redistribution layer interconnects signals with the metal interconnection layer through the through holes.

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