Display panel, electronic device, and method for manufacturing display panel

Abstract

A display panel includes: a first substrate layer in which an opening is defined; a pad electrode disposed on the first base layer and exposed to the outside through the opening; a second base layer disposed on the pad electrode and in which a first contact hole is defined; a protective layer disposed on the second base layer and in which a second contact hole overlapping the first contact hole is defined; and a connection electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole. The second contact hole has a width greater than a width of the first contact hole.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display panel, an electronic device, and a method for manufacturing a display panel, and more particularly, to a display panel having improved reliability, an electronic device, and a method for manufacturing a display panel. Background Art

[0002] Electronic devices such as smartphones, tablet personal computers ("PCs"), notebook computers, car navigations, and smart TVs are being developed. The electronic devices include display devices for providing information.

[0003] Display devices are being developed in various forms to satisfy user experience / user interface ("UX / UI") of users. Display devices have been developed to provide a wider display area and a narrower non-display area. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel, an electronic device, and a method for manufacturing the display panel that are manufactured in a simplified method and improve display quality.

[0005] In one embodiment of the present disclosure, a display panel includes: a first base layer having an opening defined therein; a pad electrode disposed on the first base layer and exposed to the outside through the opening; a second base layer disposed on the pad electrode and having a first contact hole defined therein; a protective layer disposed on the second base layer and having a second contact hole overlapping the first contact hole defined therein; and a connecting electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole. The second contact hole has a width greater than that of the first contact hole.

[0006] In an embodiment of the present disclosure, the display panel may further include a base insulating layer interposed between the first base layer and the second base layer, and the third contact hole may be defined in the base insulating layer through the base insulating layer.

[0007] In one embodiment, the third contact hole may have a width different from that of the first contact hole.

[0008] In one embodiment, a first side surface of the second base layer defining the first contact hole and a second side surface of the base insulating layer defining the third contact hole may be aligned with each other.

[0009] In one embodiment, the base insulating layer may include: a first sub-base insulating layer, which is arranged on the first base layer, and the base opening is defined in the first sub-base insulating layer; and a second sub-base insulating layer, which is arranged on the first sub-base insulating layer and the pad electrode, and the pad electrode may be arranged in the base opening.

[0010] In one embodiment, the third contact hole may be defined in the second sub-base insulating layer, and the third contact hole may overlap with the base opening.

[0011] In an embodiment, the pad electrode may include a first portion overlapping the opening and a second portion extending from the first portion in a first direction.

[0012] In one embodiment, the connecting electrode may directly contact the first portion.

[0013] In one embodiment, the connecting electrode may directly contact the second portion.

[0014] In one embodiment, the second base layer may include an organic material.

[0015] In one embodiment, the protective layer may include at least one inorganic layer.

[0016] In one embodiment, the second base layer may have a thickness greater than that of the protective layer.

[0017] In one embodiment, the first base layer may include a display area and a non-display area, and the pad electrode may overlap the non-display area.

[0018] In one embodiment of the present disclosure, an electronic device includes a display panel for displaying an image and a circuit board coupled to the display panel. The display panel includes: a first base layer having an opening defined therein; a pad electrode disposed on the first base layer and exposed to the outside through the opening; a second base layer disposed on the pad electrode and having a first contact hole defined therein; a protective layer disposed on the second base layer and having a second contact hole overlapping the first contact hole defined therein; and a connecting electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole. The second contact hole has a width greater than that of the first contact hole.

[0019] In one embodiment, the display panel may further include: a first base insulating layer disposed on the first base layer; and a second base insulating layer disposed on the first base insulating layer and the pad electrode, and the pad electrode may be disposed in a base opening defined in the first sub-base insulating layer.

[0020] In one embodiment, a third contact hole may be defined in the second sub-base insulating layer, and the third contact hole may have a width different from that of the first contact hole.

[0021] In one embodiment, each of the first contact hole and the second contact hole may overlap with the opening.

[0022] In an embodiment of the present disclosure, the electronic device may further include a metal pattern for electrically connecting the display panel to the circuit board.

[0023] In one embodiment, the display panel may further include a first sub-base insulating layer arranged on the first base layer, the circuit board may include a base film and a bump electrode between the base film and the first sub-base insulating layer, and the bump electrode and the pad electrode may be electrically connected to each other through a metal pattern.

[0024] In one embodiment of the present disclosure, the electronic device may further include an adhesive layer between the bump electrode and the first sub-base insulating layer.

[0025] In one embodiment of the present disclosure, a method for manufacturing a display panel includes: forming a pad electrode on a first preliminary base layer; forming a second preliminary base layer on the first preliminary base layer and the pad electrode; forming a preliminary protective layer on the second preliminary base layer; forming a second base layer having a first contact hole defined therein by etching the second preliminary base layer; and forming a protective layer having a second contact hole defined therein by etching the preliminary protective layer, and forming a connection electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole. The second contact hole has a width greater than that of the first contact hole.

[0026] In one embodiment of the present disclosure, the method further includes forming a base insulating layer interposed between the first preliminary base layer and the second base layer and having the third contact hole defined therein.

[0027] In an embodiment, forming the base insulating layer may include forming a first sub-base insulating layer having a base opening defined therein on the first preliminary base layer, and forming a second sub-base insulating layer on the first sub-base insulating layer and the pad electrode.

[0028] In one embodiment, forming the second sub-base insulating layer may include defining a third contact hole overlapping the first contact hole.

[0029] In one embodiment, defining the third contact hole may be performed simultaneously with defining the first contact hole.

[0030] In one embodiment, defining the third contact hole may be performed after defining the first contact hole, and the third contact hole may have a width smaller than that of the first contact hole.

[0031] In one embodiment, forming the pad electrode may include forming a metal layer on the first sub-base insulating layer, and forming the pad electrode by etching the metal layer.

[0032] In one embodiment, etching the second preliminary base layer and the preliminary protective layer may include defining a first contact hole by performing a first etching process on the preliminary protective layer, and defining a second contact hole by performing a second etching process on the second preliminary base layer.

[0033] In one embodiment, the second etching process may be performed after the first etching process.

[0034] In an embodiment of the present disclosure, the method may further include forming an opening in the first preliminary base layer to expose the pad electrode to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other embodiments, advantages and features of the present disclosure will become more apparent by describing in detail an embodiment of the present disclosure with reference to the accompanying drawings.

[0036] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0037] Figure 2 is an exploded perspective view of an electronic device according to one embodiment of the present disclosure.

[0038] Figure 3 For the Figure 2 A cross-sectional view of the display device taken along line II'.

[0039] Figure 4 FIG. 1 is a cross-sectional view briefly illustrating an embodiment of a display module according to the present disclosure.

[0040] Figure 5 FIG. 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0041] Figure 6 is a cross-sectional view of an embodiment of a display module according to the present disclosure.

[0042] Figure 7 FIG. 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0043] Figure 8 FIG. 1 is an enlarged view illustrating an embodiment of a portion of a display device according to the present disclosure.

[0044] Figure 9A As an example, Figure 8 1 is a cross-sectional view of a portion of the display device taken along line II-II'.

[0045] Figure 9B As an example Figure 9A Magnified view of region AA' illustrated in FIG.

[0046] Figure 10A and Figure 10BAn enlarged plan view illustrating an embodiment of a portion of a display device according to the present disclosure.

[0047] Figure 11 is a cross-sectional view illustrating an embodiment of a portion of a display device according to the present disclosure.

[0048] 12A to 12H is a view illustrating one operation in a method for manufacturing a display device.

[0049] Figure 13A and Figure 13B is a view illustrating one operation in a method for manufacturing a display device. DETAILED DESCRIPTION

[0050] While the present disclosure is susceptible to various modifications and alternative forms, exemplary embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that there is no intention to limit the present disclosure to the particular forms disclosed, but on the contrary, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0051] In the specification, the statement that a first component (or region, layer, section, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, connected to or coupled to the second component, or that a third component is interposed therebetween.

[0052] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportions, and dimensions of components may be exaggerated to effectively describe technical features.

[0053] The term "and / or" includes any and all combinations of one or more of the associated items.

[0054] Although the terms "first," "second," and the like may be used to describe various components, these components should not be construed as being limited by these terms. Terms are used solely to distinguish one component from another. In one embodiment, for example, a first component may also be referred to as a second component, and similarly, a second component may also be referred to as a first component, without departing from the scope and spirit of the present invention. Unless the context clearly indicates otherwise, the singular is intended to include the plural.

[0055] In addition, the terms "below", "at the lower portion", "above", and "upper portion" are used to describe the relationship between components illustrated in the drawings. The terms are relative and are described with reference to the directions indicated in the drawings.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Such terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technical field, and unless explicitly defined herein, should not be interpreted as having an ideal or overly formal meaning.

[0057] It will be further understood that the terms “include” or “have” indicate the presence of the stated features, quantities, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts and / or combinations thereof.

[0058] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device according to one embodiment of the present disclosure. Figure 3 For the Figure 2 A cross-sectional view of the display device taken along line II'.

[0060] refer to Figure 1 In one embodiment of the present disclosure, the electronic device ED may include a display surface DS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0061] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, while the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the shapes of the display area DA and the non-display area NDA may vary.

[0062] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 may be used as a basis for distinguishing between the front and rear surfaces of a member. In this specification, the term "in a plan view" may refer to a state when the display device DD is viewed in the third direction DR3.

[0063] In one embodiment of the present disclosure, the electronic device ED may be a foldable electronic device that folds about a folding axis. The folding axis may be parallel to the first direction DR1 or the second direction DR2, and the folding area may be defined within a portion of the display area DA. The electronic device ED may be in an inner folded state, with the display areas DA facing each other, or in an outer folded state, with the display areas DA facing each other.

[0064] like Figure 2 As illustrated in FIG, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM, and a housing HM. Figure 2 Briefly illustrating the electronic device ED, the electronic device ED may further include a mechanical structure (eg, a hinge) that controls the operation (eg, folding or rolling) of the display device DD.

[0065] The display device DD generates an image IM and detects external input. The display device DD includes a window WM, an upper member UM, a display module DM, a lower member LM, a circuit board (or flexible circuit board) FCB, and a driver chip DIC. The upper member UM includes a member disposed above the display module DM, and the lower member LM includes a member disposed below the display module DM.

[0066] The window WM provides a front surface of the electronic device ED and includes a transmissive area TA and a bezel area BZA. Figure 1 The display area DA and the non-display area NDA of the display surface DS illustrated in FIG are defined by the transmission area TA and the bezel area BZA. The transmission area TA is an area through which an image passes, and the bezel area BZA is an area covering structures / members disposed under the window WM.

[0067] The display module DM includes Figure 1 , and the display area DA and the non-display area NDA are respectively the display area DM-DA and the non-display area DM-NDA corresponding to each other. In the present disclosure, the term “a region / portion corresponds to a region / portion” means that a region / portion overlaps with a region / portion, and does not mean that a region / portion has the same area as that of a region / portion.

[0068] The pad area PA is provided on one side of the non-display area DM-NDA. The pad area PA is an area for electrically coupling (connecting) with the circuit board FCB described below. In one embodiment, the pad area PA may be defined on the rear surface of the display module DM.

[0069] The display module DM has a substantially rectangular shape. In this case, the expression "substantial rectangular shape" includes a shape similar to a rectangle that a user perceives as a rectangle, in addition to a rectangular shape in a mathematical sense. In one embodiment, the substantial rectangular shape may include, for example, a rectangular shape with rounded corners. In addition, for the substantial rectangular shape, the display panel DP (refer to Figure 4 ) is not limited to a straight line, but the edge may include a curved area.

[0070] The upper member UM may include a protective film or an optical film. The optical film may include a polarizer and a retarder to reduce reflection of external light. The lower member LM may include a protective film for protecting the display panel DP, a support member for supporting the display panel DP, or a digitizer. The details of the upper member UM and the lower member LM will be described below.

[0071] The circuit board FCB is provided below the display module DM. The circuit board FCB may be coupled to the rear surface of the display panel DP. The circuit board FCB electrically connects the display panel DP to the main circuit board MCB (refer to FIG. Figure 3 The circuit board FCB includes at least one insulating layer and at least one conductive layer. The conductive layer may include a plurality of signal lines.

[0072] The driving chip DIC may be disposed (eg, mounted) on the circuit board FCB. The driving chip DIC may include a driving circuit to drive pixels of the display panel DP, such as a data driving circuit. Figure 2 The driving chip DIC is shown as being disposed (eg, mounted) on the circuit board FCB, but the present disclosure is not limited thereto. In one embodiment, for example, the driving chip DIC may be disposed (eg, mounted) on the display module DM or the main circuit board MCB.

[0073] The electronic module EM may include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, or an external interface module. The electronic module EM may include a main circuit board, and each module may be disposed (e.g., mounted) on the main circuit board, or may be electrically connected to the main circuit board via a flexible circuit board. The electronic module EM is electrically connected to the power supply module PSM.

[0074] Although not separately illustrated, the electronic device ED may further include an electronic optical module. The electronic optical module may be an electronic component that outputs or receives optical signals. The electronic optical module may include a camera module and / or a proximity sensor. The camera module may capture external images through a portion of the display panel DP.

[0075] Figure 2 The housing HM illustrated in FIG is coupled to the display device DD (particularly the window WM) to receive other modules. Although the housing HM is illustrated as having an integral shape, the present disclosure is not limited thereto. The housing HM may include a plurality of portions (e.g., side edge portions and a bottom portion) coupled to each other.

[0076] refer to Figure 3 The window WM may include a base substrate BS and a frame pattern BM disposed on the bottom surface of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin film glass substrate, a protective film disposed on the thin film glass substrate, and an adhesive layer bonding the thin film glass substrate to the protective film.

[0077] The frame pattern BM used as a color light-blocking film can be formed by a coating scheme. The frame pattern BM may include a base material and a dye or pigment mixed with the base material. Figure 1 The non-display area NDA and Figure 2 The window WM may overlap the frame area BZA illustrated in FIG. The frame pattern BM may be provided on the bottom surface of the base substrate BS. When the base substrate BS has a multi-layer structure, the frame pattern BM may be located between interfaces defined by the multiple layers. In one embodiment, for example, the frame pattern BM may be located between the thin film glass substrate and the protective film. Although not separately illustrated, the window WM may further include at least one of a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer on the top surface of the base substrate BS.

[0078] The upper member UM may include an upper film. The upper film may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate.

[0079] The upper film can absorb external impacts applied to the front surface of the display device DD. In one embodiment of the present disclosure, the display module DM may include a color filter that functions as an anti-reflection member and replaces the polarizing film. This can reduce the impact strength on the front surface of the display device DD. The upper film can compensate for the reduced impact strength by applying the color filter.

[0080] Upper component UM and border area BZA (reference Figure 2 ) and the transmissive area TA (reference Figure 2 ) overlap. The upper member UM may overlap only a portion of the frame area BZA. A portion of the frame pattern BM may be exposed from the upper member UM. In one embodiment of the present disclosure, the upper member UM may be omitted. In one embodiment of the present disclosure, the upper member UM may be replaced with an optical film including a polarizer and a retarder.

[0081] Although not illustrated, an adhesive layer may be further interposed between the upper member UM and the window WM to bond the upper member UM to the window WM. The adhesive layer may be a pressure-sensitive adhesive film ("PSA") or an optically clear adhesive ("OCA").

[0082] The display module DM is disposed below the upper member UM. The display module DM overlaps the bezel area BZA and the transmissive area TA. The display module DM may completely overlap the upper member UM in the bezel area BZA. The side surfaces of the display module DM may be aligned with the side surfaces of the upper member UM. In a plan view, the edges of the display module DM may be aligned with the edges of the upper member UM.

[0083] The pad area PA of the display module DM may overlap with the upper member UM in the bezel area BZA. The portion of the display module DM corresponding to the pad area PA may be bonded to the bottom surface of the upper member UM via an adhesive layer. Since the pad area PA overlaps with the upper member UM, and the portion of the display module DM overlapping the pad area BA is bonded to the upper member UM, the upper member UM can adequately support the pad area PA when the circuit board FCB is bonded to the pad area PA.

[0084] The lower member LM may include a lower film PF and a cover panel CP. In one embodiment, the lower member LM may further include a support plate and a digitizer.

[0085] The lower film PF may expose the pad area PA of the display module DM. The lower film PF may be smaller in size than the display module DM. In one embodiment, for example, the lower film PF may overlap only with the display area DM-DA of the display module DM. An open area PF-OP may be defined in the lower film PF to correspond to the non-display area DM-NDA. In an alternative embodiment, the lower film PF may have dimensions substantially corresponding to those of the display module DM. In this case, the open area PF-OP may be defined in the lower film PF to correspond to the pad area PA. The pad area PA may be exposed through the open area PF-OP.

[0086] The lower film PF may expose the pad area PA. The lower film PF may have an area smaller than that of the display module DM. In one embodiment, the lower film PF may, for example, overlap only with the display area DM-DA. The lower film PF may have an area substantially equal to that of the display module DM. An open area PF-OP may be defined in the lower film PF to correspond to the pad area PA. The pad area PA may be exposed through the open area PF-OP.

[0087] The cover panel CP may be disposed below the lower film PF. The cover panel CP may increase resistance to compressive forces generated by external pressure. Thus, the cover panel CP may be used to prevent deformation of the display panel DP. The cover panel CP may include a flexible plastic material, such as polyimide or polyethylene terephthalate. In addition, the cover panel CP may be a colored film with relatively low light transmittance. The cover panel CP may absorb light incident from the outside. In one embodiment, for example, the cover panel CP may be a black synthetic resin film. When the display device DD is viewed from the upper portion of the window WM, the user may not be able to see the components arranged below the cover panel CP.

[0088] Although not illustrated, a support plate may be further disposed below the cover panel CP. The support plate may include a metal material having higher strength. The support plate may include a fiber-reinforced composite material. The support plate may include reinforcing fibers disposed within the matrix component. The reinforcing fibers may be carbon fibers or glass fibers. The matrix component may include a polymer resin. The matrix component may include a thermoplastic resin. In one embodiment, the matrix component may include, for example, a polyamide resin or a polypropylene resin. In one embodiment, the fiber-reinforced composite material may be, for example, carbon fiber reinforced plastic ("CFRP") or glass fiber reinforced plastic ("GFRP").

[0089] A main circuit board MCB may be provided on the bottom surface of the circuit board FCB. The circuit board FCB may include an insulating film and conductive wires disposed (e.g., mounted) on the insulating film. The main circuit board MCB may include signal lines and electronic devices, not illustrated. The electronic devices may be connected to the signal lines to electrically connect to the display module DM. The electronic devices generate various electrical signals, such as signals for generating images or signals for sensing external inputs, and process the sensed signals. A single main circuit board MCB may be provided to correspond to each electrical signal to be generated or processed. In one embodiment, for example, at least three main circuit boards MCB may be provided, but the present disclosure is not limited to a specific embodiment.

[0090] Although not illustrated, the main circuit board MCB may include a driver chip DIC (refer to FIG. Figure 2 ).

[0091] refer to Figure 2 and Figure 3 The circuit board FCB is bonded to the rear surface of the display module DM (rear surface bonding). The non-display area DM-NDA of the display module DM is not bent, thereby preventing malfunctions caused by bending of the non-display area DM-NDA of the display module DM. Furthermore, the area of ​​the bezel area BZA of the window WM covering the non-display area DM-NDA of the display module DM can be reduced.

[0092] Figure 4 FIG. 1 is a cross-sectional view briefly illustrating an embodiment of a display module according to the present disclosure.

[0093] refer to Figure 4 The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display device layer DP-ED, and an encapsulation layer TFE.

[0094] The circuit layer DP-CL is disposed on the top surface of the base layer BL. The base layer BL may be a flexible substrate that allows bending, folding, or curling. The base layer BL may be a glass substrate, a metal substrate, or a polymer substrate. However, the present disclosure is not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. Basically, the base layer BL may have the same shape as the display panel DP.

[0095] The base layer BL may have a multilayer structure. In one embodiment, the base layer BL may include, for example, a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed therebetween. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide resin, but the present disclosure is not particularly limited thereto.

[0096] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include multiple insulating layers, multiple semiconductor patterns, multiple conductive patterns, and signal lines. The circuit layer DP-CL may include pixel driver circuits. Hereinafter, unless otherwise indicated, component 'A' and component 'B' may be disposed in the same layer, which is interpreted as meaning that component 'A' and component 'B' are formed in the same process, include the same material, or have the same stacked structure. Conductive patterns or semiconductor patterns disposed in the same layer may be interpreted as described above.

[0097] The display device layer DP-ED may be disposed on the circuit layer DP-CL. The display device layer DP-ED may include a light-emitting element. In one embodiment, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro light-emitting diode ("micro-LED"), or a nano-LED.

[0098] The encapsulation layer (TFE) may be disposed on the display device layer (DP-ED). The TFE layer protects the display device layer (DP-ED), i.e., the light-emitting element, from foreign substances such as moisture, oxygen, and dust particles. The TFE layer may include at least one encapsulating inorganic layer. The TFE layer may comprise a stacked structure of a first encapsulating inorganic layer, an encapsulating organic layer, and a second encapsulating inorganic layer.

[0099] The input sensing layer ISL may be directly disposed on the display panel DP. The input sensing layer ISL may detect user input using, for example, electromagnetic induction or capacitance. The display panel DP and the input sensing layer ISL may be formed through a continuous process. In this case, the term "directly disposed" may indicate that no third component is interposed between the input sensing layer ISL and the display panel DP. In other words, a separate adhesive layer is not interposed between the input sensing layer ISL and the display panel DP.

[0100] Figure 5 The cross-sectional view briefly illustrates an embodiment of a display panel according to the present disclosure. Figure 6 FIG. 1 is a cross-sectional view briefly illustrating an embodiment of a display module according to the present disclosure.

[0101] like Figure 5 As shown in FIG. 1 , the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The plurality of pixels PX are arranged in the display area DM-DA. Each of the pixels PX includes a light emitting element and a pixel drive circuit connected thereto. The scan drive circuit SDC may include a plurality of signal lines SGL, and the pixel drive circuit may include Figure 4 The circuit layer DP-CL is illustrated in FIG.

[0102] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit generates a plurality of scan signals and sequentially outputs the scan signals to a plurality of scan lines GL described later. The scan drive circuit SDC may further include a light emitting drive circuit separate from the gate drive circuit. The light emitting drive circuit may output scan signals to scan lines in another group.

[0103] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit, such as a relatively low temperature polysilicon (“LTPS”) process or a relatively low temperature polycrystalline oxide (“LTPO”) process.

[0104] The plurality of signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each scan line GL is connected to an associated pixel PX among the pixels PX, and each data line DL is connected to an associated pixel PX among the pixels PX. The power lines PL are connected to the plurality of pixels PX. The data lines DL can provide data signals to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit SDC.

[0105] A plurality of power lines PL may be provided. In one embodiment, the power lines PL may include, for example, a first power line for receiving a first power voltage and a second power line for receiving a second power voltage having a higher level than that of the first power voltage. The first power voltage is supplied to the pixel PX through the first power line, and the second power voltage is supplied to the pixel PX through the second power line. Although Figure 5 Although one control signal line CSL is provided as an example, a plurality of control signal lines CSL may be provided.

[0106] The scan lines GL, data lines DL, and power lines PL may overlap the display area DM-DA and the non-display area DM-NDA, and the control signal lines CSL may overlap the non-display area DM-NDA. The end portions of the plurality of signal lines SGL may be aligned with one another on one side of the non-display area DM-NDA. Although each of the plurality of signal lines SGL may be integral, each of the plurality of signal lines SGL may include a plurality of portions disposed in mutually different layers. The mutually different portions separated from one another by an insulating layer may be connected to one another via contact holes defined through the insulating layer. In one embodiment, for example, the data line DL may include a first portion disposed in the display area DM-DA and a second portion disposed in the non-display area DM-NDA and provided in a layer different from that of the first portion. The first portion and the second portion may include mutually different materials and may have mutually different stacking structures.

[0107] The plurality of signal lines SGL may be electrically connected to the pad area PA. Figure 3 The circuit board FCB is shown in FIG.

[0108] Figure 6 Examples and Figure 5 sectional view of the display module DM corresponding to the pixel PX.

[0109] The pixel driving circuit PC for driving the light-emitting element LD may include multiple driving elements. The pixel driving circuit PC may include multiple transistors S-TFT, O-TFT, and a capacitor Cst. The multiple transistors S-TFT and O-TFT may include silicon transistors S-TFT and oxide transistors O-TFT. Figure 6 A silicon transistor S-TFT and an oxide transistor O-TFT are exemplified. Figure 6 The pixel driving circuit PC is provided for illustration purposes only, and the configuration of the pixel driving circuit PC is not limited thereto. The pixel driving circuit PC may include only one type of transistor among a silicon transistor S-TFT and an oxide transistor O-TFT.

[0110] Figure 6 The base layer BL is illustrated as a single layer. The base layer BL may include a synthetic resin such as polyimide. The base layer BL may be formed by coating a synthetic resin layer on a working substrate (or carrier substrate). When the display module DM is completely formed through subsequent processes, the working substrate may be removed.

[0111] refer to Figure 6A first blocking electrode (or blocking electrode) BML1 may be disposed on the base layer BL. The first blocking electrode BML1 may receive a bias voltage. The first blocking electrode BML1 may receive a first power supply voltage. The first blocking electrode BML1 may block the potential caused by polarization from affecting the silicon transistor S-TFT. The first blocking electrode BML1 may block external light from reaching the silicon transistor S-TFT. In one embodiment of the present disclosure, the first blocking electrode BML1 may be a floating electrode isolated from another electrode or line. The first blocking electrode BML1 may be disposed corresponding to the silicon transistor S-TFT. The first blocking electrode BML1 may include a metal, such as molybdenum (Mo).

[0112] The isolation layer BRL may be disposed on the base layer BL and the first barrier electrode BML1. The isolation layer BRL may prevent the introduction of foreign substances from the outside. The isolation layer BRL may include at least one inorganic layer. The isolation layer BRL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may include multiple silicon oxide layers, and the silicon nitride layer may include multiple silicon nitride layers. The silicon oxide layers and the silicon nitride layers may be alternately stacked.

[0113] The buffer layer BFL may be disposed on the isolation layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BL to the first semiconductor pattern SC1 disposed on the base layer BL. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0114] The first semiconductor pattern SC1 may be disposed on the buffer layer BFL. The first semiconductor pattern SC1 may include a silicon semiconductor. In one embodiment, the silicon semiconductor may include, for example, amorphous silicon or polysilicon. In one embodiment, the first semiconductor pattern SC1 may include, for example, low-temperature polysilicon.

[0115] The first semiconductor pattern SC1 may have different electrical characteristics depending on whether the first semiconductor pattern SC1 is doped. The first semiconductor pattern SC1 may include a first region with higher conductivity and a second region with lower conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be undoped or may be doped at a lower concentration than the first region. In one embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0116] The conductivity of the first region may be higher than that of the second region. The first region may essentially function as an electrode or a signal line. The second region may actually correspond to a channel region (active region) of a transistor. In other words, a portion of the first semiconductor pattern SC1 may be a channel of the transistor, another portion of the first semiconductor pattern SC1 may be a source or drain of the transistor, and yet another portion of the first semiconductor pattern SC1 may be a connection electrode or a connection signal line.

[0117] The source region SE1, the channel region AC1 (or active region), and the drain region DE1 of the silicon transistor S-TFT may be formed by the first semiconductor pattern SC1. When viewed in a cross-sectional view, the source region SE1 and the drain region DE1 may extend in opposite directions from the channel region AC1.

[0118] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. The inorganic layer of the circuit layer DP-CL described later and the first insulating layer 10 may have a single-layer structure or a multi-layer structure and may include at least one of the above materials, but the present disclosure is not limited thereto.

[0119] The gate electrode GT1 of the silicon transistor S-TFT is disposed on the first insulating layer 10. The gate electrode GT1 may be a portion of a metal pattern. The gate electrode GT1 overlaps the channel region AC1. The gate electrode GT1 may be a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the storage capacitor (or capacitor) Cst is disposed on the first insulating layer 10. Figure 6 Different from the example shown in FIG. 5 , the first electrode CE10 may have an integral shape with the gate electrode GT1 .

[0120] The second insulating layer 20 may be provided on the first insulating layer 10 and may cover the gate electrode GT1. In one embodiment of the present disclosure, an upper electrode overlapping the gate electrode GT1 may be further provided on the second insulating layer 20. A second electrode CE20 overlapping the first electrode CE10 may be provided on the second insulating layer 20. The upper electrode and the second electrode CE20 may have an integral form in a plan view.

[0121] The second blocking electrode BML2 is disposed on the second insulating layer 20. The second blocking electrode BML2 may be disposed corresponding to the oxide transistor O-TFT. In one embodiment of the present disclosure, the second blocking electrode BML2 may be omitted. In one embodiment of the present disclosure, the first blocking electrode BML1 may be extended to the lower portion of the oxide transistor O-TFT, such that the second blocking electrode BML2 replaces the first blocking electrode BML1.

[0122] The third insulating layer 30 may be disposed on the second insulating layer 20. A second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide ("TCO") such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), indium gallium zinc oxide ("IGZO"), zinc oxide (ZnOx), or indium oxide (In2O3).

[0123] The metal oxide semiconductor may include multiple regions SE2, AC2, and DE2, categorized by whether the transparent conductive oxide has been reduced. The region where the transparent conductive oxide has been reduced (hereinafter, also referred to as the reduced region) has a greater conductivity than the region where the transparent conductive oxide has not been reduced (hereinafter, also referred to as the non-reduced region). The reduced region essentially functions as the source / drain or signal line of the transistor. The non-reduced region effectively corresponds to the semiconductor region (or channel region) of the transistor. In other words, a portion of the second semiconductor pattern SC2 may serve as the semiconductor region of the transistor, another portion of the second semiconductor pattern SC2 may serve as the source / drain region SE2 / DE2 of the transistor, and yet another portion of the second semiconductor pattern SC2 may serve as a region for transmitting signals.

[0124] The fourth insulating layer 40 may be disposed on the third insulating layer 30. Figure 6 As shown in FIG, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In one embodiment of the present disclosure, the fourth insulating layer 40 may be an insulating pattern overlapping the gate GT2 of the oxide transistor O-TFT and exposing the source region SE2 and the drain region DE2 of the oxide transistor O-TFT.

[0125] The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a portion of the metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0126] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate electrode GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer.

[0127] The conductive layer may be disposed on the fifth insulating layer 50. According to the present disclosure, the conductive layer includes a first connection pattern CNP1 and a second connection pattern CNP2. Because the first connection pattern CNP1 and the second connection pattern CNP2 are formed through the same process, they may have the same material and the same stacking structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 formed through the first to fifth insulating layers 10, 20, 30, 40, and 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 formed through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship between the first connection pattern CNP1 and the second connection pattern CNP2 relative to the silicon transistor S-TFT and the oxide transistor O-TFT is not necessarily limited to this.

[0128] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 via a third pixel contact hole PCH3 formed through the sixth insulating layer 60. The data line DL may be disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 to cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed by the same process. Therefore, the third connection pattern CNP3 and the data line DL may have the same material and the same stacking structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0129] The first blocking electrode BML1, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo) having excellent heat resistance, an alloy including molybdenum (Mo), titanium (Ti), or an alloy including these, or an alloy including titanium (Ti). The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum having high conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer structure of titanium / aluminum / titanium stacked.

[0130] The light-emitting element LD may include an anode AE ​​(or first electrode), a light-emitting layer EL, and a cathode CE (or second electrode). The anode AE ​​of the light-emitting element LD may be disposed on the seventh insulating layer 70. The anode AE ​​may be a transmissive electrode, a transflective electrode, or a reflective electrode. The anode AE ​​may include a stacked structure of ITO / Ag / ITO stacked in this order. The positions of the anode AE ​​and the cathode CE may be interchangeable.

[0131] The pixel defining layer (PDL) may be disposed on the seventh insulating layer 70. Furthermore, the pixel defining layer (PDL) may include an organic material. The pixel defining layer (PDL) may have light-absorbing properties. In one embodiment, for example, the pixel defining layer (PDL) may have a black color. The pixel defining layer (PDL) may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal (such as chromium), or an oxide thereof. The pixel defining layer (PDL) may correspond to a light-blocking pattern having light-blocking properties.

[0132] The pixel defining layer (PDL) may cover a portion of the anode AE. In one embodiment, for example, an opening (PDL-OP) for exposing a portion of the anode AE ​​may be defined in the pixel defining layer (PDL). The light-emitting area LA may be defined to correspond to the opening (PDL-OP). In one embodiment of the present disclosure, a hole control layer may be interposed between the anode AE ​​and the light-emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be interposed between the light-emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0133] The encapsulation layer TFE may cover the light emitting element LD. The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the present disclosure is not limited thereto, and the encapsulation layer TFE may further include a plurality of inorganic layers and organic layers.

[0134] The first encapsulating insulating layer IL1 may be an inorganic layer. The first encapsulating insulating layer IL1 may prevent external moisture or oxygen from penetrating into the light-emitting element LD. In one embodiment, the first encapsulating insulating layer IL1 may include, for example, silicon nitride, silicon oxide, or any combination thereof. The first encapsulating insulating layer IL1 may be formed by a chemical vapor deposition process.

[0135] The second encapsulation insulating layer IL2 may be an organic layer. The second encapsulation insulating layer IL2 may be disposed on the first encapsulation insulating layer IL1 so as to contact the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 may provide a flat surface on the first encapsulation insulating layer IL1. Roughness formed on the top surface of the first encapsulation insulating layer IL1 or particles on the first encapsulation insulating layer IL1 are covered by the second encapsulation insulating layer IL2, thereby preventing the surface state of the top surface of the first encapsulation insulating layer IL1 from affecting components formed on the second encapsulation insulating layer IL2. In addition, the second encapsulation insulating layer IL2 may reduce stress between contacting layers. The second encapsulation insulating layer IL2 may be formed using a solution process such as a spin coating process, a slit coating process, or an inkjet process.

[0136] The third encapsulation insulating layer IL3 may be provided on the second encapsulation insulating layer IL2 to cover the second encapsulation insulating layer IL2. Compared to when the third encapsulation insulating layer IL3 is provided on the first encapsulation insulating layer IL1, the third encapsulation insulating layer IL3 may be stably formed on a flatter surface. The third encapsulation insulating layer IL3 may encapsulate moisture discharged from the second encapsulation insulating layer IL2, thereby preventing the moisture from flowing out.

[0137] The third encapsulation insulating layer IL3 may be optically transparent. In one embodiment, the third encapsulation insulating layer IL3 may have a visible light transmittance of, for example, about 90% or more. The third encapsulation insulating layer IL3 may have a higher transmittance than the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO x ) or silicon oxynitride (SiON). The third encapsulation insulating layer IL3 may be formed by a chemical vapor deposition process. Each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include a plurality of layers, and the present disclosure is not limited to a specific embodiment.

[0138] The input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In one embodiment, the input sensing layer ISL may include a first insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 6 The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 are briefly illustrated.

[0139] The first insulating layer IS-IL1 may be directly disposed on the display panel DP. The first insulating layer IS-IL1 may be an inorganic layer including at least any one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a single-layer structure or a multi-layer structure stacked in the third direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 may include conductive lines defining electrodes in a grid format. The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may or may not be connected to each other through contact holes defined through the second insulating layer IS-IL2. The connection relationship between the conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may be determined depending on the type of sensor formed by the input sensing layer ISL.

[0140] The first conductive layer ICL1 and the second conductive layer ICL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or any alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO x ) or indium zinc tin oxide ("IZTO"). In addition, the transparent conductive layer may include a conductive polymer such as poly(3,4-ethylenedioxythiophene) ("PEDOT"), metal nanowires, or graphene.

[0141] The first conductive layer ICL1 and the second conductive layer ICL2 having a multilayer structure may include metal layers. The metal layers may have, for example, a three-layer structure of titanium / aluminum / titanium. The conductive layers in the multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be interposed between the first conductive layer ICL1 and the second conductive layer ICL2. The third insulating layer IS-IL3 may cover the second conductive layer ICL2. In one embodiment of the present disclosure, the third insulating layer IS-IL3 may be omitted. The second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include inorganic layers or organic layers.

[0142] Figure 7 FIG is a plan view of an embodiment of a display panel according to the present disclosure. Specifically, Figure 7 It is a plan view of the display panel DP observed in the third direction DR3.

[0143] refer to Figure 7 The pad electrode PD may be provided on the rear surface of the display panel DP. Specifically, the pad electrode PD may be provided in the pad area PA. A plurality of pad electrodes PD may be provided. The pad electrodes PD may be arranged in the second direction DR2.

[0144] A plurality of signal lines SGL (refer to Figure 5 ) can be electrically connected to the pad area PA Figure 3 In one embodiment, for example, the plurality of signal lines SGL may be connected to the pad electrodes PD, which are provided in the pad area PA and spaced apart from each other in the first direction DR1, through connection electrodes or the like. Although not illustrated, the pad electrodes PD may be provided on the rear surface of the display panel DP and may be electrically connected to the circuit board FCB (refer to FIG. Figure 2 ).

[0145] Figure 8 This is an enlarged view of an embodiment of a portion of a display device according to the present disclosure. Figure 9A For the Figure 8 1 is a cross-sectional view of a portion of the display device taken along line II-II'. Figure 9B for Figure 9A Magnified view of region AA' illustrated in FIG. Figure 8 and Figure 9A 1 is a view illustrating a state in which the circuit board FCB is attached to the display panel DP. Hereinafter, the above repeated description will be omitted.

[0146] refer to Figure 8 and Figure 9A , the display device DD of the present disclosure may include a plurality of pad electrodes PD. The pad electrodes PD and Figure 6 The first blocking electrode BML1 illustrated in FIG may be provided in the same layer. The pad electrode PD and the first blocking electrode BML1 may be formed by the same process. In one embodiment, for example, a single metal layer may be provided on the base layer BL, the metal layer may be patterned to form the pad electrode PD in the non-display area DM-NDA, and the first blocking electrode BML1 may be formed in the display area DM-DA. Although not illustrated, the pad electrode PD may be electrically connected to the first blocking electrode BML1 through the connection electrode CNE provided on the pad electrode PD. Figure 5 The data line DL is illustrated in FIG.

[0147] The pad electrode PD may extend in the first direction DR1 and may be arranged in the second direction DR2. However, the present disclosure is not limited to this. The shape and arrangement of the pad electrode PD are not limited to the accompanying drawings. The pad electrode PD may overlap with the non-display area DM-NDA. In one embodiment, for example, the pad electrode PD may be arranged in the pad area PA. The pad electrode PD may be exposed to the outside through the first surface (or bottom surface) BL-LS of the base layer BL to be back-bonded with the circuit board FCB. However, the present disclosure is not limited to this, and the pad electrode PD may be exposed to the outside through a contact hole rather than directly exposed to the outside. The first surface BL-LS of the base layer BL faces the second surface (or upper surface) BL-US of the base layer BL in the third direction DR3.

[0148] The base layer BL may include a first sub-base layer (or first base layer) SBL1, a first sub-base inorganic layer (also referred to as a first sub-base insulating layer) SBIL1, a second sub-base inorganic layer (also referred to as a second sub-base insulating layer) SBIL2, and a second sub-base layer (or second base layer) SBL2 stacked in sequence. In the description, the first sub-base inorganic layer SBIL1 and the second sub-base inorganic layer SBIL2 may be collectively referred to as a base insulating layer. The first sub-base inorganic layer SBIL1 is disposed on the first sub-base layer SBL1, the second sub-base inorganic layer SBIL2 is disposed on the first sub-base inorganic layer SBIL1, and the second sub-base layer SBL2 is disposed on the second sub-base inorganic layer SBIL2.

[0149] In one embodiment of the present disclosure, the first sub-base layer SBL1 and the second sub-base layer SBL2 may include an organic material or a synthetic resin material, such as polyimide. The first sub-base inorganic layer SBIL1 and the second sub-base inorganic layer SBIL2 may include an inorganic material. In one embodiment, the first sub-base inorganic layer SBIL1 and the second sub-base inorganic layer SBIL2 may include, for example, silicon nitride, silicon oxynitride, or silicon oxide. Amorphous silicon may include amorphous silicon (a-Si). Each of the first sub-base inorganic layer SBIL1 and the second sub-base inorganic layer SBIL2 may include multiple layers.

[0150] The first surface BL-LS of the base layer BL is disposed on the first sub-base layer SBL1, and a second opening B2-OP is defined in the first sub-base layer SBL1 to expose the pad electrode PD outside the display module DM. The second opening B2-OP may expose a portion of the first sub-base inorganic layer SBIL1 to the outside. A first opening (also referred to as a base opening) B1-OP is defined in the first sub-base inorganic layer SBIL1 such that a portion of the pad electrode PD is disposed within the first opening B1-OP. The size of the second opening B2-OP may be larger than that of the first opening B1-OP.

[0151] The width of the second opening B2-OP in the first direction DR1 may gradually decrease in the third direction DR3. However, the present disclosure is not limited thereto. In one embodiment, for example, the width of the second opening B2-OP in the first direction DR1 may be constant in the third direction DR3. As illustrated, the pad electrode PD may be disposed in the first opening B1-OP. The pad electrode PD may be embedded in the base layer BL. However, the present disclosure is not limited thereto. In one embodiment, for example, the pad electrode PD may be disposed on the first surface BL-LS of the base layer BL.

[0152] The protective layer PTL may be disposed on the base layer BL. In one embodiment, for example, the protective layer PTL may be disposed while directly contacting the second sub-base layer SBL2. The protective layer PTL may overlap at least a portion of the second sub-base layer SBL2. The thickness of the protective layer PTL may be smaller than the thickness of the second sub-base layer SBL2. In one embodiment of the present disclosure, the protective layer PTL may include at least one inorganic layer. In one embodiment, the inorganic layer may include, for example, silicon nitride, silicon oxynitride, or silicon oxide. Amorphous silicon may include amorphous silicon (a-Si).

[0153] Reference together Figure 9A and Figure 9BThe connection electrode CNE can be electrically connected to the pad electrode PD through the contact holes CH1, CH2, and CH3. In one embodiment, the contact holes CH1, CH2, and CH3 may include, for example, a first contact hole CH1, a second contact hole CH2, and a third contact hole CH3. The first contact hole CH1 is formed through the second sub-base layer SBL2, the second contact hole CH2 is formed through the protective layer PTL, and the third contact hole CH3 may be formed in the first sub-base inorganic layer SBIL1 through the second sub-base inorganic layer SBIL2.

[0154] The first contact hole CH1 is defined by the first side surface SA1 of the second sub-base layer SBL2, and the first width W1 of the first contact hole CH1 can be defined as the distance between the first side surfaces SA1. The second contact hole CH2 is defined by the second side surface SA2 of the protective layer PTL, and the second width W2 of the second contact hole CH2 can be defined as the distance between the second side surfaces SA2. The third contact hole CH3 is defined by the third side surface SA3 of the second sub-base inorganic layer SBIL2, and the third width W3 of the third contact hole CH3 can be defined as the distance between the third side surfaces SA3.

[0155] In one embodiment of the present disclosure, the first width W1 of the first contact hole CH1 may be different from the second width W2 of the second contact hole CH2. In one embodiment, the second width W2 may be larger than the first width W1. In the process of forming the first contact hole CH1 and the second contact hole CH2, for example, the protective layer PTL and the second sub-base layer SBL2 may have different etching rates. Therefore, the first width W1 and the second width W2 may be different from each other. In an alternative embodiment, after the protective layer PTL may be etched first, the second sub-base layer SBL2 may be etched so that the first width W1 and the second width W2 may be different from each other. As illustrated, the third width W3 may be smaller than the first width W1. However, the present disclosure is not limited thereto. In one embodiment, for example, the third width W3 may be equal to the first width W1. In other words, the first side surface SA1 and the third side surface SA3 may be aligned with each other in the third direction DR3.

[0156] The second contact hole CH2 may be formed after the protective layer PTL is provided on the second sub-base layer SBL2. In other words, the second contact hole CH2 may be formed simultaneously with the first contact hole CH1, or may be formed after the first contact hole CH1 is formed. When forming the first contact hole CH1, an operation of etching the second sub-base layer SBL2 including an organic material may be included. In the operation of etching the second sub-base layer SBL2, exhaust gas may be emitted to reduce the display quality of the display device DD. In one embodiment of the present disclosure, after the protective layer PTL including at least one inorganic layer is provided on the second sub-base layer SBL2, the second sub-base layer SBL2 is etched, thereby reducing the outflow of the emitted exhaust gas. Therefore, a display device DD with improved display quality can be provided.

[0157] In one embodiment of the present disclosure, Figure 6 The first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 illustrated in the figure may not be formed in the pad area PA. Although not illustrated, a photoresist may be provided before forming the protective layer PTL. Therefore, the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 may not be formed between the second subbase layer SBL2 and the protective layer PTL. In an alternative embodiment, a photoresist may be provided before forming the connection electrode CNE. Therefore, the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 may not be formed between the connection electrode CNE and the protective layer PTL. Therefore, the connection electrode CNE may be provided directly on the first to third side surfaces SA1, SA2, and SA3 without a step difference. Therefore, the connection electrode CNE can be prevented from being disconnected due to the step difference, thereby preventing a connection failure between the connection electrode CNE and the pad electrode PD caused by residues of the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2. Therefore, a display device DD with improved reliability can be provided.

[0158] The first contact hole CH1, the second contact hole CH2, and the third contact hole CH3 may overlap with each other in a plan view. Furthermore, in a plan view, the first to third contact holes CH1, CH2, and CH3 may overlap with the first opening B1-OP and the second opening B2-OP. As shown in the figure, the width of the second opening B2-OP is formed to be larger than each of the first to third widths W1, W2, and W3, but the present disclosure is not limited thereto. In one embodiment, for example, the width of the second opening B2-OP may be smaller than each of the first to third widths W1, W2, and W3.

[0159] Return Reference Figure 8 and Figure 9AThe circuit board FCB may be attached to the display panel DP while being bent on the rear surface of the display panel DP. An adhesive layer may be interposed between the circuit board FCB and the first surface BL-LS of the base layer BL. The circuit board FCB may be fixed to the first surface BL-LS of the base layer BL by the adhesive layer.

[0160] The circuit board (FCB) may include a base film (BF) and bump electrodes (BMP) disposed on the base film (BF). The base film (BF) may be integral and electrically connected to the plurality of bump electrodes (BMP). In this case, the base film (BF) may include a plurality of wires. However, the present disclosure is not limited thereto. The base film (BF) may be attached only to the plurality of bump electrodes (BMP) and may not be electrically connected to the plurality of bump electrodes (BMP). In this case, the base film (BF) may include a synthetic resin material, such as polyimide. The bump electrodes (BMP) may be disposed on the base film (BF).

[0161] The bump electrode BMP may not overlap the pad electrode PD in a plan view. The bump electrode BMP may be electrically connected to the pad electrode PD. The bump electrode BMP may be formed to correspond to the pad electrode PD. In other words, one bump electrode BMP may correspond to one pad electrode PD. The bump electrode BMP may extend in a first direction DR1 and may be arranged in a second direction DR2. The planar area of ​​the pad electrode PD may be larger than the planar area of ​​the bump electrode BMP.

[0162] The adhesive layer AF may be provided between the base film BF and the pad electrode PD. In one embodiment of the present disclosure, the adhesive layer AF may include a non-conductive material. In one embodiment, the adhesive layer AF may include, for example, a non-conductive film.

[0163] The bump electrode BMP may be electrically connected to the pad electrode PD. Figure 2 ) may further include a metal pattern MP for electrically connecting the bump electrode BMP to the pad electrode PD. The metal pattern MP may be provided on the pad electrode PD and the bump electrode BMP to electrically connect the pad electrode PD to the bump electrode BMP. The metal pattern MP may be provided so as to correspond in number to each of the pad electrode PD and the bump electrode BMP.

[0164] Each metal pattern MP may be a pattern formed by curing a metal ink. The metal pattern MP may include solder paste. The metal pattern MP may be formed using a metal ink including silver or copper. The metal pattern MP may be formed by curing and then patterning the metal ink. The metal pattern MP may be formed at a relatively low temperature and may electrically connect and bond the pad electrode PD to the bump electrode BMP without requiring a relatively high-temperature pressing process.

[0165] The display device DD according to the present disclosure may further include an adhesive resin AR. The adhesive resin AR may include an optically transparent resin. However, the material of the adhesive resin AR is not limited thereto and may include a general adhesive or a bonding agent. In one embodiment, the adhesive resin AR may include, for example, a pressure sensitive adhesive ("PSA") or an optically clear adhesive ("OCA"). The adhesive resin AR may cover the metal pattern MP exposed to the outside. Figure 9A The adhesive resin AR may be formed to fill the second opening B2-OP and contact the side surface of the first sub-substrate layer SBL1, thereby reducing the possibility of internal components of the display device DD being broken when the display device DD is subjected to external impact and bent around the second opening B2-OP.

[0166] Figure 10A and Figure 10B FIG. 1 is an enlarged view of a portion of a display device according to an embodiment of the present disclosure. In the following description, the above repeated description will be omitted.

[0167] refer to Figure 10A The connection electrode CNEa can be electrically connected to the pad electrode PD through the contact holes CH1, CH2a, and CH3. The first contact hole CH1 is defined by the first side surface SA1 of the second sub-base layer SBL2, and the first width W1 of the first contact hole CH1 can be defined as the distance between the first side surfaces SA. The second contact hole CH2a is defined by the second side surface SA2a of the protective layer PTLa, and the second width W2a of the second contact hole CH2a can be defined as the distance between the second side surfaces SA2a. The third contact hole CH3 is defined by the third side surface SA3 of the second sub-base inorganic layer SBIL2, and the third width W3 of the third contact hole CH3 can be defined as the distance between the third side surfaces SA3.

[0168] As illustrated, the first width W1 may be smaller than the second width W2a, and the third width W3 may be smaller than the first width W1. However, the present disclosure is not limited thereto, and the first width W1, the second width W2a, and the third width W3 may be equal to each other. In other words, the first side surface SA1, the second side surface SA2a, and the third side surface SA3 may be aligned with each other in the third direction DR3. Therefore, the connection electrode CNEa can be provided on the first side surface SA1, the second side surface SA2a, and the third side surface SA3 without a step difference, thereby preventing the connection electrode CNEa from being disconnected by the first side surface SA1, the second side surface SA2a, and the third side surface SA3.

[0169] refer to Figure 10BThe connection electrode CNEb can be electrically connected to the pad electrode PD through the contact holes CH1a, CH2b, and CH3. The first contact hole CH1a can be defined by the first side surface SA1a of the second sub-base layer SBL2, and the first width W1a of the first contact hole CH1a can be defined as the distance between the first side surfaces SA1a. The second contact hole CH2b can be defined by the second side surface SA2b of the protective layer PTLb, and the second width W2b of the second contact hole CH2b can be defined as the distance between the second side surfaces SA2b. The third contact hole CH3 can be defined by the third side surface SA3 of the second sub-base inorganic layer SBIL2, and the third width W3 of the third contact hole CH3 can be defined as the distance between the third side surfaces SA3.

[0170] In the method for manufacturing a display device DD (refer to Figure 2 ), the protective layer PTLb, the second sub-base layer SBL2, and the second sub-base inorganic layer SBIL2 can be etched in sequence, so that the first width W1a of the second sub-base layer SBL2 is smaller than the second width W2b of the protective layer PTLb, and the third width W3 of the second sub-base inorganic layer SBIL2 is smaller than the first width W1a of the second sub-base layer SBL2. Therefore, the protective layer PTLb, the second sub-base layer SBL2, and the second sub-base inorganic layer SBIL2 can be prevented from gradually decreasing in the opposite direction due to the difference in etching rates among the protective layer PTLb, the second sub-base layer SBL2, and the second sub-base inorganic layer SBIL2. Therefore, the connection electrode CNEb can be prevented from being disconnected by the first side surface SA1a, the second side surface SA2b, and the third side surface SA3.

[0171] Figure 11 is a cross-sectional view of a portion of an embodiment of a display device DDa according to the present disclosure.

[0172] refer to Figure 11 The pad electrode PDa may include a first portion B1 overlapping with the first opening B1-OP and a second portion B2 not overlapping with the first opening B1-OP. The second portion B2 may be directly disposed on the first sub-substrate inorganic layer SBIL1. The first portion B1 may be disposed in the pad area PA. The first portion B1 may be disposed in the first opening B1-OP. The first portion B1 may be exposed to the outside through the second opening B2-OP. The second portion B2 may extend from the first portion B1 in the first direction DR1. The first portion B1 and the second portion B2 may be integrally formed with each other.

[0173] Each of the first to third contact holes CH1, CH2, and CH3 may not overlap with the first opening B1-OP. In one embodiment of the present disclosure, the connection electrode CNE may directly contact the second portion B2, which does not overlap with the first opening B1-OP. The connection electrode CNE may be electrically connected to the second portion B2 to electrically connect to the pad electrode PDa. In a plan view, each of the first to third contact holes CH1, CH2, and CH3 may partially overlap with the second opening B2-OP. However, in a plan view different from the accompanying drawings, each of the first to third contact holes CH1, CH2, and CH3 may not overlap with the second opening B2-OP.

[0174] 12A to 12H A diagram illustrating an embodiment of an operation in a method for manufacturing a display device. 12A to 12H In description of the method for manufacturing a display device in an embodiment of the present disclosure, the same reference numerals will be given to the same components as those described above, and details thereof will be omitted.

[0175] refer to Figure 12A , an operation of forming a first preliminary subsubstrate layer (also referred to as a first preliminary substrate layer) P-SBL1 and an operation of forming a first preliminary subsubstrate inorganic layer P-SBIL1 on the first preliminary subsubstrate layer P-SBL1 may be performed.

[0176] refer to Figure 12B , wherein the first sub-base inorganic layer SBIL1 defining the first opening B1-OP can be formed by etching the first preliminary sub-base inorganic layer P-SBIL1 (referring to Figure 12A ) is formed. In one embodiment, for example, the first opening B1-OP may be formed in the first sub-base inorganic layer SBIL1 by a photolithography process. Thereafter, the metal layer MTL may be formed on the first sub-base inorganic layer SBIL1. Figure 12B and Figure 12C , the metal layer MTL may be patterned to form a pad electrode PD. The pad electrode PD may be disposed in the first opening B1-OP. However, the present disclosure is not limited thereto. In one embodiment, as Figure 11 As illustrated in FIG. 5 , for example, after the metal layer MTL is patterned, the pad electrode PDa may overlap the entire portion of the non-display area DM-NDA.

[0177] refer to Figure 12D A second preliminary subbase inorganic layer (also referred to as a second preliminary subbase layer) P-SBIL2 may be formed on the first subbase inorganic layer SBIL1 and the pad electrode PD, and a second preliminary subbase layer P-SBL2 may be formed on the second preliminary subbase inorganic layer P-SBIL2. The second preliminary subbase inorganic layer P-SBIL2 and the second preliminary subbase layer P-SBL2 may be stacked in sequence.

[0178] A photoresist layer PR may be disposed on the second preliminary sub-base layer P-SBL2. Figure 6 , the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 may be disposed on the base layer BL of the present disclosure. However, the photoresist layer PR may be disposed on the second preliminary sub-base layer P-SBL2 so that the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 may not be formed in the pad area PA (refer to Figure 9A ). Thereafter, the photoresist layer PR may be removed.

[0179] refer to Figure 12E The preliminary protective layer P-PTL may be formed on the second preliminary sub-base layer P-SBL2. The protective layer PTL formed by the preliminary protective layer P-PTL may include at least one inorganic layer. In one embodiment, the inorganic layer may include, for example, silicon nitride, silicon oxynitride, or silicon oxide. The amorphous silicon may include amorphous silicon (a-Si).

[0180] Reference together Figure 12D and Figure 12E , the preliminary protective layer P-PTL may be provided to directly contact the second preliminary sub-base layer P-SBL2. In other words, Figure 6 The first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, and BML2 illustrated in the embodiment may not be disposed between the second preliminary sub-base layer P-SBL2 and the preliminary protective layer P-PTL. In an alternative embodiment, the preliminary protective layer P-PTL may be one of the first to fifth insulating layers 10 to 50.

[0181] Reference together Figure 12E and Figure 12F , the protective layer PTL can be formed by etching (or a first etching process) the preliminary protective layer P-PTL. In detail, the photoresist layer PR is provided on the preliminary protective layer P-PTL, and the first etching process is performed on the preliminary protective layer P-PTL, thereby forming the contact hole (or second contact hole) CH2. When the first to third contact holes CH1, CH2, CH3 (refer to Figure 12H ), a first etching process may be performed on the preliminary protective layer P-PTL to prevent a portion of the preliminary protective layer P-PTL from remaining on the second sub-base layer SBL2 (refer to Figure 12H In one embodiment, the first etching process may be omitted. Although not illustrated, to form the photoresist layer PR, a preliminary photoresist layer is disposed on the preliminary protective layer P-PTL and patterned using a mask. After performing the first etching process, the protective layer PTL defining the second contact hole CH2 may be formed. Thereafter, the photoresist layer PR may be removed.

[0182] refer to Figure 12G , the first contact hole CH1 and the third contact hole CH3 are formed using a hard mask MSK-H. The hard mask MSK-H may include an IZO mask. After the IZO layer is formed on the protective layer PTL, a mask opening OP-M may be formed in the IZO layer through a photolithography process. The second preliminary sub-substrate inorganic layer P-SBIL2 and the second preliminary sub-substrate inorganic layer P-SBL2 may be etched (or a second etching process may be performed) to form a second sub-substrate inorganic layer SBL2 defining the first contact hole CH1 and a second sub-substrate inorganic layer SBIL2 defining the third contact hole CH3. A mask including a transparent conductive oxide other than IZO may be used.

[0183] When the second etching process is performed on the second preliminary sub-base layer P-SBL2, exhaust gas may be discharged, thereby reducing the display device DD (refer to FIG. Figure 2 ) display quality. Before performing the second etching process, the protective layer PTL may be provided on the second preliminary sub-base layer P-SBL2 including at least one inorganic layer, thereby reducing the outflow of exhaust gas discharged when etching the second preliminary sub-base layer P-SBL2. Therefore, a display device DD with improved display quality (refer to Figure 2 ).

[0184] In addition, in order to simplify the display device (DD, refer to Figure 2 ), the second etching process may be performed on the second preliminary sub-substrate inorganic layer P-SBIL2 and the second preliminary sub-substrate layer P-SBL2 in a single process.

[0185] refer to Figure 12H , the connection electrode CNE may be formed on the pad electrode PD and the protective layer PTL. The connection electrode CNE may be electrically connected to the pad electrode PD through the first to third contact holes CH1, CH2, CH3. Figure 12E and Figure 12H , the first insulating layer 10 to the fifth insulating layer 50 (reference Figure 6 ) and conductive layers CNP1, CNP2, BML2 (reference Figure 6 ) may not be formed between the connection electrode CNE and the protective layer PTL. Therefore, the connection electrode CNE may be directly provided on the side surface defining the first to third contact holes CH1, CH2, CH3 without a step difference, thereby preventing the connection electrode CNE from being disconnected due to the step difference. In addition, connection failure between the connection electrode CNE and the pad electrode PD caused by residues of the first to fifth insulating layers 10 to 50 and the conductive layers CNP1, CNP2, BML2 may be prevented. Therefore, a display device DD with improved reliability may be provided (refer to FIG. Figure 2 ).

[0186] Figure 13A and Figure 13B 1 is a diagram illustrating an embodiment of an operation of a method for manufacturing a display device. Figure 13A and Figure 13B Example circuit board FCB (reference Figure 2 ) is connected to the display module DM (reference Figure 2 )'s rear surface.

[0187] refer to Figure 13A ,exist Figure 12H The display device DD (refer to Figure 2 After a portion of the substrate is inverted, an operation of forming the first sub-substrate layer SBL1 by etching the first preliminary sub-substrate layer P-SBL1 may be performed. Although not illustrated, a photoresist layer is provided on the first preliminary sub-substrate layer P-SBL1, and the first preliminary sub-substrate layer P-SBL1 is etched to form a second opening B2-OP. The pad electrode PD may be directly exposed to the outside through the second opening B2-OP formed through the first preliminary sub-substrate layer P-SBL1. The pad electrode PD may be exposed to the width of the second opening B2-OP in the first direction DR1.

[0188] refer to Figure 13B , an operation of electrically connecting the display module DM to the circuit board FCB according to the present disclosure may be performed. Specifically, the circuit board FCB may be disposed on the first surface BL-LS of the base layer BL. An adhesive layer may be interposed between the circuit board FCB and the first surface BL-LS of the base layer BL. The circuit board FCB may be fixed to the first surface BL-LS of the base layer BL via the adhesive layer.

[0189] The circuit board FCB may include a base film BF and bump electrodes BMP disposed on the base film BF. The base film BF may be integral and electrically connected to the bump electrodes BMP. The bump electrodes BMP may be secured to the first surface BL-LS of the base layer BL via an adhesive layer AF. Although not illustrated, the circuit board FCB may be attached to the base layer BL while being bent on the first surface BL-LS of the base layer BL.

[0190] After this, an operation of forming a metal pattern MP may be performed. The metal pattern MP may be formed by curing a metal ink. The metal pattern MP may be formed by curing the metal ink at a relatively low temperature and then patterning the cured metal ink. The pad electrode PD and the bump electrode BMP may be electrically connected to each other and simultaneously bonded via the metal pattern MP.

[0191] After forming the metal pattern MP, an adhesive resin AR may be formed to cover the metal pattern MP in the second opening B2-OP. The adhesive resin AR may include an optically transparent resin. However, the material of the adhesive resin AR is not limited thereto. In one embodiment, the material of the adhesive resin AR may include, for example, a general adhesive or a bonding agent.

[0192] As described above, in the display panel according to the present disclosure, a protective layer comprising at least one inorganic layer can be provided on the second sub-base layer comprising an organic material. Therefore, the outflow of exhaust gas discharged when etching the second sub-base layer can be reduced. Therefore, a display device with improved display quality can be provided.

[0193] Furthermore, since the insulating layer and the conductive layer are not provided between the base layer and the protective layer, the connection electrode is directly provided on the side surface defining the contact hole, thereby preventing the connection electrode from being disconnected by the insulating layer and the conductive layer. Therefore, connection failures caused by residues of the insulating layer and the conductive layer can be prevented. Consequently, a display device with improved reliability can be provided.

[0194] Although the embodiments of the present disclosure have been described for purposes of illustration, those skilled in the art will appreciate that various modifications and substitutions are possible without departing from the scope and spirit of the invention as disclosed in the claims.

[0195] Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0196] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display panel, comprising: a first substrate layer, the opening being defined therein; a pad electrode, disposed on the first base layer and exposed to the outside through the opening; a second base layer, the second base layer being disposed on the pad electrode and having a first contact hole defined therein; a protective layer disposed on the second base layer, wherein a second contact hole overlapping the first contact hole is defined in the protective layer; as well as a connecting electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole, The second contact hole has a width greater than that of the first contact hole.

2. The display panel according to claim 1, further comprising: a base insulating layer, disposed between the first base layer and the second base layer, A third contact hole is defined in the base insulating layer through the base insulating layer. 3 . The display panel of claim 2 , wherein the third contact hole has a width different from that of the first contact hole. 4 . The display panel of claim 2 , wherein a first side surface of the second base layer defining the first contact hole and a second side surface of the base insulating layer defining the third contact hole are aligned with each other.

5. The display panel according to claim 2, wherein the base insulating layer comprises: a first sub-base insulating layer disposed on the first base layer, wherein a base opening is defined in the first sub-base insulating layer; as well as a second sub-base insulating layer disposed on the first sub-base insulating layer and the pad electrode, and The pad electrode is disposed in the substrate opening.

6. The display panel according to claim 5, wherein the third contact hole is defined in the second sub-base insulating layer, and The third contact hole overlaps with the substrate opening.

7. The display panel according to claim 1, wherein the pad electrode comprises: a first portion overlapping the opening; as well as A second portion extends from the first portion in a first direction. The display panel according to claim 7 , wherein the connection electrode directly contacts the first portion. 9 . The display panel according to claim 7 , wherein the connection electrode directly contacts the second portion. 10 . The display panel according to claim 1 , wherein the second base layer comprises an organic material. The display panel according to claim 10 , wherein the protective layer comprises at least one inorganic layer. 12 . The display panel according to claim 1 , wherein the second base layer has a thickness greater than that of the protective layer.

13. The display panel according to claim 1, wherein the first base layer comprises: display area and non-display area, and The pad electrode overlaps the non-display area.

14. An electronic device comprising: shell; an electronic module, disposed inside the housing; as well as A display device overlaps with the electronic module, and the display device includes: A display panel for displaying an image, the display panel comprising: a first substrate layer, the opening being defined therein; a pad electrode, disposed on the first base layer and exposed to the outside through the opening; a second base layer, the second base layer being disposed on the pad electrode and having a first contact hole defined therein; a protective layer disposed on the second base layer, and a second contact hole overlapping the first contact hole is defined in the protective layer; and a connecting electrode disposed on the protective layer and electrically connected to the pad electrode through the first contact hole and the second contact hole; and a circuit board coupled to the display panel, The second contact hole has a width greater than that of the first contact hole.

15. The electronic device according to claim 14, wherein the display panel further comprises: a first sub-base insulating layer, disposed on the first base layer; as well as a second sub-base insulating layer disposed on the first sub-base insulating layer and the pad electrode, and The pad electrode is disposed in a base opening defined in the first sub-base insulating layer.

16. The electronic device according to claim 15, wherein a third contact hole is defined in the second sub-base insulating layer, and The third contact hole has a width different from that of the first contact hole. 17 . The electronic device according to claim 14 , wherein each of the first contact hole and the second contact hole overlaps with the opening.

18. The electronic device according to claim 14, further comprising: The metal pattern is used to electrically connect the display panel to the circuit board.

19. The electronic device according to claim 18, wherein the display panel further comprises a first sub-base insulating layer disposed on the first base layer, The circuit board comprises: basement membrane; as well as a bump electrode disposed between the base film and the first sub-base insulating layer, and The bump electrode and the pad electrode are electrically connected to each other through the metal pattern.

20. The electronic device according to claim 19, further comprising: An adhesive layer is disposed between the bump electrode and the first sub-base insulating layer.

21. A method for manufacturing a display panel, the method comprising: forming a pad electrode on the first preliminary base layer; forming a second preliminary base layer on the first preliminary base layer and the pad electrode; forming a preliminary protective layer on the second preliminary base layer; forming a second base layer having a first contact hole defined therein by etching the second preliminary base layer, and forming a protection layer having a second contact hole defined therein by etching the preliminary protection layer; and forming a connection electrode on the protective layer, wherein the connection electrode is electrically connected to the pad electrode through the first contact hole and the second contact hole; The second contact hole has a width greater than that of the first contact hole.

22. The method according to claim 21, further comprising: A base insulating layer is formed between the first preliminary base layer and the second base layer, and a third contact hole is defined in the base insulating layer.

23. The method according to claim 22, wherein forming the base insulating layer comprises: forming a first sub-base insulating layer having a base opening defined therein on the first preliminary base layer; as well as A second sub-base insulating layer is formed on the first sub-base insulating layer and the pad electrode.

24. The method according to claim 23, wherein forming the second sub-base insulating layer comprises: The third contact hole is defined to overlap with the first contact hole. 25 . The method according to claim 24 , wherein the defining the third contact hole is performed simultaneously with the defining the first contact hole.

26. The method according to claim 24, wherein said defining said third contact hole is performed after said defining said first contact hole, and The third contact hole has a width smaller than that of the first contact hole.

27. The method according to claim 23, wherein forming the pad electrode comprises: forming a metal layer on the first sub-base insulating layer; as well as The pad electrode is formed by etching the metal layer.

28. The method according to claim 21, wherein etching the second preliminary base layer and the preliminary protective layer comprises: defining the first contact hole by performing a first etching process on the preliminary protective layer; as well as The second contact hole is defined by performing a second etching process on the second preliminary base layer. The method of claim 28 , wherein the second etching process is performed after the first etching process.

30. The method of claim 21, further comprising: An opening exposing the pad electrode to the outside is defined in the first preliminary base layer.

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