Memory system, operating method thereof, and computer readable storage medium

Abstract

The embodiment of the invention discloses a memory system, an operation method thereof and a computer readable storage medium, the memory system comprises a memory controller and a memory coupled with the memory controller, the memory comprises a plurality of memory blocks, and each memory block comprises a plurality of physical pages; the memory controller is configured to: determine at least one source memory block of the plurality of memory blocks; in response to the fact that the bitmap type associated with a first source storage block in the at least one source storage block is a first bitmap, effective data stored in the first source storage block is written into a first target storage block in the multiple storage blocks; wherein the first bitmap comprises at least one first logic value, and the first logic value is used for identifying a physical page, storing valid data, in a plurality of physical pages of the storage block; the first target storage block is different from the source storage block; and in response to writing the valid data into the first target storage block, erasing the source storage block.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] Memory is categorized as volatile memory and non-volatile memory based on whether it retains stored data during power outages. Non-volatile memory that retains data during power outages can include read-only memory (ROM) and flash memory. Taking flash memory as an example, since it cannot be overwritten, invalid data must be cleared to ensure sufficient storage space for data. This frees up available storage space. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, a memory system is provided, which includes a memory controller and a memory coupled to the memory controller, the memory including multiple memory blocks, and the memory blocks including multiple physical pages; the memory controller is configured to: determine at least one source memory block among the multiple memory blocks; in response to a bitmap type associated with a first source memory block among the at least one source memory block being a first bitmap, write valid data stored in the first source memory block to a first target memory block among the multiple memory blocks; wherein the first bitmap includes at least one first logical value, and the first logical value is used to identify a physical page storing the valid data among the multiple physical pages of the memory block; the first target memory block is different from the source memory block; and in response to the valid data being written to the first target memory block, erase the source memory block.

[0004] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory system is provided, wherein the memory system includes a memory controller and a memory coupled to the memory controller, the memory includes multiple memory blocks, and the memory blocks include multiple physical pages; the operating method includes: determining at least one source memory block among the multiple memory blocks; in response to a bitmap type associated with a first source memory block among the at least one source memory block being a first bitmap, writing valid data stored in the first source memory block to a first target memory block among the multiple memory blocks; wherein the first bitmap includes at least one first logical value, and the first logical value is used to identify a physical page storing the valid data among the multiple physical pages of the memory block; the first target memory block is different from the source memory block; and in response to the valid data being written to the first target memory block, erasing the source memory block.

[0005] According to a third aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed by a processor, the operating method as described in any embodiment of the second aspect of the embodiment of the present disclosure is implemented.

[0006] In an embodiment of the present disclosure, at least one source storage block among a plurality of storage blocks is determined by a memory controller; in response to the bitmap type associated with the first source storage block among the at least one source storage block being a first bitmap, valid data stored in the first source storage block is written to a first target storage block among the plurality of storage blocks; in response to the valid data being written to the first target storage block, the source storage block is erased; since the first bitmap includes at least one first logical value, the first logical value is used to identify a physical page storing valid data among a plurality of physical pages of the storage block, when performing a garbage collection operation, the physical address of the physical page storing valid data can be directly determined according to the number of the first logical values, and there is no need to retrieve whether there is a valid mapping entry for the physical page corresponding to the first logical value. In this way, on the one hand, the duration of garbage collection can be reduced and the efficiency of garbage collection can be improved; on the other hand, in the case where the data stored in the source storage block is very large or very random, the first bitmap provided by the embodiment of the present disclosure can greatly improve the efficiency of garbage collection, and is more suitable for application scenarios with large data volumes or high data randomness. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0008] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0009] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure.

[0010] Figure 2b is a schematic diagram of a solid-state hard disk according to an embodiment of the present disclosure.

[0011] Figure 3 is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0012] Figure 4 Schematic cross-sectional view of a memory according to an embodiment of the present disclosure.

[0013] Figure 5is a schematic diagram of a memory including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure.

[0014] Figure 6 It is a schematic diagram showing a garbage collection operation according to an embodiment of the present disclosure.

[0015] Figure 7 is a schematic diagram of a memory system according to an embodiment of the present disclosure.

[0016] Figure 8 This is a schematic diagram of a first source storage block and a first bitmap according to an embodiment of the present disclosure.

[0017] Figure 9 This is a schematic diagram of a second source storage block and a second bitmap according to an embodiment of the present disclosure.

[0018] Figure 10 The flowchart of a method for operating a memory system according to an embodiment of the present disclosure is shown.

[0019] Figure 11 The flowchart of generating a first bitmap or a second bitmap according to an embodiment of the present disclosure is shown.

[0020] Figure 12 The figure is a flowchart showing a garbage collection operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0023] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0024] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0026] The memory in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0027] Figure 1 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown, the electronic device 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0028] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0029] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error checking and correction (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., Figure 1For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-E (Peripheral Component Interconnect Express) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Development Equipment (IDE) protocol, the Firewire protocol, and the like.

[0030] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0031] Figure 3 3 is a schematic block diagram of a three-dimensional NAND memory 300 according to an embodiment of the present disclosure. The memory 300 may be Figure 1 3. An example of a memory 104 in FIG. Memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is described as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of ​​the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0032] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value other than the three nominal storage values ​​can be used to represent an erased state.

[0033] like Figure 3As shown in FIG, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0034] like Figure 3As shown in FIG, a NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-memory block level, at the quarter-memory block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a physical page of memory cells 306, which is the basic data unit for programming operations. The size of a physical page in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding physical page and a gate line coupling the control gates. A physical page contains multiple memory cells 306, which are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each memory cell row being parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0035] Figure 4 1 is a cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure. Figure 4 As shown, NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. Gate layers 411 and insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in stacked structure 410 may determine the number of memory cells included in memory cell array 301.

[0036] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0037] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0038] In some embodiments, NAND memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0039] Return Reference Figure 3, the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0040] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one physical page of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0041] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0042] The control logic 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0043] Typically, flash memory (e.g., Figure 1 The memory 104 in the memory 104) relies on garbage collection operations to free up space occupied by invalid data. The garbage collection operations can be performed by a memory controller (e.g., Figure 1 Specifically, at least one memory block is selected from a plurality of memory blocks as a source memory block (also referred to as an old memory block or a sacrifice block); valid data in the selected source memory block is read and written to a target memory block (also referred to as a new memory block); and the selected source memory block is erased to obtain an available memory block (also referred to as a free block).

[0044] It should be noted that the data stored in the storage block includes at least one of invalid data and valid data. Invalid data usually refers to garbage data that has been deleted or overwritten, and valid data usually refers to data that the user is still using. In actual applications, whether the data is valid can be determined by looking up the logical to physical address mapping (Logical address To Physicaladdress, L2P) table.

[0045] Typically, after determining the source memory block that needs to perform a garbage collection operation, valid data is retrieved through the Page Table Entry Bitmap (PTE bitmap) associated with the source memory block, where the PTE bitmap is used to identify whether the physical page of the source memory block stores data. For example, if data is stored on a physical page of the source memory block, it can be identified by a logical value of "1" or "0" on the corresponding bit in the PTE bitmap. Conversely, if no data is stored on a physical page of the source memory block, it can be identified by a logical value of "1" or "0" on the corresponding bit in the PTE bitmap.

[0046] The memory controller can retrieve valid data according to the PTE bitmap and L2P table and read out the valid data of the source memory block. Figure 6 As shown, the memory controller can search the Page Middle Directory (PMD) table based on the logical value "1" in the PTE bitmap to determine whether there is a valid mapping entry (L2P-PCA). If a valid mapping entry exists, the data of the physical page corresponding to the logical value "1" is determined to be valid data, and the page table entry (PTE) table is searched to determine the physical address (Data-PCA) of the physical page storing the valid data. Based on the physical address (Data-PCA), the valid data (Data (LCA: 1027)) in the storage block is read. Of course, after searching the PMD table based on other logical values ​​"1" in the PTE bitmap, if it determines that there is no valid mapping entry, the memory controller determines that the data of the physical page corresponding to the other logical value "1" is invalid data.

[0047] It should be noted that, in actual applications, the memory controller can page the L2P table to form a multi-level page table, which includes the above-mentioned PMD table and PTE table. It should be understood that the L2P table may also include Figure 6Other page tables not shown in the figure, for example, a Page Global Directory (PGD) table, a Page Upper Directory (PUD) table, etc.

[0048] It is understandable that the logical value "1" in the PTE bitmap indicates that the data stored in the corresponding physical page may be valid data. Therefore, in order to avoid the loss of valid data, during the garbage collection operation, the L2P table needs to be searched once for each logical value "1" in the PTE bitmap. The greater the number of logical values ​​"1", the more times the table needs to be looked up. However, when the source storage block stores a large amount of data or the data is very random, more bits in the PTE bitmap will be set to the logical value "1". Usually, a maximum of 4KB of bits in the PTE bitmap associated with a source storage block will be set to the logical value "1". During garbage collection, the L2P table needs to be searched multiple times, which makes garbage collection time-consuming and inefficient.

[0049] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a memory system. Figure 7 is a schematic diagram of a memory system according to an embodiment of the present disclosure. Figure 8 is a schematic diagram showing a first source storage block and a first bitmap according to an embodiment of the present disclosure, Figure 9 This is a schematic diagram of a second source storage block and a second bitmap according to an embodiment of the present disclosure. Figures 7 to 9 The memory system provided by the embodiment of the present disclosure is exemplarily described.

[0050] Reference Figure 7 As shown, the memory system 600 includes a memory controller 610 and a memory 620 coupled to the memory controller 610. The memory controller 610 and the memory 620 can be coupled in any suitable manner. The memory controller 610 includes a processor 611, a buffer 612, a host interface 613, a memory interface 614, etc. Of course, the memory controller 610 may also include other circuits or modules not shown.

[0051] In some embodiments, the host interface 613 will receive data from the host (e.g., Figure 1The processor 611 outputs requests, data, and the like received from the host 108 to the internal bus, and transmits data read from the memory 620 and responses from the processor 611 to the host. The memory interface 614 controls the writing of data to the memory 620 and the reading of data from the memory 620 based on instructions from the processor 611. The processor 611 controls the memory system 600 as a whole. The processor 611 is, for example, a central processing unit (CPU) or a microprocessor unit (MPU). When the processor 611 receives a request from the host via the host interface 613, it performs control based on the request. For example, the processor 611 instructs the memory interface 614 to write data to the memory 620 in response to a write request from the host. Furthermore, the processor 611 instructs the memory interface 614 to read data from the memory 620 in response to a read request from the host.

[0052] It should be noted that the processor 611 described in the embodiment of the present disclosure may include multiple functional modules, and each functional module of the processor 611 may be a software module running on a processor that is part of the processor 611 (for example, a microcontroller unit (MCU)), or may be a hardware module of a finite state machine (FSM) (for example, an integrated circuit (IC, such as an application-specific IC (ASIC), a field-programmable gate array (FPGA)), etc.), or may be a combination of software modules and hardware modules.

[0053] In some embodiments, the memory controller 610 is configured to perform mapping management on data stored in the memory 620. Specifically, the memory controller 610 may update and maintain an L2P table. Each mapping entry in the L2P table may represent a mapping relationship between a logical address and a physical address. When a host sends a read request including a logical address to the memory controller 610, the memory controller 610 may obtain the corresponding physical address based on the L2P table and the logical address in the read request, read the data from the memory 620 based on the physical address, and send the data to the host.

[0054] In some embodiments, the memory controller 610 includes a buffer 612, which may include, but is not limited to, a static random-access memory (SRAM). Furthermore, the memory system 600 also includes a memory for storing the L2P table, such as a dynamic random-access memory (DRAM). The memory controller 610 can quickly obtain the L2P table from the DRAM, thereby achieving higher read efficiency. The DRAM can be located inside or outside the memory controller 610. Of course, in other embodiments, the L2P table can be stored in a three-dimensional NAND memory, and the L2P table is loaded into the memory controller 610 when the memory system 600 is powered on.

[0055] The memory 620 includes a memory cell array 621 and a peripheral circuit 622 coupled to the memory cell array 621. The memory cell array 621 includes a plurality of memory blocks, and the memory blocks include a plurality of physical pages. Figure 7 N memory blocks are shown, which are respectively denoted as block0, block1, ... block(N-1); each memory block may include m physical pages, which are respectively denoted as page0, page1, ... page(m-1); wherein N and m are both integers greater than 1. The memory 620 may include the following: Figures 3 to 5 The three-dimensional NAND memory shown in FIG. 1 is currently mainly programmed (also called written) in units of physical pages and erased in units of memory blocks.

[0056] In some embodiments, the memory controller 610 is configured to: determine at least one source storage block among a plurality of storage blocks; in response to a bitmap type associated with a first source storage block among the at least one source storage block being a first bitmap, write valid data stored in the first source storage block to a first target storage block among the plurality of storage blocks; wherein the first bitmap includes at least one first logical value, and the first logical value is used to identify a physical page storing valid data among a plurality of physical pages of the storage block; the first target storage block is different from the source storage block; and in response to valid data being written to the first target storage block, erase the source storage block.

[0057] In this embodiment, when performing a garbage collection operation, the memory controller 610 can select at least one storage block from multiple storage blocks as a source storage block, and obtain a bitmap associated with the source storage block; when the bitmap type associated with the source storage block is a first bitmap, the memory controller 610 can search the L2P table according to the first logical value in the first bitmap, determine the physical address of the physical page corresponding to the first logical value, and read the valid data stored in the physical page based on the physical address; after writing the read valid data into the first target storage block, erase the first source storage block, thereby obtaining a usable storage block.

[0058] It should be noted that the memory controller 610 can classify and manage multiple storage blocks in the memory 620. Specifically, the multiple storage blocks can be divided into occupied blocks, free blocks, bad blocks, etc. according to their usage, wherein an occupied block represents a storage block that stores data, a free block represents a storage block that does not store data, and a bad block represents a storage block that cannot be used normally. Here, the free block can be an unused storage block or a storage block that can still be used normally after being erased. Therefore, when performing a garbage collection operation, at least one occupied block can be selected from the multiple occupied blocks as a source storage block, and a free block can be selected from the multiple free blocks as a first target storage block. The first target storage block is used to receive valid data from the source storage block. For ease of understanding, the source storage block whose bitmap type is the first bitmap is recorded as the first source storage block.

[0059] The first bitmap may include a plurality of bits, each of which may be set to a first logic value or a third logic value to identify whether the data stored in the corresponding physical page in the first source memory block is valid. Figure 8 As shown, the first bitmap may include 144 bits, of which 127 bits are set to the first logic value, indicating that the data stored in the corresponding 127 physical pages is valid data; 17 bits are set to the third logic value, indicating that the data stored in the corresponding 17 physical pages is invalid data. The first logic value may be one of the logic values ​​"1" or "0", and the third logic value may be the other of the logic values ​​"1" or "0". In this embodiment, the first logic value is "0" and the third logic value is "1" for exemplary description. For the sake of simplicity, Figure 8 Only the third logic value "1" is shown in FIG, and the first logic value "0" is not shown. Here, the number of bits in the first bitmap, the number of first logic values, and the number of third logic values ​​are not limited to Figure 8 As shown, those skilled in the art can make reasonable settings according to actual conditions.

[0060] It is understandable that the data stored in the physical pages corresponding to all logical values ​​"0" in the first bitmap are all valid data. Therefore, when performing a garbage collection operation, the memory controller 610 can directly determine the physical address of the physical page storing valid data based on the number of logical values ​​"0" in the first bitmap, and no longer needs to search whether there is a valid mapping entry for the physical page corresponding to the logical value "0". In this way, on the one hand, the length of garbage collection can be reduced and the efficiency of garbage collection can be improved; on the other hand, when the data stored in the source storage block is very large or very random, the use of the first bitmap provided by the embodiment of the present disclosure can greatly improve the efficiency of garbage collection, which is more suitable for application scenarios with large data volumes or high data randomness.

[0061] Here, the garbage collection operation on the source memory block may be performed by firmware loaded into the memory controller 610. Specifically, the firmware may be loaded and executed on the processor 611 upon power-up. Valid data read from the first source memory block may be temporarily stored in the buffer 612 under the control of the processor 611. In one example, the firmware may be stored in the memory controller 610; in another example, the firmware may be stored in the memory 620.

[0062] It should be noted that the garbage collection operation includes foreground garbage collection (Foreground GC, FGC) and background garbage collection (Background GC, BGC). When the available storage space in the memory 620 is less than the total amount of written data, the memory controller 610 needs to perform garbage collection on the memory 620 to release enough storage space for data writing. The garbage collection at this time is a passive method, called foreground garbage collection; when the memory controller 610 is in an idle state, the memory controller 610 actively performs garbage collection on the memory 620 to release more storage space. The garbage collection at this time is an active method, called background garbage collection. The technical solution provided by the embodiment of the present disclosure can be implemented in at least one process of foreground garbage collection and background garbage collection to ensure that there is sufficient storage space in the memory 620 to store data. In a specific embodiment, the garbage collection operation can be a foreground garbage collection. Due to the reduction in the duration of garbage collection, write timeout can be avoided.

[0063] In some embodiments, the memory controller 610 is further configured to: in response to the bitmap type associated with the second source storage block in at least one source storage block being a second bitmap, determine the physical page storing data in the second source storage block; wherein the second bitmap includes at least one second logical value, the second logical value is used to identify the physical page storing data in multiple physical pages of the storage block, and the second logical value is different from the first logical value; in response to the logical-to-physical address mapping table, determine whether the data stored in the physical page storing data in the second source storage block is valid; in response to the data stored in the physical page storing data in the second source storage block being valid, write the valid data stored in the second source storage block to the first target storage block.

[0064] In this embodiment, when the bitmap type associated with the source storage block is the second bitmap, the memory controller 610 may search the L2P table based on the second logical value in the second bitmap to determine whether there is a valid mapping entry for the physical page corresponding to the second logical value. If a valid mapping entry exists, the memory controller 610 may determine the physical address of the physical page corresponding to the second logical value and read valid data stored in the physical page based on the physical address. After writing the read valid data to the first target storage block, the memory controller 610 may erase the second source storage block, thereby obtaining a usable storage block. For ease of understanding, the source storage block with the second bitmap type is referred to as the second source storage block.

[0065] The second bitmap may include a plurality of bits, each of which may be set to a second logic value or a fourth logic value to identify whether the corresponding physical page in the second source storage block stores data. Figure 9 As shown, the second bitmap may include 144 bits, of which 16 bits are set to the second logic value, indicating that the corresponding 16 physical pages store data; and 128 bits are set to the fourth logic value, indicating that the corresponding 128 physical pages do not store data. The second logic value may be one of the logic values ​​"1" or "0", and the fourth logic value may be the other of the logic values ​​"1" or "0". In this embodiment, the second logic value is "1" and the fourth logic value is "0" for exemplary description. For the sake of simplicity, Figure 9 Only the second logic value "1" is shown in the figure, and the fourth logic value "0" is not shown. Here, the number of bits in the second bitmap, the number of second logic values, and the number of fourth logic values ​​are not limited to Figure 9 As shown, those skilled in the art can make reasonable settings according to actual conditions.

[0066] It is understandable that the data stored in the physical pages corresponding to all logical values ​​"1" in the second bitmap may be valid data. Therefore, when performing a garbage collection operation, the memory controller 610 needs to check whether there are valid mapping entries for the physical pages corresponding to the logical value "1" in the second bitmap to avoid loss of valid data.

[0067] In actual applications, the degree of randomness of data stored in different source storage blocks may vary. If all source storage blocks that need to be garbage collected are marked with a single bitmap, for example, all source storage blocks are marked with Figure 6 As shown in the page table entry bitmap, for source storage blocks with a high degree of data randomness, the number of "1"s in the page table entry bitmap associated with them is large, which means that more L2P table searches are required, resulting in a longer garbage collection time. For another example, if all source storage blocks use Figure 8 As shown in the first bitmap, for a source storage block with a lower degree of data randomness, the number of "1"s in the first bitmap associated therewith is larger, which means that the bit of the first bitmap is set to "1" more times and the space occupied by the first bitmap increases, resulting in increased firmware overhead and storage space occupation.

[0068] Therefore, in the embodiments of the present disclosure, different types of bitmaps are designed specifically to take into account the differences between different source storage blocks. For example, a first bitmap can be used to identify source storage blocks with a higher degree of randomness; a second bitmap can be used to identify source storage blocks with a lower degree of randomness. This increases the flexibility of the bitmap design in the memory system. It is understandable that when the randomness of the source storage blocks is high, the garbage collection operation is more efficient based on the first bitmap; when the randomness of the source storage blocks is low, the garbage collection operation is more efficient based on the second bitmap. Those skilled in the art can make reasonable settings based on actual circumstances, and the present disclosure does not impose any special restrictions on this.

[0069] In some embodiments, the memory controller 610 is further configured to determine whether the bitmap type associated with the source memory block is the first bitmap or the second bitmap. Exemplarily, the memory controller 610 may generate different identification bits to record different bitmap types. For example, the memory controller 610 may generate a first identification bit, which is used to indicate the bitmap type of the first bitmap; the memory controller 610 may also generate a second identification bit, which is used to indicate the bitmap type of the second bitmap, and the second identification bit is different from the first identification bit.

[0070] In some embodiments, the first flag bit and the second flag bit may be represented by different logical values. For example, the first flag bit may be a logical value of "1" or "0," and the second flag bit may be a logical value of "1" or "0," and the present disclosure has no particular limitation on this.

[0071] In the embodiment of the present disclosure, by generating different identification bits, the type of the first bitmap or the second bitmap can be identified. By obtaining the identification bit of the bitmap associated with the source storage block, the type of the bitmap associated with the source storage block can be determined, thereby performing corresponding garbage collection operations. This is conducive to improving the efficiency of garbage collection.

[0072] In some embodiments, the memory controller 610 is configured to: in response to a first write command, write the first logical page data indicated by the first write command to an initial source storage block among multiple storage blocks; wherein the initial source storage block and the first target storage block are different; in response to the first logical page data being written to the initial source storage block, update the initial bitmap associated with the initial source storage block; wherein the initial bitmap includes a first bitmap and a second bitmap; in response to the updated initial bitmap, determine the number of physical pages storing valid data in the initial source storage block; wherein the physical pages storing valid data in the initial source storage block are physical pages storing the first logical page data; in response to the number of physical pages storing valid data in the initial source storage block being greater than a preset threshold, save the first bitmap to the memory 620.

[0073] For example, the memory controller 610 may generate a first write signal in response to a first write command, and send the first write signal and the first logical page data to the memory 620 via the memory interface 614. The peripheral circuit 622 may write the first logical page data to the memory cell array 621 in response to the first write signal, for example, to at least one physical page of the initial source memory block. Here, the first write command includes at least one of a sequential write command and a random write command.

[0074] After writing the first logical page data to the initial source storage block, the processor 611 may update the L2P table and the initial bitmap associated with the initial source storage block. For example, for the physical page to which the logical page data is written, the corresponding bits in the first bitmap and the second bitmap may be updated to a logical value of "1." It will be appreciated that the more physical pages to which the logical page data is written, the greater the number of logical values ​​"1" in the first bitmap and the second bitmap. In actual applications, the processor 611 may generate an initial bitmap associated with the initial source storage block when writing data to the initial source storage block for the first time, and update the initial bitmap after the data is written to the initial source storage block.

[0075] After updating the initial bitmap, the processor 611 may count the number of logical values ​​"1" in the first bitmap to determine the number of physical pages storing valid data in the initial source storage block; when the number of logical values ​​"1" in the first bitmap is greater than a preset threshold, all bits in the first bitmap may be set to a logical value "0" (i.e., a first logical value), and then the first bitmap may be saved to the memory 620. Here, the processor 611 may initialize the first bitmap (i.e., reset the first bitmap) when the number of logical values ​​"1" in the first bitmap is greater than a preset threshold. Of course, in other embodiments, the processor 611 may also count the number of logical values ​​"1" in the second bitmap to determine the number of physical pages storing valid data in the initial source storage block.

[0076] It can be understood that in the embodiment of the present disclosure, when writing data to the initial source storage block, two different types of bitmaps can be generated. When the number of physical pages storing valid data in the initial source storage block exceeds a preset threshold, the second bitmap can be deleted and only the first bitmap can be retained, and the first bitmap can be saved to the memory 620. Since the first logical value in the first bitmap is used to identify the physical page storing valid data in the associated storage block, when the initial source storage block corresponding to the first bitmap is selected as the source storage block, the efficiency of garbage collection of source storage blocks with a higher degree of randomness can be improved.

[0077] In some embodiments, the memory controller 610 is further configured to: in response to the number of physical pages storing valid data in the initial source memory block being less than or equal to a preset threshold, save the second bitmap to the memory 620. As described in the above embodiment, when it is determined that the number of physical pages storing valid data in the initial source memory block is less than or equal to the preset threshold, the second bitmap may be saved to the memory 620. Here, the logical value "1" in the second bitmap is the above-mentioned second logical value.

[0078] It can be understood that in the embodiment of the present disclosure, when the number of physical pages storing valid data in the initial source storage block does not exceed a preset threshold, the first bitmap can be deleted and only the second bitmap can be retained, and the second bitmap can be saved in the memory 620. Since the number of second logical values ​​in the second bitmap is small, when the initial source storage block corresponding to the second bitmap is selected as the source storage block, the efficiency of garbage collection of source storage blocks with a lower degree of randomness can be improved.

[0079] It should be noted that the preset threshold can be reasonably set based on the capacity of the storage block, and this disclosure does not impose any specific restrictions on this. In one specific example, the preset threshold is 70% of the total number of physical pages in the storage block. That is, when the number of physical pages storing valid data exceeds 70% of the total number of physical pages, the bitmap associated with the storage block is set to the first bitmap.

[0080] In some embodiments, the memory controller 610 is further configured to: generate a first identification bit in response to the first bitmap being saved to the memory 620, and save the first identification bit to the memory 620; generate a second identification bit in response to the second bitmap being saved to the memory 620, and save the second identification bit to the memory 620.

[0081] In the disclosed embodiment, after the first bitmap is saved to the memory 620, a corresponding first identification bit may be generated, where the first identification bit is used to indicate the bitmap type of the first bitmap. Thus, when the storage block corresponding to the first bitmap is selected as the source storage block, the processor 611 can determine that the bitmap associated with the storage block is the first bitmap by obtaining the corresponding first identification bit, thereby performing the corresponding garbage collection operation. The garbage collection operation process for the storage block corresponding to the first bitmap has been described in the above embodiment and will not be repeated here.

[0082] In the disclosed embodiment, after the second bitmap is saved to the memory, a corresponding second identification bit can be generated. The second identification bit is used to indicate the bitmap type of the second bitmap. Thus, when the storage block corresponding to the second bitmap is selected as the source storage block, the processor can determine that the bitmap associated with the storage block is the second bitmap by obtaining the corresponding second identification bit, thereby performing the corresponding garbage collection operation. The garbage collection operation process for the storage block corresponding to the second bitmap has been described in the above embodiment and will not be repeated here.

[0083] In addition, in the embodiment of the present disclosure, by saving at least one of the first identification bit and the second identification bit in the memory, the loss of the first identification bit and the second identification bit information can be avoided.

[0084] In some embodiments, the memory controller 610 is specifically configured to select at least one initial source memory block from a plurality of initial source memory blocks as a source memory block. Garbage collection operations are typically based on a greedy algorithm. Specifically, an initial source memory block that stores less valid data is selected as a source memory block. This reduces the time required to read valid data from the source memory block, thereby improving garbage collection efficiency. In practical applications, the algorithm for selecting a source memory block from a plurality of initial source memory blocks is not limited to this and may also be other algorithms known in the art.

[0085] It is understandable that, since the first logic value in the first bitmap is used to identify the physical page storing valid data, when selecting a source storage block from the initial source storage blocks corresponding to the first bitmap, the initial source storage block corresponding to the first bitmap having a smaller number of first logic values ​​can be directly selected, thereby further reducing the garbage collection time and improving the garbage collection efficiency.

[0086] In some embodiments, the memory controller 610 is configured to: in response to a second write command following the first write command, write the second logical page data indicated by the second write command to a second target storage block among the multiple storage blocks; wherein the second target storage block is different from the first target storage block; in response to the second logical page data being written to the second target storage block, update the logical-to-physical address mapping table; in response to the updated logical-to-physical address mapping table, determine whether the first logical page data is rewritten; in response to the first logical page data being rewritten, determine the bitmap type associated with the initial source storage block where the rewritten first logical page data is located; in response to the bitmap type associated with the rewritten initial source storage block being the first bitmap, update the first bitmap; in response to the bitmap type associated with the rewritten initial source storage block being the second bitmap, keep the second bitmap unchanged.

[0087] Exemplarily, the memory controller 610 may generate a second write signal in response to the second write command, and send the second write signal and the second logical page data to the memory 620 via the memory interface 614. The peripheral circuit 622 may write the second logical page data to the memory cell array 621 in response to the second write signal, for example, to at least one physical page of the second target memory block. Here, the second write command includes at least one of a sequential write command and a random write command, and the second target memory block may be at least one of an occupied block or a blank block. If the second target memory block is an occupied block, at least a portion of the second logical page data may be written to a blank physical page of the occupied block, i.e., a physical page that does not store data.

[0088] After writing the second logical page data to the second target storage block, the processor 611 can update the L2P table and determine whether the first logical page data is overwritten based on the updated L2P table; in the case of overwriting the first logical page data, the processor 611 determines the bitmap type associated with the initial source storage block where the rewritten first logical page data is located based on the obtained identification bit. For example, if the processor 611 obtains the first identification bit, the first bitmap associated with the initial source storage block is updated; if the processor 611 obtains the second identification bit, the second bitmap associated with the initial source storage block remains unchanged.

[0089] It should be noted that the updated L2P table records the mapping entries between the physical address and the logical address of the second logical page data. Searching the updated L2P table can determine the physical address of the second logical page data. When writing the second logical page data, if the logical address of the second logical page data is consistent with the logical address of the first logical page data, this is a data overwrite. The second logical page data will not overwrite the overwritten first logical page data, but will be written to another physical page. The overwritten first logical page data will be marked as garbage data (also known as invalid data). Therefore, by searching the updated L2P table, it can be determined whether the first logical page data has been overwritten.

[0090] In some embodiments, the first bitmap further includes at least one third logical value, the third logical value being used to identify a physical page storing invalid data among multiple physical pages of the storage block, and the third logical value is different from the first logical value; the memory controller 610 is specifically configured to: in response to the bitmap associated with the rewritten initial source storage block being the first bitmap, adjust the first logical value of the target in the first bitmap to the third logical value; wherein the first logical value of the target is used to identify the physical page where the rewritten first logical page data is located. Exemplarily, if a physical page of the initial source storage block is rewritten, the bit corresponding to the rewritten physical page in the first bitmap is adjusted from a logical value of "0" to a logical value of "1" to indicate that the data stored in the physical page has become invalid data.

[0091] The present disclosure provides a memory system, the memory system including a memory controller and a memory coupled to the memory controller, the memory including a plurality of memory blocks, the memory blocks including a plurality of physical pages; the memory controller is configured to: determine at least one source memory block among the plurality of memory blocks; in response to a bitmap type associated with a first source memory block in the at least one source memory block being a first bitmap, write valid data stored in the first source memory block to a first target memory block among the plurality of memory blocks, the first bitmap including at least one first logical value, the first logical value being used to identify a physical page storing valid data among a plurality of physical pages of the memory block; the first target memory block is different from the source memory block; in response to valid data being written to the first target memory block, erase the source memory block. Thus, in a first aspect, when performing a garbage collection operation, the physical address of the physical page storing valid data can be directly determined based on the number of the first logical values, without having to search whether there is a valid mapping entry for the physical page corresponding to the first logical value, thereby reducing the garbage collection time and improving the efficiency of garbage collection; in a second aspect, when the data stored in the source memory block is very large or very random, the first bitmap provided by the embodiment of the present disclosure can greatly improve the efficiency of garbage collection, and is more suitable for application scenarios with large data volumes or high data randomness.

[0092] Based on the above memory system, an embodiment of the present disclosure further provides an operating method of the memory system.

[0093] Figure 10 This is a flowchart illustrating a method for operating a memory system according to an embodiment of the present disclosure. The method includes at least the following steps:

[0094] S710: Determine at least one source storage block among a plurality of storage blocks;

[0095] S720: In response to a bitmap type associated with a first source storage block in at least one source storage block being a first bitmap, write valid data stored in the first source storage block to a first target storage block in the plurality of storage blocks; wherein the first bitmap includes at least one first logical value, the first logical value being used to identify a physical page in the plurality of physical pages of the storage block that stores valid data; and the first target storage block is different from the source storage block.

[0096] S730: In response to valid data being written into the first target memory block, erasing the source memory block.

[0097] In some embodiments, the above-mentioned operating method also includes: in response to the bitmap type associated with the second source storage block in at least one source storage block being a second bitmap, determining the physical page storing data in the second source storage block; wherein the second bitmap includes at least one second logical value, the second logical value is used to identify the physical page storing data in multiple physical pages of the storage block, and the second logical value is different from the first logical value; in response to the logical-to-physical address mapping table, judging whether the data stored in the physical page storing data in the second source storage block is valid; in response to the data stored in the physical page storing data in the second source storage block being valid, writing the valid data stored in the second source storage block to the first target storage block.

[0098] In some embodiments, the above operation method further includes: determining whether the bitmap type associated with the source storage block is the first bitmap or the second bitmap.

[0099] In some embodiments, the above-mentioned operating method also includes: in response to a first write command, writing the first logical page data indicated by the first write command to an initial source storage block among multiple storage blocks; wherein, the initial source storage block and the first target storage block are different; in response to the first logical page data being written to the initial source storage block, updating the initial bitmap associated with the initial source storage block; wherein, the initial bitmap includes a first bitmap and a second bitmap; in response to the updated initial bitmap, determining the number of physical pages storing valid data in the initial source storage block; wherein, the physical pages storing valid data in the initial source storage block are physical pages storing the first logical page data; in response to the number of physical pages storing valid data in the initial source storage block being greater than a preset threshold, saving the first bitmap to the memory.

[0100] In some embodiments, the above operating method further includes: in response to the number of physical pages storing valid data in the initial source memory block being less than or equal to a preset threshold, saving the second bitmap to the memory.

[0101] In some embodiments, the above-mentioned operating method further includes: in response to the first bitmap being saved to the memory, generating a first identification bit, and saving the first identification bit to the memory; wherein, the first identification bit is used to indicate the bitmap type of the first bitmap; in response to the second bitmap being saved to the memory, generating a second identification bit, and saving the second identification bit to the memory; wherein, the second identification bit is used to indicate the bitmap type of the second bitmap, and the second identification bit is different from the first identification bit.

[0102] In some embodiments, the determining of at least one source storage block from the plurality of storage blocks includes: selecting at least one initial source storage block from a plurality of initial source storage blocks as the source storage block.

[0103] In some embodiments, the above-mentioned operation method also includes: in response to a second write command after the first write command, writing the second logical page data indicated by the second write command to a second target storage block among multiple storage blocks; wherein the second target storage block is different from the first target storage block; in response to the second logical page data being written to the second target storage block, updating the logical-to-physical address mapping table; in response to the updated logical-to-physical address mapping table, determining whether the first logical page data is rewritten; in response to the rewriting of the first logical page data, determining the bitmap type associated with the initial source storage block where the rewritten first logical page data is located; in response to the bitmap type associated with the rewritten initial source storage block being the first bitmap, updating the first bitmap.

[0104] In some embodiments, the above operation method further includes: in response to the bitmap type associated with the rewritten initial source storage block being the second bitmap, keeping the second bitmap unchanged.

[0105] In some embodiments, the first bitmap also includes at least one third logical value, and the third logical value is used to identify a physical page storing invalid data among multiple physical pages of the storage block, and the third logical value is different from the first logical value; the bitmap type associated with the above-mentioned initial source storage block in response to the rewrite is the first bitmap, and updating the first bitmap includes: in response to the bitmap associated with the initial source storage block in the rewrite being the first bitmap, adjusting the first logical value of the target in the first bitmap to the third logical value; wherein the first logical value of the target is used to identify the physical page where the first logical page data is located where the rewrite occurs.

[0106] In the embodiments of the present disclosure, the memory system operating method can be executed by the memory controller in the memory system of any of the aforementioned embodiments. The technical effects achieved by the memory system in the aforementioned embodiments can also be achieved by the memory system operating method of this memory system, and will not be described in detail here. Regarding the operating method in the aforementioned embodiments, the specific implementation of each step has been described in detail in the relevant device embodiments and will not be elaborated on here.

[0107] Figure 11This is a flow chart showing a method of generating a first bitmap or a second bitmap according to an embodiment of the present disclosure. Figure 11 The operating method of the memory system provided in the embodiment of the present disclosure is exemplarily described.

[0108] Reference Figure 11 As shown, in step S810: Programming. Here, the memory controller may generate a write signal in response to a write command, and the peripheral circuit may program an initial source memory block among the multiple memory blocks in response to the write signal to write the logical page data to the initial source memory block. Of course, the memory controller may also program reread data to the initial source memory block during a garbage collection operation.

[0109] In step S820: bits of the initial bitmap are set according to the logical address. Here, after the logical page data is written to the physical page of the initial source storage block, the processor may set the corresponding bit in the initial bitmap associated with the initial source storage block to a logical value of "1". The initial bitmap includes a first bitmap and a second bitmap. For details about the initial bitmap, please refer to the detailed description of the above embodiment and will not be repeated here.

[0110] In step S830: the L2P table is updated. Here, the logical page data written to the initial source storage block can be one or more entries. Each time a logical page data entry is written, the L2P table is updated once to avoid data loss. In a specific example, a logical page data entry can be 4KB.

[0111] Step S830 may include step S831: determining whether the bitmap type associated with the rewritten storage block is a first bitmap. Here, whether data rewriting occurs may be determined based on the updated L2P table. If rewriting occurs, the identification bit of the rewritten storage block may be obtained to determine the bitmap type associated with the rewritten storage block.

[0112] If the first flag is obtained, it can be determined that the bitmap associated with the overwritten storage block is the first bitmap, and step S832 is executed: the bit overwritten in the first bitmap is set to "1". Here, the overwritten storage block and the original source storage block are different storage blocks. If the second flag is obtained, the next data is written and the L2P table is updated again until the end of the original source storage block is reached, that is, step S840. Here, writing to the end of the original source storage block can be understood as the original storage block is about to be filled with data.

[0113] Step S840 may include step S841: counting the number of "1"s in the second bitmap; and step S842: determining whether the count is greater than a preset threshold. By counting the number of "1"s in the second bitmap associated with the initial source storage block, the number of physical pages storing valid data in the initial source storage block can be determined. When the number of logical "1"s is greater than the preset threshold, step S850 may be executed. Here, the number of logical "1"s in the first bitmap associated with the initial source storage block may also be counted.

[0114] In step S850, the first bitmap is initialized, the initialized first bitmap is saved, and the bitmap type is recorded. Here, all bits in the first bitmap can be initialized to a logical value of "0" to identify the physical page storing valid data in the initial source storage block, and the initialized first bitmap is saved to the memory; a first identification bit can also be generated to identify the bitmap type associated with the initial source storage block as the first bitmap.

[0115] When the number of logical values ​​"1" is less than or equal to a preset threshold, step S860 may be executed: saving the second bitmap and recording the bitmap type. Here, the second bitmap may be directly saved to the memory, and the logical value "1" in the second bitmap is used to identify the physical page storing the data. A second identification bit may also be generated to identify the bitmap type associated with the original source storage block as the second bitmap.

[0116] At this point, a first bitmap associated with the initial source storage block may be generated by executing the above steps S810 to S840 and S850; or a second bitmap associated with the initial source storage block may be generated by executing the above steps S810 to S840 and S860.

[0117] Figure 12 This is a flowchart of a garbage collection operation according to an embodiment of the present disclosure. Figure 12 The operating method of the memory system provided in the embodiment of the present disclosure is exemplarily described.

[0118] Reference Figure 12 As shown, in step S910: determine the source storage block. Here, an initial source storage block storing less valid data can be selected as the source storage block based on a greedy algorithm. The number of source storage blocks can be one or more, and the bitmap types of any two source storage blocks among the multiple source storage blocks can be the same or different.

[0119] In step S920, a determination is made as to whether the bitmap associated with the source storage block is the first bitmap. Here, the determination of whether the bitmap associated with the source storage block is the first bitmap can be based on whether the flag bit in the bitmap associated with the source storage block is the first flag bit. If so, step S930 is executed to directly determine the valid data information. Specifically, based on the logical value "0" in the first bitmap, the L2P table is directly searched to determine the physical address of the physical page storing the valid data, and the valid data is read based on the physical address.

[0120] If not, it is determined that the bitmap associated with the source storage block is the second bitmap, and step S940 is executed: a valid mapping entry is retrieved based on the second bitmap. Specifically, the L2P table is directly searched based on the logical value "1" in the second bitmap to determine whether a mapping entry exists for the physical page storing the data. If a mapping entry exists, the physical address of the physical page storing the valid data is determined, and the valid data is read based on the physical address.

[0121] After reading the valid data, step S950 is executed: the valid data is migrated from the source storage block to the target storage block. After the valid data migration is completed, the source storage block is erased to obtain an available storage block.

[0122] At this point, by executing the above steps S910 to S950, the garbage collection operation can be completed.

[0123] Based on the above memory system, an embodiment of the present disclosure further provides a computer-readable storage medium, on which instructions are stored. When the instructions are executed by a processor, an operating method as in any of the above embodiments is implemented.

[0124] Here, to implement all or part of the processes in the operating methods of the above embodiments, hardware associated with instructions (e.g., computer programs) may be used. The computer programs may be stored in a computer-readable storage medium, and the execution of the computer program may include the processes of the operating methods in any of the above embodiments. The computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive, etc. The computer-readable storage medium may also include a combination of multiple storage media.

[0125] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0126] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0127] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0128] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0129] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system, characterized in that: The memory system includes a memory controller and a memory coupled to the memory controller, wherein the memory includes a plurality of memory blocks, each of which includes a plurality of physical pages; and the memory controller is configured to: determining at least one source memory block among the plurality of memory blocks; In response to a bitmap type associated with a first source storage block among the at least one source storage block being a first bitmap, writing valid data stored in the first source storage block to a first target storage block among the multiple storage blocks; wherein the first bitmap includes at least one first logical value, the first logical value being used to identify a physical page among multiple physical pages of the storage block that stores the valid data; and the first target storage block is different from the source storage block; In response to the valid data being written into the first target memory block, the source memory block is erased.

2. The memory system according to claim 1, wherein: The memory controller is further configured to: In response to a second source storage block in the at least one source storage block being associated with a second bitmap type being a second bitmap, determining a physical page storing data in the second source storage block; wherein the second bitmap includes at least one second logical value, the second logical value being used to identify a physical page storing data in a plurality of physical pages of the storage block, the second logical value being different from the first logical value; In response to the logical-to-physical address mapping table, determining whether data stored in a physical page storing data in the second source storage block is valid; In response to data stored in a physical page storing data in the second source memory block being valid, the valid data stored in the second source memory block is written to the first target memory block.

3. The memory system according to claim 2, wherein: The memory controller is further configured to: It is determined whether the bitmap type associated with the source storage block is the first bitmap or the second bitmap.

4. The memory system according to claim 2 or 3, characterized in that: The memory controller is configured to: In response to a first write command, writing the first logical page data indicated by the first write command into an initial source memory block among the plurality of memory blocks; wherein the initial source memory block is different from the first target memory block; In response to the first logical page data being written into the initial source storage block, updating an initial bitmap associated with the initial source storage block; wherein the initial bitmap includes the first bitmap and the second bitmap; In response to the updated initial bitmap, determining the number of physical pages storing valid data in the initial source storage block; wherein the physical pages storing valid data in the initial source storage block are physical pages storing the first logical page data; In response to the number of physical pages storing valid data in the initial source memory block being greater than a preset threshold, the first bitmap is saved to the memory.

5. The memory system according to claim 4, wherein: The memory controller is further configured to: In response to the number of physical pages storing valid data in the initial source memory block being less than or equal to the preset threshold, the second bitmap is saved to the memory.

6. The memory system according to claim 5, wherein: The memory controller is further configured to: In response to the first bitmap being saved in the memory, generating a first identification bit, and saving the first identification bit in the memory; wherein the first identification bit is used to indicate a bitmap type of the first bitmap; In response to the second bitmap being saved to the memory, a second identification bit is generated and the second identification bit is saved to the memory; wherein the second identification bit is used to indicate the bitmap type of the second bitmap, and the second identification bit is different from the first identification bit.

7. The memory system according to claim 4 or 5, characterized in that: The memory controller is specifically configured as follows: At least one of the initial source memory blocks is selected from a plurality of the initial source memory blocks as the source memory block.

8. The memory system according to claim 5, wherein: The memory controller is configured to: In response to a second write command following the first write command, write the second logical page data indicated by the second write command into a second target storage block among the plurality of storage blocks; wherein the second target storage block is different from the first target storage block; In response to the second logical page data being written into the second target storage block, updating the logical-to-physical address mapping table; In response to the updated logical-to-physical address mapping table, determining whether the first logical page data is rewritten; In response to the rewriting of the first logical page data, determining a bitmap type associated with the original source storage block where the rewritten first logical page data is located; In response to the bitmap type associated with the rewritten original source storage block being the first bitmap, the first bitmap is updated.

9. The memory system according to claim 8, wherein: The memory controller is further configured to: In response to the bitmap type associated with the rewritten original source storage block being the second bitmap, the second bitmap is kept unchanged.

10. The memory system according to claim 8, wherein: The first bitmap further includes at least one third logical value, the third logical value being used to identify a physical page storing invalid data among the multiple physical pages of the memory block, and the third logical value is different from the first logical value; the memory controller is specifically configured to: In response to the bitmap associated with the rewritten initial source storage block being the first bitmap, the first logical value of the target in the first bitmap is adjusted to the third logical value; wherein the first logical value of the target is used to identify the physical page where the first logical page data is rewritten.

11. A method for operating a memory system, characterized in that: The memory system includes a memory controller and a memory coupled to the memory controller, the memory includes a plurality of memory blocks, and the memory blocks include a plurality of physical pages; the operating method includes: determining at least one source memory block among the plurality of memory blocks; In response to a bitmap type associated with a first source storage block among the at least one source storage block being a first bitmap, writing valid data stored in the first source storage block to a first target storage block among the multiple storage blocks; wherein the first bitmap includes at least one first logical value, the first logical value being used to identify a physical page among multiple physical pages of the storage block that stores the valid data; and the first target storage block is different from the source storage block; In response to the valid data being written into the first target memory block, the source memory block is erased.

12. The operating method according to claim 11, characterized in that: The operation method further includes: In response to a second source storage block in the at least one source storage block being associated with a second bitmap type being a second bitmap, determining a physical page storing data in the second source storage block; wherein the second bitmap includes at least one second logical value, the second logical value being used to identify a physical page storing data in a plurality of physical pages of the storage block, the second logical value being different from the first logical value; In response to the logical-to-physical address mapping table, determining whether data stored in a physical page storing data in the second source storage block is valid; In response to data stored in a physical page storing data in the second source memory block being valid, the valid data stored in the second source memory block is written to the first target memory block.

13. The operating method according to claim 12, characterized in that: The operation method further includes: It is determined whether the bitmap type associated with the source storage block is the first bitmap or the second bitmap.

14. The operating method according to claim 12 or 13, characterized in that: The operation method further includes: In response to a first write command, writing the first logical page data indicated by the first write command into an initial source memory block among the plurality of memory blocks; wherein the initial source memory block is different from the first target memory block; In response to the first logical page data being written into the initial source storage block, updating an initial bitmap associated with the initial source storage block; wherein the initial bitmap includes the first bitmap and the second bitmap; In response to the updated initial bitmap, determining the number of physical pages storing valid data in the initial source storage block; wherein the physical pages storing valid data in the initial source storage block are physical pages storing the first logical page data; In response to the number of physical pages storing valid data in the initial source memory block being greater than a preset threshold, the first bitmap is saved to the memory.

15. The operating method according to claim 14, characterized in that: The operation method further includes: In response to the number of physical pages storing valid data in the initial source memory block being less than or equal to the preset threshold, the second bitmap is saved to the memory.

16. The operating method according to claim 15, characterized in that: The operation method further includes: In response to the first bitmap being saved in the memory, generating a first identification bit, and saving the first identification bit in the memory; wherein the first identification bit is used to indicate a bitmap type of the first bitmap; In response to the second bitmap being saved to the memory, a second identification bit is generated and the second identification bit is saved to the memory; wherein the second identification bit is used to indicate the bitmap type of the second bitmap, and the second identification bit is different from the first identification bit.

17. The operating method according to claim 14 or 15, characterized in that: The determining of at least one source storage block among the plurality of storage blocks comprises: At least one of the initial source memory blocks is selected from a plurality of the initial source memory blocks as the source memory block.

18. The operating method according to claim 15, characterized in that: The operation method further includes: In response to a second write command following the first write command, write the second logical page data indicated by the second write command into a second target storage block among the plurality of storage blocks; wherein the second target storage block is different from the first target storage block; In response to the second logical page data being written into the second target storage block, updating the logical-to-physical address mapping table; In response to the updated logical-to-physical address mapping table, determining whether the first logical page data is rewritten; In response to the rewriting of the first logical page data, determining a bitmap type associated with the original source storage block where the rewritten first logical page data is located; In response to the bitmap type associated with the rewritten original source storage block being the first bitmap, the first bitmap is updated.

19. The operating method according to claim 18, characterized in that: The operation method further includes: In response to the bitmap type associated with the rewritten original source storage block being the second bitmap, the second bitmap is kept unchanged.

20. The operating method according to claim 18, characterized in that: The first bitmap further includes at least one third logic value, the third logic value being used to identify a physical page storing invalid data among the plurality of physical pages of the storage block, and the third logic value is different from the first logic value; The bitmap type associated with the rewritten initial source storage block is the first bitmap, and updating the first bitmap includes: In response to the bitmap associated with the rewritten initial source storage block being the first bitmap, the first logical value of the target in the first bitmap is adjusted to the third logical value; wherein the first logical value of the target is used to identify the physical page where the first logical page data is rewritten.

21. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed by a processor, the operating method according to any one of claims 11 to 20 is implemented.

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