PCIe BAR space mapping method, system and device of data stream processor and medium

Abstract

The invention relates to the technical field of servers, and particularly provides a PCIe BAR space mapping method, system and device for a data stream processor and a medium, and the method comprises the steps: reading the configuration space information of a PCIe device, and determining the total size of a memory space needing to be used by the data stream processor based on the configuration space information; obtaining the size of a special memory of each computing core; determining the size of a DDR (Double Data Rate) memory area for task calculation according to the total size of the memory space and the size of the special memory; instantiating a static container for a special memory equipped for each computing core, and instantiating a dynamic container for the DDR memory area; and distributing different BAR spaces for the static container and the dynamic container. According to the method, through a dual-mode address mapping mechanism of the static container and the dynamic container, the key problem that a 32-bit PCIe BAR space cannot support super 4GB memory access of a data stream processor is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of servers, and in particular relates to a PCIe BAR space mapping method, system, device and medium for a data stream processor. Background Art

[0002] A data flow processor refers to a processor designed with a data flow architecture. Unlike processors with a von Neumann architecture, processors with a data flow architecture drive the computing process through data flow rather than conventional instruction flow.

[0003] In traditional PCIe device designs, the Base Address Register (BAR) space is allocated using a 32-bit addressing scheme. This design has certain drawbacks: the 32-bit BAR space only supports a maximum physical address space of 4GB, which cannot meet the large-scale memory mapping requirements of data flow processors (such as deep learning model parameters). Therefore, how to solve the problem of large-capacity memory access in the 32-bit BAR space without changing the hardware design has become a research issue. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a PCIe BAR space mapping method, system, device and medium for a data stream processor to solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a PCIe BAR space mapping method for a data stream processor, comprising: Read the configuration space information of the PCIe device, and determine the total size of the memory space required by the data stream processor based on the configuration space information; Get the dedicated memory size of each computing core; Determining the size of the DDR memory area used for task calculation according to the total size of the memory space and the size of the dedicated memory; Instantiate a static container for the dedicated memory of each computing core, and instantiate a dynamic container for the DDR memory area; Allocate different BAR spaces for static containers and dynamic containers.

[0006] In an optional embodiment, reading configuration space information of a PCIe device and determining a total size of memory space required to be used by a data stream processor based on the configuration space information includes: During the PCIe device enumeration phase, the required memory size is obtained by accessing the configuration space of the PCIe device; Sum up the memory space required by all PCIe devices to obtain the total memory space.

[0007] In an optional embodiment, the method further includes: If it is confirmed that the total size of the memory space exceeds the set threshold, a dual-mode address mapping mechanism is enabled, where the dual-mode address mapping mechanism is used to map the dedicated memory and DDR memory areas of the computing core to different BAR spaces respectively.

[0008] In an optional embodiment, obtaining the dedicated memory size of each computing core includes: Read the hardware parameters of the data stream processor through the kernel driver interface; The number of various computing cores and the size of the dedicated memory equipped for each computing core are analyzed based on the hardware parameters.

[0009] In an optional embodiment, the core parameters of the static container include: The compute core base address is the starting address of the PCIe bus address space allocated for the dedicated memory area of ​​the compute core during instantiation. Computes the size of the core's own private memory.

[0010] In an optional embodiment, the dynamic container manages a set of variable number of memory blocks, each block representing a continuous task data storage area; The core parameters of the memory block include: The memory block base address is used to indicate the starting address of the task data block in the PCIe bus address space; The space size is used to indicate the length of the task data block.

[0011] In an optional embodiment, the method further includes: During the execution of computing tasks, the dynamic container adopts a prefetching strategy, which includes: Based on the analysis of the task queue, predict the data blocks that need to be accessed in the next computing phase; The dynamic container establishes the physical address mapping of these predicted data blocks in advance.

[0012] In a second aspect, the present invention provides a PCIe BAR space mapping system for a data stream processor, comprising: A first acquisition module is configured to read configuration space information of a PCIe device and determine a total size of memory space required by a data stream processor based on the configuration space information; The second acquisition module is used to obtain the dedicated memory size of each computing core; A memory calculation module, configured to determine the size of a DDR memory area used for task calculation based on the total size of the memory space and the size of the dedicated memory; A container construction module, configured to instantiate a static container for the dedicated memory of each computing core and a dynamic container for the DDR memory area; The space mapping module is used to allocate different BAR spaces to static containers and dynamic containers.

[0013] According to a third aspect, a device is provided, comprising: A memory for storing a PCIe BAR space mapping program of a data stream processor; The processor is configured to implement the steps of the PCIe BAR space mapping method for the data stream processor provided in the first aspect when executing the PCIe BAR space mapping program of the data stream processor.

[0014] In a fourth aspect, a computer-readable medium is provided, on which a PCIe BAR space mapping program of a data stream processor is stored. When the PCIe BAR space mapping program of the data stream processor is executed by a processor, the steps of the PCIe BAR space mapping method of the data stream processor provided in the first aspect are implemented.

[0015] This invention solves the key problem that the 32-bit PCIe BAR space cannot support data flow processors with memory access exceeding 4GB through an innovative "static container + dynamic container" dual-mode address mapping mechanism. The specific effects are as follows: 1) Breaking through the 32-bit address space limitation Dynamic containers use a block-based key-value management mechanism to break down a single large memory request into multiple dynamically mappable sub-blocks. By loading and unloading memory block mappings on demand, they enable seamless expansion of the physical address space and support terabyte-level memory access without hardware modifications.

[0016] 2) Resource utilization optimization Static container: solidifies the register / local memory mapping of the computing core (such as instruction cache and configuration registers) to ensure zero-latency access to core basic functions.

[0017] Dynamic container: Dynamically maps DDR data blocks (such as model parameters) only when actual computing tasks are triggered, avoiding long-term occupation of BAR space. 3) Significant performance improvement Dynamic containers use a prefetching strategy: they predict the data blocks required for the next computing phase based on the task queue, establish mappings in advance, and reduce mapping switching delays.

[0018] The key-value pair design supports O(1) complexity address translation, eliminating the table lookup overhead of the traditional paging mechanism.

[0019] 4) Enhance system stability Isolate core function memory from task data memory: A computing core crash will not pollute the dynamic mapping area. Task failure only requires resetting the corresponding dynamic container, reducing system recovery time to milliseconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

[0022] Figure 2 FIG. 4 is a schematic block diagram of a system according to an embodiment of the present invention.

[0023] Figure 3 A schematic structural diagram of a device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0026] The PCIe BAR space mapping method for a data stream processor provided by an embodiment of the present invention is executed by a computer device. Accordingly, the PCIe BAR space mapping system for a data stream processor runs in the computer device.

[0027] Figure 1 This is a schematic flow chart of a method according to an embodiment of the present invention. Figure 1 The present invention proposes a PCIe BAR space mapping method for data flow processors. Through the "static container + dynamic container" dual-mode address mapping mechanism, it solves the key problem that the 32-bit PCIe BAR space cannot support data flow processors to access memory exceeding 4GB.

[0028] The main steps include: (1) During the PCIe device enumeration phase, the host reads the configuration space information of the PCIe device to obtain the total size of the memory space required by the data stream processor. If the required memory space is greater than 4G, the dual-mode address mapping mechanism is used.

[0029] (2) Obtain detailed parameter information of the data stream processor through the kernel driver interface, and determine the configuration information such as the number of various computing cores of the data stream processor and the size of the memory of each processing core.

[0030] (3) Establishing a data stream processor address mapping model. The address mapping model is constructed based on the information obtained in steps 1 and 2. The construction method is to use a static container class to instantiate a container for the memory space required by the computing core itself, and a dynamic container class to instantiate a container for the DDR memory area storing computing task data. Different BAR spaces are allocated for static containers and dynamic containers.

[0031] (4) The static container class contains two basic parameters: the computing core base address and the space size; the computing core base address is the starting address of the PCI address space allocated to the computing core when the static container is instantiated, and the space size is the memory space size required by the computing core itself obtained in step 2.

[0032] (5) The dynamic container class contains a set of key-value pairs. The number of key-value pairs is determined by the scale of data processed by the computing task. The key-value pairs also contain two basic parameters: the memory block base address and the space size. The memory block base address is when the dynamic container is instantiated. The memory space required for the computing task is divided into blocks, and the starting address of each block is used as the base address of the key-value pair. The length of each block is used as the space size of the key-value pair. The number of blocks is the number of key-value pairs instantiated in the dynamic container.

[0033] (6) When executing computing tasks, the dynamic container adopts a prefetching strategy to predict the data blocks required for the next computing stage based on the task queue, establish a mapping in advance, and reduce the mapping switching delay.

[0034] In one embodiment of the present invention, the order of the steps of the method may be changed, and some steps may be omitted, depending on different requirements. The method includes: S1 reads the configuration space information of the PCIe device and determines the total size of the memory space required by the data flow processor based on the configuration space information; S2. Obtain the dedicated memory size of each computing core; S3 based on the total size of the memory space and the dedicated memory size, determine the size of the DDR memory area used for task calculation; S4 are dedicated memory instantiation static container for each computing core equipped with its own, and instantiate dynamic container for the DDR memory area; S5. Allocate different BAR spaces for static containers and dynamic containers.

[0035] In an embodiment of the present invention, based on step S1, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0036] During the PCIe device enumeration phase at system startup, the host accesses the target device's configuration space to obtain the total memory size required. If the required memory size exceeds 4GB, the dual-mode address mapping mechanism is enabled and steps 2-5 are executed. If the total memory size does not exceed 4GB, steps 2-5 are not executed.

[0037] In an embodiment of the present invention, based on step S2, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0038] Through the kernel driver interface, the host further reads and analyzes the detailed hardware parameters of the data flow processor. These parameters include key configuration information such as the number of various computing cores and the size of each computing core's dedicated memory (such as SRAM and L2Cache).

[0039] The kernel driver communicates with the data stream processor through the standard Device Control Interface (DevCtrl). This interface provides a standardized command set covering functions such as parameter reading, configuration updates, and status queries. To obtain parameters, the driver first sends a parameter request command to the data stream processor. This command includes a specific identifier that specifies the required parameter type. Upon receiving the request, the data stream processor packages the hardware parameters stored in internal registers or configuration memory into a parameter data packet according to a predefined data format.

[0040] The hardware parameters of a data flow processor contain a wealth of structural information, with the number of compute cores and dedicated memory configuration being key parameters. Compute cores, as the execution units for data flow processing, directly determine the system's parallel processing capabilities. The topology and interconnection structure of each compute core are described in the core architecture field within the parameters, which includes information such as the core type identifier, instruction set architecture (ISA) version number, and the number of pipeline stages. Dedicated memory configuration parameters detail the storage resources of each compute core, including key metrics such as static random access memory (SRAM) and level 2 cache (L2Cache) capacity, bit width, and access latency. As the core carrier for near-memory computing, SRAM parameters directly influence data locality optimization strategies. L2 cache configuration parameters affect the performance balance of multi-level storage systems, and the driver must initialize and configure the cache coherence protocol based on these parameters.

[0041] During the parameter parsing phase, the kernel driver adheres to a strict validation and conversion mechanism. First, a CRC check is performed on the received parameter data packet to ensure data integrity. Subsequently, the data packet is decapsulated according to the parameter format definition, converting the binary data into a structured parameter object. For key parameters such as the number of compute cores and dedicated memory size, the driver performs bounds checks to verify compliance with hardware design specifications and system resource constraints. The parsed parameter information is stored in the system's Device Descriptor Table (DDT) for access by the operating system's resource management modules (such as the task scheduler and memory allocator). Furthermore, the driver must establish a parameter change monitoring mechanism to monitor dynamic hardware parameter changes in real time, enabling timely adjustments to system configuration policies during device operation to optimize performance and achieve efficient resource utilization.

[0042] In an embodiment of the present invention, based on step S3, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0043] In heterogeneous computing systems, precise allocation of DDR memory regions is crucial for balancing resource utilization between PCIe devices and the computing core. Step S3 optimizes the DDR memory region by integrating the global memory requirements of PCIe devices with the local storage characteristics of the computing core. This process involves multi-level address mapping strategies and dynamic resource allocation algorithms, balancing hardware architecture constraints with system performance objectives.

[0044] First, the system needs to establish a memory demand model to quantify the DDR allocation benchmark. The total memory size of a PCIe device includes components such as device register space, DMA buffers, and data processing space. The size of the dedicated memory for the compute core reflects the near-memory computing capability, including SRAM for data temporary storage and L2 cache for fast access. DDR allocation must meet the following formula: Total DDR demand = max(PCIe device peak bandwidth × processing latency, number of concurrent compute core tasks × single-task data volume) - ∑(dedicated memory capacity for each compute core). This formula ensures that the DDR capacity can cover the device's bursty data transmission needs while also compensating for insufficient local storage capacity.

[0045] Secondly, DDR region division follows a hierarchical address mapping strategy. The system divides the DDR space into a fixed region and a flexible region. The fixed region maps the base address space of PCIe devices, establishing a 1:1 physical address mapping through the IOMMU (Input / Output Memory Management Unit). The flexible region uses a dynamic page table mechanism to dynamically adjust page allocation based on the compute core load. For example, when the GPU core performs high-throughput calculations, the flexible region can allocate more large pages (such as 2MB / 1GB pages) to reduce the TLB (Translation Look-aside Buffer) miss rate.

[0046] In an embodiment of the present invention, based on step S4, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0047] S401. Instantiate a static container for the dedicated memory configured for each computing core.

[0048] For each compute core's dedicated memory area, a static container is instantiated. This container manages a memory mapping of fixed size and relatively stable location.

[0049] Static containers contain two core parameters: Compute core base address: The starting address of the PCIe bus address space allocated for the dedicated memory area of ​​the compute core during instantiation.

[0050] Space size: the size of the dedicated memory of the computing core itself obtained in step S2.

[0051] S402. Instantiate a dynamic container for the DDR memory area.

[0052] A dynamic container is instantiated for the external DDR memory area used to store the input / output data of computing tasks. This container manages task data blocks that are variable in size and may change location frequently.

[0053] Dynamic containers manage a variable number of memory blocks (Chunks), each of which represents a continuous task data storage area.

[0054] Each memory block is described by two core parameters: Memory block base address: The starting address of the task data block in the PCIe bus address space.

[0055] Space size: the length of the task data block.

[0056] The dynamic container determines the number of memory blocks to allocate and manage based on the size of the data to be processed by the current computing task. During instantiation, it divides the total memory space required for the task data into one or more appropriately sized blocks and records the base address and size of each block.

[0057] In an embodiment of the present invention, based on step S5, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0058] In the PCIe system architecture, the Base Address Register (BAR)-based address space mapping mechanism is a core technology for achieving memory resource isolation and efficient access. Mapping static and dynamic containers to different BAR spaces is a key step in building a hierarchical memory access model through the coordinated configuration of hardware address decoding and software drivers. This process involves the PCIe configuration space protocol, address translation mechanisms, and dynamic management strategies for system resources.

[0059] The configuration space of a PCIe device consists of multiple BAR registers. Each BAR corresponds to an independent address space window, used to map the memory or I / O resources required by the device. When executing S501 and S502, the system must first follow the standard BAR initialization process specified in the PCIe specification. BAR register initialization is performed through the Configuration Access Mechanism (CAM), which defines two configuration cycles: Type 0 and Type 1, for accessing the configuration space of functional devices and bridge devices, respectively.

[0060] S501. Map a static container to the first BAR space of a PCIe device.

[0061] First, the driver reads the static container's metadata to obtain its base address and space size. It then writes a specific probing value to the PCIe device's first BAR register to identify the address space type (memory or I / O) supported by the BAR and its maximum capacity. Based on the probing results, the system aligns the static container's physical address range with the BAR's address space. This alignment must meet the PCIe specification's address boundary requirements, typically 128 bytes, to ensure efficient data transfer. After address mapping is complete, the driver establishes a mapping between the static container and the first BAR space in the system's Device Address Mapping Table (DAT). It also configures the IOMMU (Input / Output Memory Management Unit) to translate virtual addresses to physical addresses, ensuring secure and transparent memory access.

[0062] S502: Map the dynamic container to the second BAR space of the PCIe device.

[0063] Because the memory blocks managed by dynamic containers are variable in size and frequently relocate, the system requires a flexible address allocation strategy. Before mapping, the driver must calculate the total address space required based on the number and size of memory blocks currently managed by the dynamic container. To accommodate the scalability requirements of dynamic memory, the system typically reserves a certain amount of address space margin. During the BAR initialization phase, in addition to performing similar detection operations as for static containers, the BAR's prefetchable property must be configured to optimize data transfer performance. For mapping dynamic memory blocks, the system uses a segmented mapping strategy, allocating each memory block to a contiguous address segment within the second BAR space. Address binding is achieved by updating the memory block's base address metadata. Furthermore, the system must establish a dynamic memory mapping table to record the correspondence between each memory block and the BAR space address in real time, enabling rapid updates to mapping information when memory blocks are dynamically adjusted.

[0064] The BAR space isolation design of the two containers enables logical partitioning of memory resources, significantly improving system security and performance. From a security perspective, the isolation of physical address windows prevents illegal access between different types of memory areas. Combined with the IOMMU's access control mechanism, it effectively prevents memory out-of-bounds attacks. From a performance perspective, the fixed mapping of static containers reduces address translation overhead and supports low-latency access to computing cores. The flexible mapping of dynamic containers adapts to the dynamic changes of task data and improves the data transmission efficiency of the PCIe bus through prefetch optimization and address continuation processing.

[0065] In one embodiment, the operation strategy of the dynamic container is also defined: During the execution of computing tasks, dynamic containers adopt a prefetching strategy.

[0066] The strategy is based on the analysis of the task queue and predicts the data blocks that may need to be accessed in the next computing phase.

[0067] After the prediction is completed, the dynamic container establishes the physical address mapping of these predicted data blocks in advance (for example, preloading the corresponding Scatter-Gather List entries into the device DMA engine).

[0068] This prefetch operation is designed to reduce the delay caused by waiting for the data block address mapping to be established (mapping switching delay), thereby improving data throughput and task execution efficiency.

[0069] In some embodiments, the PCIe BAR space mapping system of the data stream processor may include a plurality of functional modules composed of computer program segments. The computer program of each program segment in the PCIe BAR space mapping system of the data stream processor may be stored in a memory of a computer device and executed by at least one processor to perform (see Figure 1 Description) PCIe BAR space mapping function of the data flow processor.

[0070] In this embodiment, the PCIe BAR space mapping system of the data stream processor can be divided into multiple functional modules according to the functions it performs, such as Figure 2 As shown. The module referred to in the present invention refers to a series of computer program segments that can be executed by at least one processor and can perform fixed functions, which are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0071] A first acquisition module is configured to read configuration space information of a PCIe device and determine a total size of memory space required by a data stream processor based on the configuration space information; The second acquisition module is used to obtain the dedicated memory size of each computing core; A memory calculation module, configured to determine the size of a DDR memory area used for task calculation based on the total size of the memory space and the size of the dedicated memory; A container construction module, configured to instantiate a static container for the dedicated memory of each computing core and a dynamic container for the DDR memory area; The space mapping module is used to allocate different BAR spaces to static containers and dynamic containers.

[0072] Figure 3The PCIe BAR space mapping method for the data stream processor provided in the embodiment of the present application can be applied to a device. Those skilled in the art will understand that the device structure involved in the embodiment of the present invention does not constitute a limitation of the device, and the device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. In the embodiment of the present invention, the device includes but is not limited to a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of the present application described and / or required herein.

[0073] The device 300 may include a processor 310, a memory 320, and a communication unit 330. These components communicate via one or more buses. Those skilled in the art will appreciate that the server structure shown in the figure does not limit the present invention. The server structure may be a bus structure or a star structure, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0074] The memory 320 can be used to store execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the device 300 can perform some or all of the steps in the above-described method embodiments.

[0075] The processor 310 is the control center of the storage device, which uses various interfaces and lines to connect various parts of the entire electronic device. It executes various functions of the electronic device and / or processes data by running or executing software programs and / or modules stored in the memory 320, and calling data stored in the memory. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs with the same or different functions. For example, the processor 310 can only include a central processing unit (CPU). In an embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0076] The communication unit 330 is configured to establish a communication channel so that the storage device can communicate with other devices, receive user data sent by other devices, or send user data to other devices.

[0077] The present invention also provides a computer medium, wherein the computer medium may store a program that, when executed, may include some or all of the steps of each embodiment provided by the present invention. The medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0078] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software and a necessary general-purpose hardware platform. Based on this understanding, the technical solutions in the embodiments of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a medium such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, among other media capable of storing program code, and includes instructions for causing a computer device (which can be a personal computer, a server, or a second device, a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention.

[0079] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0080] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or modules, and can be electrical, mechanical or other forms.

[0081] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of the present embodiment according to actual needs.

[0082] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0083] Although the present invention has been described in detail with reference to the accompanying drawings and in conjunction with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, persons of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and such modifications or substitutions shall be within the scope of the present invention. Any changes or substitutions that can be easily conceived by persons skilled in the art within the technical scope disclosed in the present invention shall be within the scope of protection of the present invention.

Claims

1. A PCIe BAR space mapping method for a data stream processor, characterized in that: include: Read the configuration space information of the PCIe device, and determine the total size of the memory space required by the data stream processor based on the configuration space information; Get the dedicated memory size of each computing core; Determining the size of the DDR memory area used for task calculation according to the total size of the memory space and the size of the dedicated memory; Instantiate a static container for the dedicated memory of each computing core, and instantiate a dynamic container for the DDR memory area; Allocate different BAR spaces for static containers and dynamic containers.

2. The method according to claim 1, characterized in that Reading configuration space information of the PCIe device and determining the total size of the memory space required by the data stream processor based on the configuration space information includes: During the PCIe device enumeration phase, the required memory size is obtained by accessing the configuration space of the PCIe device; Sum up the memory space required by all PCIe devices to obtain the total memory space.

3. The method according to claim 2, characterized in that After determining the total size of the memory space required by the data stream processor based on the configuration space information, the method further includes: If it is confirmed that the total size of the memory space exceeds the set threshold, a dual-mode address mapping mechanism is enabled, where the dual-mode address mapping mechanism is used to map the dedicated memory and DDR memory areas of the computing core to different BAR spaces respectively.

4. The method according to claim 1, wherein Get the dedicated memory size of each computing core, including: Read the hardware parameters of the data stream processor through the kernel driver interface; The number of various computing cores and the size of the dedicated memory equipped for each computing core are analyzed based on the hardware parameters.

5. The method according to claim 1, wherein The core parameters of a static container include: The compute core base address is the starting address of the PCIe bus address space allocated for the dedicated memory area of ​​the compute core during instantiation. Computes the size of the core's own private memory.

6. The method according to claim 1, wherein The dynamic container manages a set of variable number of memory blocks, each block representing a continuous task data storage area; The core parameters of the memory block include: The memory block base address is used to indicate the starting address of the task data block in the PCIe bus address space; The space size is used to indicate the length of the task data block.

7. The method according to claim 1, characterized in that The method further comprises: During the execution of computing tasks, the dynamic container adopts a prefetching strategy, which includes: Based on the analysis of the task queue, predict the data blocks that need to be accessed in the next computing phase; The dynamic container establishes the physical address mapping of these predicted data blocks in advance.

8. A PCIe BAR space mapping system for a data stream processor, characterized in that: include: A first acquisition module is configured to read configuration space information of a PCIe device and determine a total size of memory space required by a data stream processor based on the configuration space information; The second acquisition module is used to obtain the dedicated memory size of each computing core; A memory calculation module, configured to determine the size of a DDR memory area used for task calculation based on the total size of the memory space and the size of the dedicated memory; A container construction module, configured to instantiate a static container for the dedicated memory of each computing core and a dynamic container for the DDR memory area; The space mapping module is used to allocate different BAR spaces to static containers and dynamic containers.

9. A PCIe BAR space mapping device for a data stream processor, characterized in that: include: A memory for storing a PCIe BAR space mapping program of a data stream processor; A processor, configured to implement the steps of the PCIe BAR space mapping method of the data stream processor according to any one of claims 1 to 7 when executing the PCIe BAR space mapping program of the data stream processor.

10. A computer-readable medium storing a computer program, characterized in that: The readable medium stores a PCIe BAR space mapping program of a data stream processor, and when the PCIe BAR space mapping program of the data stream processor is executed by a processor, the steps of the PCIe BAR space mapping method of the data stream processor according to any one of claims 1 to 7 are implemented.

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