Random verification method based on register array, electronic equipment and medium

Abstract

The invention relates to the technical field of chip verification, in particular to a random verification method based on a register array, electronic equipment and a medium, S1, setting m = 1, and executing S2; s2, inputting the same random test excitation to the RAm and the RBm in the target register array; s3, predicting a random write-in value by the RAm, and updating the Fm into the random write-in value predicted by the RAm; s4, the RBm writes a random number based on the input random test excitation; s5, reading data currently stored in RTL instances of all registers in the design of the chip to be tested out of order, comparing the data with a current corresponding reference value, if all the data are the same, executing S6, otherwise, determining that verification fails, and ending the process; s6, comparing m with M, if mlt; if m is equal to M, setting m to be equal to m + 1, returning to execute S2, and if m is equal to M, ending random verification of the target register array. According to the invention, random verification of the register array can be realized.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a random verification method based on a register array, electronic equipment and a medium. Background Art

[0002] Currently, chip verification requires the use of Universal Verification Methodology (UVM). A UVM RAL (Universal Verification Methodology) register model is generated within the verification environment, and the hardware register model in the device under test (DUT) is verified using the UVM RAL register model. In graphics processing unit (GPU) systems, a single address is often mapped to multiple registers. Multiple registers corresponding to a single address form a register array, and GPU systems need to use the same address to access multiple different register entities within the register array. However, existing register addressing methods are address-based, with a one-to-one correspondence between addresses and registers. Furthermore, in the UVM RAL, only one register entity exists for the same address. Therefore, the existing UVM RAL can only perform random verification of a single register, and cannot implement random verification of register arrays. Therefore, implementing random verification of register arrays has become a pressing issue. Summary of the Invention

[0003] The present invention aims to provide a random verification method, electronic device and medium based on a register array, which can realize random verification involving a register array.

[0004] According to a first aspect of the present invention, a random verification method based on a register array is provided, comprising: Step S1, initially set m=1, and execute step S2; Step S2: Add the UVM RAL model instance RA corresponding to the mth register in the target register array m and RTL instance RB m Input the same random test stimulus; Step S3, RA m Based on the random test stimulus input, the random write value is predicted and {F1,F2,...,F m ,...,F M F in m Updated to RA m Predicted random write values, {F1,F2,...,F m ,...,FM} is the RA stored in the preset cache area m The corresponding reference value sequence, F m is the reference value stored in RA m in; Step S4, RB m Write a random number based on the input random test stimulus; Step S5, Read the data currently stored in the RTL instances of all registers in the chip design to be tested in a scrambled order and compare it with the current corresponding reference value. If all are the same, execute Step S6; otherwise, the verification fails and the process ends; Step S6, Compare m and M. If m < M, set m = m + 1 and return to execute Step S2. If m = M, end the random verification of the target register array.

[0005] According to a second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present invention.

[0006] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for executing the method according to the first aspect of the present invention.

[0007] The present invention has obvious advantages and beneficial effects compared with the prior art. By means of the above technical solutions, a random verification method, an electronic device, and a medium based on a register array provided by the present invention can achieve considerable technical progressiveness and practicality, and have wide industrial utilization value. It has at least the following beneficial effects: In the embodiment of the present invention, the reference values of the register array are pre-stored in the preset cache area and updated in real time to ensure that the reference values of the register array are accurate and easy to obtain, realizing the random verification including the register array. In addition, when a complete random write operation is performed on each register in the register array, the data currently stored in the RTL instances of all registers in the chip design to be tested is read in a scrambled order and compared with the current corresponding reference value, which can improve the efficiency and accuracy of debugging. Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 A flow chart of a random verification method based on a register array provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The embodiment of the present invention provides a random verification method based on a register array, such as Figure 1 Shown, including: Step S1: Initially set m=1, and proceed to step S2.

[0012] It should be noted that the register array includes M registers, m is the register number in the register array, and M is the total number of registers in the register array.

[0013] Step S2: Add the UVM RAL model instance RA corresponding to the mth register in the target register array m and RTL (Register Transfer Level) instance RB m Enter the same random test stimulus.

[0014] It should be noted that each register in the chip design under test has a corresponding UVM RAL model instance and RTL instance. m and RB m One-to-one correspondence. Typically, the verification code drives the UVM RAL model to predict random write values ​​based on the corresponding addresses and attributes. The UVM RAL model then inputs the same random test stimulus to the RTL instance based on the verification component, and performs random write operations in the RTL instance. The chip design under test can specifically be a GPU chip design.

[0015] Step S3, RA m Based on the random test stimulus input, the random write value is predicted and {F1,F2,...,F m ,...,F M F in m Updated to RA m Predicted random write values, {F1,F2,...,F m ,...,F M} is the RA stored in the preset cache area m The corresponding reference value sequence, F m For RAm Reference value stored in .

[0016] It should be noted that the UVM RAL model is a standard value. If the value written in the RTL example is consistent with the standard value in the UVM RAL model, it is correct. Otherwise, the verification fails. Since the register array only corresponds to one register address, it is impossible to directly obtain the reference value of each register in the register array UVM RAL model. Based on this, the present invention sets the reference value {F1, F2, ..., F m ,...,F M} and updated in real time to ensure the accuracy of the reference values ​​stored in the preset cache area and facilitate their acquisition.

[0017] Step S4, RB m Random test based on input stimulus writes random numbers.

[0018] Step S5: read the currently stored data in the RTL instance of all registers in the chip design under test out of order and compare them with the current corresponding reference values. If all are the same, execute step S6; otherwise, the verification fails and the process ends.

[0019] It should be noted that, under normal circumstances, RB m RA should be written in m The predicted random write value, but the actual situation may be abnormal, resulting in RB m The value written in is not equal to RA m Predicted random write value, RA may also occur m Predicted random write value incorrectly written to non-RB m The corresponding address may also appear in the RA m Predicted random write value written to RB m At the same time, RA m The predicted random write value is written to other addresses. Therefore, in order to ensure accuracy, in step S5, it is necessary to read the currently stored data in the RTL instance of all registers and compare them with the currently corresponding reference values.

[0020] In addition, in step S5, each time the currently stored data in the RTL instance of a register is randomly read, it is compared with the current corresponding reference value. If they are different, the verification fails; otherwise, the currently stored data in the RTL instance of the next register is randomly read until the currently stored data in the RTL instances of all registers in the to-be-tested chip design is read and compared with the current corresponding reference value. It should be noted that in the prior art, the currently stored data in the RTL instances of all registers in the to-be-tested chip design is read in sequence and compared with the current corresponding reference value. However, in some application scenarios, the emergence of some problems has a window period. For example, in one application scenario, problems are exposed within 5 cycles after writing to the register, and the problems may be restored by other read / write operations after 5 cycles. Therefore, if the problem location can only be read after 5 cycles, the problem point cannot be verified. In addition, if the problem point is in a later position, sequential reading will consume a large amount of time. For the above reasons, the present invention adopts out-of-order reading, that is, randomly reads the currently stored data in the RTL instances of all registers in the to-be-tested chip design and compares it with the current corresponding reference value, which can improve the efficiency and accuracy of debugging.

[0021] Step S6: Compare m and M. If m < M, set m = m + 1 and return to execute step S2. If m = M, end the random verification of the target register array.

[0022] In the to-be-tested chip design, in addition to the register group, there is also a situation of a single register. For the random verification of the single register type and the register group type, different methods are required. As an embodiment, the method further includes: Step S10: Initially set n = 1, and use R n ,..., R N} in the register instance set {R1, R2,..., R n} corresponding to the to-be-tested chip design as the target register instance, and execute step S20, where R n is the nth register instance corresponding to the to-be-tested chip design, the value range of n is from 1 to N, N is the total number of register instances corresponding to the to-be-tested chip design, and the type of R n is a single register or a register array.

[0023] It should be noted that R n may be a single register or a register array composed of multiple registers.

[0024] Step S20: If the type of R n is a single register, execute step S30. If the type of R n is a register array, then R nAs the target register array, execute step S1 - step S6, and then execute step S70.

[0025] Step S30: Input the same random test stimuli to the UVM RAL model instance RC n corresponding to R n and the RTL instance RD n

[0026] It should be noted that for each register in the chip design under test, there is a corresponding UVM RAL model instance and RTL instance, and RC n and RD n correspond one by one. Usually, the verification code drives the UVM RAL model to predict the random write value based on the corresponding address and attributes. The UVM RAL model inputs the same random test stimuli to the RTL instance based on the verification component, and performs random write operations in the RTL instance.

[0027] Step S40: RC n predicts the random write value based on the input random test stimuli, and updates the predicted random write value to RC n

[0028] It should be noted that the RC n corresponding to the R of a single register type n can be directly accessed based on the address. Therefore, for the R n of a single register type, directly update the predicted random write value to RC n as the reference value.

[0029] Step S50: RD n writes a random number based on the input random test stimuli.

[0030] Step S60: Randomly read the data currently stored in the RTL instances of all registers in the chip design under test and compare it with the current corresponding reference value. If all are the same, execute step S70; otherwise, the verification fails and the process ends.

[0031] Among them, for each randomly read data currently stored in the RTL instance of a register, compare it with the current corresponding reference value. If they are different, the verification fails; otherwise, randomly read the data currently stored in the RTL instance of the next register until all the data currently stored in the RTL instances of all registers in the chip design under test have been read and compared with the current corresponding reference values.

[0032] Step S70: Compare n and N. If n < N, set n = n + 1 and return to execute step S20. If n = N, the verification passes and the process ends. ​​

[0033] For register arrays, there is a special copy operation that copies the data in one register in the register array to another array in the register group. This operation can be effective for all register arrays in the chip under test design, achieving efficient batch operations. For such application scenarios, the embodiment of the present invention also provides a corresponding random testing method. As an embodiment, the step S6 further includes: Step S100: Obtain a register array copy instruction, the register array copy instruction being effective for all register arrays, and the register array copy instruction including a first register serial number and a second register serial number.

[0034] The first register number is the register number corresponding to the source address, and the second register number is the register number corresponding to the target address. The data stored in the source address in each register array needs to be copied to the target address.

[0035] Step S200: All register arrays corresponding to {F1, F2, ..., F m ,...,F M}, the second register number corresponds to F m The value of the first register number is updated to the corresponding F m value.

[0036] It should be noted that step S200 can quickly and accurately update {F1, F2, ..., F m ,...,F M}.

[0037] Step S300: writing the value of the register RTL instance corresponding to the first register number in the RTL instances of all register arrays in the chip design to be tested into the register RTL instance corresponding to the second register number; Step S400: read the currently stored data in the RTL instances of all registers in the chip design under test out of order and compare them with the currently corresponding reference values. If all are the same, the register data copy verification passes; otherwise, the register data copy verification fails.

[0038] Among them, each time the data currently stored in the RTL instance of a register is randomly read, it is compared with the current corresponding reference value. If they are different, the verification fails. Otherwise, the data currently stored in the RTL instance of the next register is randomly read until the data currently stored in the RTL instances of all registers in the chip design to be tested are read and compared with the current corresponding reference value.

[0039] It should be noted that, under normal circumstances, the register array copy instruction should write the value of the register RTL instance corresponding to the first register number in the RTL instance of all register arrays in the chip design to be tested into the register RTL instance corresponding to the second register number. However, during the actual execution process, there may be anomalies. For example, it may happen that when writing the value of the register RTL instance corresponding to the first register number into the register RTL instance corresponding to the second register number, an error occurs in the written value. It may also happen that the value of the register RTL instance corresponding to the first register number is written into the register RTL instance that does not correspond to the second register number. It may also happen that while writing the value of the register RTL instance corresponding to the first register number into the register RTL instance corresponding to the second register number, the value of the register RTL instance corresponding to the first register number is also written into the register RTL instance that does not correspond to the second register number. Therefore, in order to ensure accuracy, in step S400, it is necessary to read the currently stored data in the RTL instances of all registers and compare them with the currently corresponding reference values.

[0040] As an embodiment, in step S5, step S60, and step S400, the out-of-order reading of the RTL instance of all registers in the chip design under test and comparing the currently stored data with the currently corresponding reference values ​​include: Step S51, randomly reading the data currently stored in the RTL instance of the register in the chip design under test. If the RTL instance of the register currently read is an RTL instance of a register of type single register, then executing step S52; if the RTL instance of the register currently read is an RTL instance of a register in a register array, then executing step S53; Step S52: Obtain data stored in the UVM RAL model instance corresponding to the currently read register as a reference value and compare it with the data currently stored in the RTL instance of the register.

[0041] Step S53, obtain the UVM RAL model instance corresponding to the currently read register in {F1, F2, ..., F m ,...,F M} is compared with the data currently stored in the RTL instance of the register.

[0042] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0043] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0044] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0045] This embodiment of the present invention pre-stores the reference values ​​of the register array in a preset cache area and updates them in real time, ensuring that the reference values ​​of the register array are accurate and easily accessible, thus achieving random verification of the register array. Furthermore, when each register in the register array is fully randomly written, the currently stored data in the RTL instance of all registers in the chip design under test is read out of order and compared with the corresponding reference values, which can improve the efficiency and accuracy of debugging.

[0046] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A random verification method based on a register array, comprising: Step S1, initially set m = 1, and execute Step S2; Step S2: Add the UVM RAL model instance RA corresponding to the mth register in the target register array m and RTL instance RB m Input the same random test stimulus; Step S3, RA m Based on the random test stimulus input, the random write value is predicted and {F1,F2,...,F m ,...,F M F in m Updated to RA m Predicted random write values, {F1,F2,...,F m ,...,F M } is the RA stored in the preset cache area m The corresponding reference value sequence, F m For RA m Reference values ​​stored in ; Step S4, RB m Random test based on input stimulus writes random numbers; Step S5, randomly read the currently stored data in the RTL instances of all registers in the chip design to be tested and compare it with the corresponding reference value at present. If all are the same, execute Step S6; otherwise, the verification fails and the process ends; Step S6, compare m and M. If m < M, set m = m + 1 and return to execute Step S2. If m = M, end the random verification of the target register array.

2. The method according to claim 1, wherein the method further comprises: Step S10: Initially set n=1, and design the register instance set {R1, R2, ..., R n ,...,R N R in n As a target register example, step S20 is executed, wherein R n is the nth register instance corresponding to the chip under test design, the value range of n is 1 to N, N is the total number of register instances corresponding to the chip under test design, R n The corresponding type is a single register or a register array; Step S20: If R n The corresponding type is a single register, then execute step S30. If R n The corresponding type is a register array, then R n As the target register array, execute steps S1 to S6, and then execute step S70; Step S30, to R n Corresponding UVM RAL model instance RC n and RTL instance RD n Input the same random test stimulus; Step S40, RC n Predict random write values ​​based on input random test stimulus, and update the predicted random write values ​​to RC n middle; Step S50, RD n Random test based on input stimulus writes random numbers; Step S60, randomly read the currently stored data in the RTL instances of all registers in the chip design to be tested and compare it with the corresponding reference value at present. If all are the same, execute Step S70; otherwise, the verification fails and the process ends; Step S70, compare n and N. If n < N, set n = n + 1 and return to execute Step S20. If n = N, the verification passes and the process ends.

3. The method according to claim 2, wherein after Step S6, it further comprises: Step S100, obtain a register array copy instruction, which takes effect on all register arrays. The register array copy instruction includes a first register number and a second register number; Step S200: All register arrays corresponding to {F1, F2, ..., F m ,...,F M }, the second register number corresponds to F m The value of the first register number is updated to the F corresponding to the m The value of Step S300, write the value in the register RTL instance corresponding to the first register number in the RTL instances of all register arrays in the chip design to be tested into the register RTL instance corresponding to the second register number; Step S400, randomly read the currently stored data in the RTL instances of all registers in the chip design to be tested and compare it with the corresponding reference value at present. If all are the same, the register data copy verification passes; otherwise, the register data copy verification fails.

4. The method according to claim 3, wherein in Step S5, Step S60, and Step S400, every time the currently stored data in the RTL instance of a randomly read register is compared with the corresponding reference value at present. If they are different, the verification fails; otherwise, randomly read the currently stored data in the RTL instance of the next register until the currently stored data in the RTL instances of all registers in the chip design to be tested is read and compared with the corresponding reference value at present.

5. The method according to claim 1, wherein in Step S5, Step S60, and Step S400, the randomly reading the currently stored data in the RTL instances of all registers in the chip design to be tested and comparing it with the corresponding reference value at present includes: Step S51, randomly read the currently stored data in the RTL instance of a register in the chip design to be tested. If the currently read register RTL instance is a register RTL instance of a single register type, execute Step S52; if the currently read register RTL instance is a register RTL instance in a register array, execute Step S53; Step S52: obtaining the data stored in the UVM RAL model instance corresponding to the currently read register as a reference value and comparing it with the data currently stored in the RTL instance of the register; Step S53, obtain the UVM RAL model instance corresponding to the currently read register in {F1, F2, ..., F m ,...,F M } is compared with the data currently stored in the RTL instance of the register.

6. The method according to claim 1, characterized in that The chip design to be tested is a GPU chip design.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 6.

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