A computing circuit and a computing method for integer frequency pulse signal steps

Abstract

The application relates to the field of processor internal structure design, and discloses a calculation circuit and a calculation method for integer frequency pulse signal steps, which comprise a user configuration module, a NAND gate, a delay unit, a system counter, a comparator, a latch, a step counter, an inverter, a AND gate 1, a AND gate 2, a step latch L1, a step latch L2, a step calculation module and a user reading module; different delay series N are configured to generate step clock with different frequencies for the step counter to count; when the system counter count value is equal to the period register period value, the step counter count value is latched to the step latch to calculate the step, and the problem that the step generates errors due to temperature and voltage changes is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor internal structure design, in particular to a calculation circuit and method for step length of integer frequency pulse signal. BACKGROUND

[0002] In a power electronic device system, an integer frequency pulse signal is often needed, and the circuit of the integer frequency pulse signal needs a delay unit to work. The delay time of the delay unit is not dependent on a clock, but only related to a process. After the delay time of the delay unit is calculated, the step length is obtained, and the step length is the number of delay modules B contained in a system clock cycle. Therefore, the conventional method for calculating the step length is , T is the system clock cycle, and M is the delay time of the delay module B. After the step length S is calculated, it is rounded to an integer, and the final step length is obtained. Therefore, the premise of the existing step length calculation is to know the value of the system clock cycle T and the value of the delay time M of the delay module B.

[0003] However, during the working process of the chip, the values of the system clock cycle T and the delay time M of the delay module B change after the temperature and voltage change. The specific values of the system clock cycle T and the delay time M of the delay module B cannot be accurately known under the current temperature and voltage, which causes the step length calculation to be biased, and thus the frequency of the integer frequency pulse signal is no longer an integer frequency. SUMMARY

[0004] To solve the above technical problems, the present application provides a calculation circuit and method for step length of integer frequency pulse signal, so as to calculate the step length without obtaining the value of the system clock cycle T and the value of the delay time M of the delay module B, and solve the problem of step length error caused by temperature and voltage change.

[0005] To achieve the above purpose, the technical scheme of the present application is as follows:

[0006] A calculation circuit for step length of integer frequency pulse signal, comprising a user configuration module, a NAND gate, a delay unit, a system counter, a comparator, a latch, a step length counter, an inverter, a AND gate 1, a AND gate 2, a step length latch L1, a step length latch L2, a step length calculation module and a user reading module.

[0007] The user configuration module is used for user to configure the period value of the period register, the working enable, the delay stage number N, the step length latch L1 enable, the step length latch L2 enable and the step length calculation enable.

[0008] The NAND gate is used for generating a clock signal to the delay unit according to the working enable configured by the user and the step length clock returned by the delay unit.

[0009] The delay unit is configured to generate a step clock according to a user-configured delay stage number N and a clock signal output by the NAND gate, and send the step clock to the step counter while feeding back to the NAND gate input;

[0010] The system counter is configured to count according to a system clock and a count enable, generate a count value, and send the count value to the comparator;

[0011] The comparator is configured to compare the count value of the system counter and a period value of a user-configured period register to generate a trigger signal, the trigger signal is valid when the two values are equal, and send the trigger signal to the latch, the AND gate 1, and the AND gate 2;

[0012] The latch is configured to open the count enable according to a user-configured work enable, close the count enable when the trigger signal is valid, and send the count enable to the system counter, the step counter, and the user reading module;

[0013] The step counter is configured to count according to the step clock generated by the delay unit and the count enable, and generate a count value;

[0014] The inverter is configured to take the user-configured work enable as an inverse value to control the system counter and the step counter to clear;

[0015] The AND gate 1 is configured to generate a latch enable 1 for the step latch L1 according to the trigger signal and a user-configured step latch L1 enable;

[0016] The AND gate 2 is configured to generate a latch enable 2 for the step latch L2 according to the trigger signal and a user-configured step latch L2 enable;

[0017] The step latch L1 and the step latch L2 are configured to latch the count values of the step counter under two different frequency step clocks according to the latch enable 1 and the latch enable 2;

[0018] The step calculation module is configured to calculate a step according to the count values of the step counter latched by the step latch L1 and the step latch L2 under a user-configured step calculation enable control, and send the step to a step register of the user reading module;

[0019] The user reading module is configured to allow a user to read the count enable and the step value.

[0020] In the above scheme, the delay unit includes 256 delay modules B and a 256-to-1 selector in series;

[0021] The delay module B is configured to delay a clock signal, the input of the first delay module B is a clock signal output by the NAND gate, and the input of the i-th delay module B is Ai , output is Z i ; the output of each delay module B enters the next delay module B and 256-to-1 selector simultaneously;

[0022] The 256-to-1 selector is used to select the clock signal output of a certain delay module B according to the delay stage number N, i.e. to obtain the step clock, when the delay stage number N is x, the output Z x of the xth delay module B is selected as the output, i.e. the step clock is Z x .

[0023] A calculation method for the step of an integer frequency pulse signal, which adopts the calculation circuit for the step of an integer frequency pulse signal as described above, comprises the following steps:

[0024] Step one, configure the user configuration module:

[0025] Turn off the working enable, the system counter and the step counter are automatically cleared, and the step clock is turned off; configure the period register period value; configure the delay stage number N for the first time; turn on the step latch L1 enable, turn off the step latch L2 enable and the step calculation enable;

[0026] Step two, configure the user configuration module:

[0027] Turn on the working enable, the step clock is generated by the NAND gate and the delay unit, the latch turns on the counting enable, and the system counter and the step counter start the first counting;

[0028] Step three, read the user reading module:

[0029] Cyclically read the counting enable, when the system counter counting value is equal to the period register period value, a trigger signal is generated, the latch turns off the counting enable, at this time the user reads the counting enable to be turned off, which represents that the first counting of the system counter and the step counter is completed, the trigger signal and the step latch L1 enable are both effective, the latch enable 1 is generated through the AND gate 1, and the step counter counting value is latched into the step latch L1;

[0030] Step four, configure the user configuration module:

[0031] Turn off the working enable, the system counter and the step counter are automatically cleared, the trigger signal is invalid, the delay counting N is configured for the second time, the stage value of which is different from the stage value of the delay stage number N configured for the first time, turn off the step latch L1 enable and turn on the step latch L2 enable;

[0032] Step five, configure the user configuration module:

[0033] The working enable is opened, the control NOR gate and the delay unit generate the step clock, the latch opens the count enable, the system counter and the step counter start the second counting;

[0034] Step six, reading the user reading module:

[0035] The cycle reading enable is looped, when the system counter value is equal to the cycle register cycle value, a trigger signal is generated, the latch closes the count enable, at this time, the user reads the count enable to be closed, representing that the second counting of the system counter and the step counter is completed, the trigger signal and the step latch L2 enable are both valid, the latch enable 2 is generated through the AND gate 2, and the step counter value is latched into the step latch L2;

[0036] Step seven, configuring the user configuration module:

[0037] The working enable is closed, the control NOR gate and the delay unit close the step clock, the system counter and the step counter are automatically cleared, and the step latch L2 enable is closed;

[0038] Step eight, configuring the user configuration module:

[0039] The step calculation enable is opened, the step calculation module starts to work, the step is calculated according to the step counter values latched in the step latch L1 and the step latch L2, and the step is input into the step register of the user reading module for the user to read.

[0040] In the scheme, the delay stage number N is configured to be less than the system clock frequency.

[0041] In the scheme, in step eight, the step calculation method is as follows:

[0042] Suppose that the cycle value of the cycle register is D, the delay stage number N is configured to have two different stage values C1 and C2, the latched value of the step latch L1 is V1, and the latched value of the step latch L2 is V2.

[0043] The step S calculation formula is as follows:

[0044] ;

[0045] After the step S is calculated, S is rounded to an integer value, that is, the final obtained step.

[0046] Through the technical scheme, the calculation circuit and the calculation method for the integer frequency pulse signal step provided by the application have the following beneficial effects:

[0047] The step size calculation circuit disclosed in this invention generates two step size clocks with different frequencies by configuring two different delay stages N, without requiring the user to know the system clock period and the delay time of the delay module B, and without changing the period value of the period register. After two working times of the same duration, the latch values ​​of step size latch L1 and step size latch L2 are obtained. The step size is automatically calculated by the step size calculation module, which solves the problem of step size error caused by temperature and voltage changes. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0049] Figure 1 This is a schematic diagram of a circuit for calculating the step size of an integer frequency pulse signal, as disclosed in an embodiment of the present invention.

[0050] Figure 2 This is a schematic diagram of the delay unit structure;

[0051] Figure 3 This is a schematic diagram of a step clock. Detailed Implementation

[0052] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0053] This invention provides a circuit for calculating the step size of integer frequency pulse signals, such as... Figure 1 As shown, the system includes a user configuration module, NAND gates, a delay unit, a system counter, a comparator, a latch, a step counter, an inverter, AND gate 1, AND gate 2, step latch L1, step latch L2, a step calculation module, and a user read module. The system counter operates based on the system clock, and the step counter operates based on the step clock. When the system counter's count value equals the period value of the period register, the step counter's count value is latched into the step latch for step calculation. Figure 1 Black dots indicate intersecting lines, while the absence of black dots indicates non-intersecting lines. The functions of each module are as follows:

[0054] 1. User Configuration Module

[0055] The user configuration module allows users to configure the period value of the period register, the working enable, the number of delay stages N, the enable of step latch L1, the enable of step latch L2, and the enable of step calculation; through the above configuration, the operation and number of times the entire circuit operates are controlled.

[0056] Period register is used to configure period value, which is compared with system counter count value. When system counter count value equals period register period value, comparator output trigger signal, count enable is closed, and step size latch L1 enable and step size latch L2 enable are enabled, and step size counter count value is latched to step size latch L1 and step size latch L2 respectively.

[0057] Work enable is used to generate step size clock with NAND gate and delay unit, and to generate count enable with control latch. When work enable is opened, first, step size clock is generated, and second, control latch opens count enable. When count enable is opened, system counter and step size counter start counting. When work enable is closed, first, step size clock is closed, and second, system counter and step size counter are cleared.

[0058] Delay stage N is used to control 256 to 1 selector in delay unit to output step size clock. Delay count N is configured as different stage values. 256 to 1 selector in delay unit selects output Z of different delay module B as step size clock. Frequency of step size clock is different. Note that frequency of step size clock must be less than frequency of system clock, so configuration of delay stage N has requirements.

[0059] Step size latch L1 enable and step size latch L2 enable are used to latch step size counter count value. When system counter count value equals period register period value for the first time, trigger signal is valid. At this time, step size latch L1 enable is opened. After passing through AND gate 1, latch enable 1 is valid, and step size counter count value is latched to step size latch L1. When system counter count value equals period register period value for the second time, trigger signal is valid again. At this time, step size latch L2 enable is opened. After passing through AND gate 2, latch enable 2 is valid, and step size counter count value is latched to step size latch L2.

[0060] Step size calculation enable is used for step size calculation. When step size latch L1 and step size latch L2 obtain latched values, step size calculation enable is opened, and step size calculation module automatically calculates step size.

[0061] 2, NAND gate

[0062] The NAND gate is used to generate the clock signal for the delay unit according to the user-configured work enable and the step clock returned by the delay unit. The output logic of the NAND gate is: when any one of the inputs is 0, the output of the NAND gate is 1, and when all the inputs are 1, the output of the NAND gate is 0. Therefore, when the work enable is off, one input of the NAND gate is 0, the output of the NAND gate is 1, and the input of the delay unit is 1, the step clock is always 1, and the step clock is off; when the work enable is on, one input of the NAND gate is 1, and at this time the NAND gate is logically equivalent to an inverter, so that the input A of the first delay module B in the delay unit is the inverted signal of the step clock, so that the step clock is a high-low changing pulse, and the step clock is on.

[0063] 3. The delay unit

[0064] The delay unit is used to generate the step clock according to the user-configured delay stage number N and the clock signal output by the NAND gate, and send it to the step counter, and feedback to the input of the NAND gate;

[0065] As shown in Figure 2 , the delay unit includes 256 delay modules B and a 256-to-1 selector in series;

[0066] The delay module B is used to delay the clock signal, the input of the first delay module B is the clock signal output by the NAND gate, and the input of the i-th delay module B is A i , and the output is Z i ; the output of each delay module B enters the next delay module B and the 256-to-1 selector at the same time; 256 delay modules B are connected in series, that is, the clock signal output of the previous delay module B is the clock signal input of the current delay module B, and the clock signal output of the current delay module B is the clock signal input of the next delay module B.

[0067] The 256-to-1 selector is used to select the clock signal output of a certain delay module B according to the delay stage number N, that is, to obtain the step clock. When the delay stage number N is x, the output Z x of the x-th delay module B is output, that is, the step clock is Z x . The relationship is as follows:

[0068] When N = 1, the step clock is the clock signal output of the first delay module B, representing that there is 1 delay module B participating in the delay calculation, that is, Z1;

[0069] When N = 2, the step clock is the clock signal output of the second delay module B, representing that there are 2 delay modules B participating in the delay calculation, that is, Z2;

[0070] When N=255, the step clock is the clock signal output of the 255th delay module B, representing that there are 255 delay modules B participating in the delay calculation, namely Z255;

[0071] When N=256, the step clock is the clock signal output of the 256th delay module B, representing that there are 256 delay modules B participating in the delay calculation, namely Z256.

[0072] When the work enable is turned on, the step clock output by the 256-to-1 selector and the work enable are input to the input of the 1st stage delay module B after being operated by the NAND gate.

[0073] If the period value of the step clock is P, the number of delay stages N is C, and the delay time of the delay module B is M, then the period value P of the step clock is calculated as follows:

[0074] (1);

[0075] The schematic diagram of the step clock is shown in Figure 3 ;

[0076] According to the description of the delay stage number N, the step clock frequency must be less than the system clock frequency. If the system clock frequency is 100Mhz and the period is 10ns, and the delay of the delay module B is 150ps, then the maximum step clock frequency is 100Mhz, and the minimum value of the number of delay stages N C can be calculated according to formula (1) as 34, that is, the minimum value of the number of delay stages N configured by the user is 34, and the maximum value is Figure 2 The number of all delay modules B in the delay unit in is 256. For safety, it is not recommended to configure the step clock frequency close to the system clock frequency, because as the temperature and voltage change, the delay time of the delay module B may change too much, which may cause the step clock frequency to be greater than the system clock frequency.

[0077] 4、System counter

[0078] The system counter is used to count according to the system clock and the count enable, generate a count value and send it to the comparator.

[0079] 5、Comparator

[0080] The comparator is used to compare the count value of the system counter and the period value of the period register configured by the user to generate a trigger signal, which is valid when the two are equal, and sends the trigger signal to the latch, AND gate 1 and AND gate 2; controls the latch to close the count enable, and at the same time enables the step latch L1 and the step latch L2, and after being operated by the AND gate 1 and the AND gate 2, generates the latch enable 1 and the latch enable 2.

[0081] 6、Latch

[0082] Latch is used to open count enable according to user configuration, and send to system counter, step counter and user read module; count enable is opened, which means that system counter and step counter are counting, when system counter value is equal to period register value, trigger signal is valid, latch will close count enable, which means that system counter and step counter counting is completed.

[0083] 7、Step counter

[0084] Step counter is used to count according to step clock generated by delay unit and count enable, and generate count value; period value of period register is always unchanged when system counter counts twice, so the time of trigger signal generation is fixed, when delay counter N configures two different stage values, step counter counts twice different count values which are respectively latched to step latch L1 and step latch L2.

[0085] 8、Inverter

[0086] Inverter is used to control system counter and step counter to clear zero after taking inverse of user configuration work enable; count and clear zero of system counter cannot occur at the same time, and count and clear zero of step counter also cannot occur at the same time, so work enable needs to be controlled to clear zero after taking inverse.

[0087] 9、AND gate 1

[0088] AND gate 1 is used to generate latch enable 1 for step latch L1 according to trigger signal and user configuration step latch L1 enable; the output logic of AND gate 1 is: when all inputs are 1, the output of AND gate 1 is 1, when any input is 0, the output of AND gate 1 is 0. So when step latch L1 enable is opened and trigger signal is valid, the output of AND gate 1 is 1, latch enable 1 is valid, and the count value of step counter is latched to step latch L1, when step latch L1 enable is closed or trigger signal is invalid, the output of AND gate 1 is 0, latch enable 1 is invalid, and the count value of step counter is prohibited to be latched to step latch L1.

[0089] 10、AND gate 2

[0090] AND gate 2 is used to generate latch enable 2 to step size latch L2 according to trigger signal and user configured step size latch enable L2; the output logic of AND gate 2 is: when all inputs are 1, the output of AND gate 2 is 1, when any one input is 0, the output of AND gate 2 is 0. So when step size latch enable L2 is opened and trigger signal is valid, the output of AND gate 2 is 1, latch enable 2 is valid, and the count value of step size counter is latched to step size latch L2, when step size latch enable L2 is closed or trigger signal is invalid, the output of AND gate 2 is 0, latch enable 2 is invalid, and the count value of step size counter is prohibited from being latched to step size latch L2.

[0091] 11. step size latch L1 and step size latch L2

[0092] Step size latch L1 and step size latch L2 are used to latch the count value of step size counter under different frequency step size clock respectively according to latch enable 1 and latch enable 2.

[0093] 12. step size calculation module

[0094] Step size calculation module is used to calculate step size according to the count value of step size counter latched by step size latch L1 and step size latch L2 under the control of user configured step size calculation enable, and send the step size to step size register of user reading module.

[0095] 13. user reading module

[0096] User reading module is used for user to read count enable and step size value.

[0097] Count enable is used to mark whether system counter and step size counter are working, when count enable is opened, it represents that system counter and step size counter are working, and the count value of system counter is less than the period value of period register, when count enable is closed, it represents that system counter and step size counter have completed work under the current frequency of step size clock, the count value of system counter is equal to the period value of period register, and the count value of step size counter is latched to step size latch L1 or step size latch L2.

[0098] Step size register is used to read step size value, and the step size value read by user is used to generate integer frequency pulse signal.

[0099] A method for calculating step size of integer frequency pulse signal, which adopts the above-mentioned circuit for calculating step size of integer frequency pulse signal, and comprises the following steps:

[0100] Step one, configure user configuration module:

[0101] Close the work enable, system counter and step counter are automatically cleared, step clock is closed; configure the period register period value; configure the delay stage N value for the first time; open the step latch Ll enable, close the step latch L2 enable and step calculation enable;

[0102] Step two, configure the user configuration module:

[0103] Open the work enable, control NAND gate and delay unit to generate step clock, latch open count enable, system counter and step counter start the first counting;

[0104] Step three, read the user read module:

[0105] Loop read count enable, when the system counter count value is equal to the period register period value, generate trigger signal, latch close count enable, at this time the user reads to count enable is closed, which represents that the system counter and step counter complete the first counting, trigger signal and step latch Ll enable are both valid, through AND gate 1, generate latch enable 1, which latches the step counter count value into step latch Ll;

[0106] Step four, configure the user configuration module:

[0107] Close the work enable, system counter and step counter are automatically cleared, trigger signal is invalid, configure the delay count N value for the second time, which is different from the delay stage N value configured for the first time, close the step latch Ll enable, open the step latch L2 enable;

[0108] Step five, configure the user configuration module:

[0109] Open the work enable, control NAND gate and delay unit to generate step clock, latch open count enable, system counter and step counter start the second counting;

[0110] Step six, read the user read module:

[0111] Loop read count enable, when the system counter count value is equal to the period register period value, generate trigger signal, latch close count enable, at this time the user reads to count enable is closed, which represents that the system counter and step counter complete the second counting, trigger signal and step latch L2 enable are both valid, through AND gate 2, generate latch enable 2, which latches the step counter count value into step latch L2;

[0112] Step seven, configure the user configuration module:

[0113] Close the work enable, control NAND gate and delay unit to close step clock, system counter and step counter are automatically cleared, close the step latch L2 enable;

[0114] Step eight, configure the user configuration module:

[0115] Open the step length calculation enable, the step length calculation module starts to work, and the step length is calculated according to the step counter count values of the step length latch L1 and the step length latch L2, and is input to the step length register of the user reading module for user reading.

[0116] The step length calculation method is as follows:

[0117] Suppose the period value of the period register is D, the system clock period is T, and the delay time of the delay module B is M. Since the period value D of the period register is unchanged during the working process of the step length calculation circuit, the time W counted by the step counter twice is the same, that is:

[0118] ;

[0119] The delay stage number N is configured with two different stage values, C1 and C2, to generate two step length clocks with different frequencies. After the step counter counts twice, the latch value of the step length latch L1 is V1, and the latch value of the step length latch L2 is V2.

[0120] ;

[0121] ;

[0122] Calculate the intermediate variable H:

[0123] ;

[0124] The step length S calculation formula is as follows:

[0125] ;

[0126] After the step length S is calculated, S is rounded to an integer value, which is the final obtained step length.

[0127] For example, the system clock frequency is 100Mhz, the period T is 10ns, the delay of the delay unit module B is 150ps, and the delay unit has a total of 256 delay stages. The working process is as follows:

[0128] The step length S = T / M = 10ns / 150ps = 67.

[0129] 1. Configure the user configuration module, close the working enable, configure the period register to 65535, configure the delay stage number N to 80 for the first time, and open the step length latch L1 enable;

[0130] 2, open the work enable, the step calculation circuit begins to work for the first time, the count enable is opened;

[0131] 3, read the user read module, read the count enable in a loop, when the user read the count enable is closed, close the work enable, the latch value V1 of the step latch L1 is 26966 (obtained by simulation);

[0132] 4, configure the delay stage N for the second time as 200, close the step latch L1 enable, open the step latch L2 enable;

[0133] 5, open the work enable, the step calculation circuit begins to work for the second time, the count enable is opened;

[0134] 6, read the user read module, read the count enable in a loop, when the user read the count enable is closed, close the work enable, the latch value V2 of the step latch L2 is 10865 (obtained by simulation);

[0135] 7, configure the user configuration module, close the step latch L2 enable, open the step calculation enable, the step calculation module begins to work, the step S is obtained by substituting the step latch L1 latch value 26966 and the step latch L2 latch value 10865 into the calculation formula of the step S:

[0136] ;

[0137] Round the step S value, the integer value of the step S is 67.

[0138] The calculation result shows that the step result calculated by the step calculation circuit is the same as the step result calculated by the system clock period T value 10ns and the delay value 150ps of the delay module B.

[0139] In summary, the step calculation circuit perfectly realizes the automatic calculation of the step, and solves the problem of step error caused by temperature and voltage change.

[0140] The above description of disclosed embodiments enables those skilled in the art to carry out or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit for calculating the step size of an integer frequency pulse signal, characterized in that, It includes a user configuration module, NAND gates, delay units, system counters, comparators, latches, step counters, inverters, AND gate 1, AND gate 2, step latch L1, step latch L2, step calculation module, and user read module; The user configuration module is used to allow users to configure the period value, working enable, delay level N, step size latch L1 enable, step size latch L2 enable, and step size calculation enable of the period register. The NAND gate is used to generate a clock signal for the delay unit based on the user-configured work enable and the step clock returned by the delay unit. The delay unit is used to generate a step clock based on the user-configured delay level N and the clock signal output by the NAND gate, and send it to the step counter, while also feeding it back to the input of the NAND gate. The system counter is used to count according to the system clock and the counting enable, generate a count value and send it to the comparator; The comparator is used to compare the system counter count value and the period value of the user-configured period register to generate a trigger signal. When the two are equal, the trigger signal is valid and is sent to the latch, AND gate 1 and AND gate 2. The latch is used to enable counting according to the user-configured working enable, disable counting when the trigger signal is valid, and send the signal to the system counter, step counter, and user read module. The step counter is used to count based on the step clock generated by the delay unit and the counting enable, and to generate a count value. The inverter is used to invert the user-configured working enable and then clear the system counter and step counter to zero. The AND gate 1 is used to generate latch enable 1 to the step latch L1 according to the trigger signal and the step latch L1 configured by the user. The AND gate 2 is used to generate latch enable 2 for the step latch L2 based on the trigger signal and the step latch L2 configured by the user. The step size latches L1 and L2 are used to latch the count values ​​of the step size counter under two different frequency step size clocks according to latch enable 1 and latch enable 2 respectively. The step size calculation module is used to calculate the step size based on the step size counter count value latched by step size latch L1 and step size latch L2 under the step size calculation enable control configured by the user, and send it to the step size register of the user reading module. The user reading module is used to allow users to read the count enable and step size values.

2. The circuit for calculating the step size of an integer frequency pulse signal according to claim 1, characterized in that, The delay unit includes 256 delay modules B connected in series and one 256-to-1 selector; The delay module B is used to delay the clock signal. The input of the first delay module B is the clock signal output by a NAND gate. Except for the first delay module B, the input of the i-th delay module B is A. i The output is Z. i The output of each delay module B simultaneously enters the next delay module B and the 256-to-1 selector. The 256-to-1 selector is used to select the clock signal output of a certain delay module B according to the delay level N, thus obtaining the step clock. When the delay level N is x, the output Z of the xth delay module B is selected. x Output, i.e., clock step size Z x .

3. A method for calculating the step size of an integer frequency pulse signal, employing a calculation circuit for the step size of an integer frequency pulse signal as described in claim 1 or 2, characterized in that, Includes the following steps: Step 1: Configure the user configuration module: Disable the working enable; the system counter and step counter are automatically cleared; the step clock is turned off; configure the period value of the period register; configure the level value of the delay level N for the first time; enable the step latch L1; disable the step latch L2 and the step calculation enable; Step 2, Configure the user configuration module: When the working enable is turned on, the control NAND gate and delay unit generate the step clock, the latch turns on the counting enable, and the system counter and step counter start the first count. Step 3, read the user's reading module: The counting enable is read cyclically. When the system counter count value equals the period value of the period register, a trigger signal is generated, and the latch disables the counting enable. At this time, the user reads that the counting enable is disabled, which means that the system counter and the step counter have completed the first count. The trigger signal and the step latch L1 enable are both effective. After passing through AND gate 1, latch enable 1 is generated, which latches the step counter count value into the step latch L1. Step 4, Configure the user configuration module: The working enable is turned off, the system counter and step counter are automatically cleared to zero, the trigger signal is invalid, the delay count N level value is configured a second time, making it different from the delay count N level value configured the first time, the step latch L1 is turned off, and the step latch L2 is turned on. Step 5, Configure the user configuration module: When the working enable is turned on, the control NAND gate and delay unit generate a step clock, the latch turns on the counting enable, and the system counter and step counter start the second counting. Step 6, Read the user's reading module: The counting enable is read cyclically. When the system counter count value equals the period value of the period register, a trigger signal is generated, and the latch disables the counting enable. At this time, the user reads that the counting enable is disabled, which means that the system counter and the step counter have completed the second count. The trigger signal and the step latch L2 enable are both effective. After passing through AND gate 2, latch enable 2 is generated, which latches the step counter count value into the step latch L2. Step 7, Configure the user configuration module: The working enable is turned off, the control NAND gate and delay unit are turned off the step clock, the system counter and step counter are automatically cleared, and the step latch L2 is turned off. Step 8, Configure the user configuration module: When step size calculation is enabled, the step size calculation module starts working. It calculates the step size based on the step size counter count value latched by step size latches L1 and L2, and inputs it to the step size register of the user read module for the user to read and use.

4. The method for calculating the step size of an integer frequency pulse signal according to claim 3, characterized in that, The delay level N should be configured such that the step clock frequency is less than the system clock frequency.

5. The method for calculating the step size of an integer frequency pulse signal according to claim 3, characterized in that, In step eight, the step size is calculated as follows: Assume the period value of the period register is D, the delay stage number N is configured with two different stage values, namely C1 and C2, the latch value of step latch L1 is V1, and the latch value of step latch L2 is V2. The formula for calculating step size S is as follows: ； After calculating the step size S, round S to obtain an integer value, which is the final step size.

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