Chip design method and device

Abstract

The invention provides a chip design method and device.The method comprises the steps that design information and netlist information of a chip are obtained, the design information comprises a plurality of first elements for chip design, and the netlist information comprises the connection relation among the first elements; the first element comprises any one or more of a macro cell, a port, a standard cell, an input / output unit and an IP core; according to the design information, a plurality of second elements are determined, and the second elements comprise any one or more of a macro cell group, a port group, a standard cell group, a block, a block group, an input and output unit group and an IP core group; obtaining a first design result of the chip according to the design information, the netlist information and the plurality of second elements, the first design result comprising a data flow relationship among a plurality of third elements, and the third elements comprising the first element or the second element; and displaying the first design result on the interface. According to the method provided by the invention, the chip design efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip design method and device. Background Art

[0002] The chip design process can be divided into two parts: logic design (also known as front-end design) and physical design (also known as back-end design). The physical design process of a chip is the process of optimizing multiple circuits for various metrics, such as circuit area, trace length, and power consumption.

[0003] The traditional physical design phase includes floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff. Many of these steps require significant manual intervention and numerous iterations to achieve timing, power, performance, and area (PPA) convergence. This process relies heavily on engineer experience and requires significant time and repeated iterations to achieve the desired physical design results, significantly impacting chip design iteration cycles. Summary of the Invention

[0004] The present application provides a chip design method and device, which can improve the efficiency of chip design.

[0005] In a first aspect, a chip design method is provided, the method comprising: obtaining design information and netlist information of a chip, the design information comprising a plurality of first elements for chip design, the netlist information comprising a connection relationship between the plurality of first elements, the first elements comprising any one or more of a macro cell, a port, a standard cell, an input and output (IO) cell, and an intellectual property (IP) core; determining a plurality of second elements based on the design information, the second elements comprising any one or more of a macro cell group, a port group, a standard cell group, a block, a block group, an input and output cell group, and an IP core group; obtaining a first design result of the chip based on the design information, the netlist information, and the plurality of second elements, the first design result comprising a data flow relationship between a plurality of third elements, the third element comprising the first element or the second element; and displaying the first design result on an interface.

[0006] This application provides a chip design method that not only supports fine-grained data flow display, but also supports coarse-grained data flow display. Users can customize the display of data flow according to their needs, adapt to various application scenarios, and improve the design efficiency of the chip.

[0007] The first element is a fine-grained element, the second element is a coarse-grained element, and the second element may include the first element. For example, a macrocell group includes multiple macrocells, a port group includes multiple ports, a standard cell group includes multiple standard cells, an input / output cell group includes multiple input / output cells, and an IP core group includes multiple IP cores. A block may include any one or more of a macrocell, a port, or a standard cell, and a block group includes multiple blocks.

[0008] It should be understood that ports are used for data exchange within the chip, and IO units are used for data exchange with data outside the chip. IP cores are pre-designed circuit function modules in the chip.

[0009] Exemplarily, the second element may be obtained according to the data flow of the first element or through clustering.

[0010] The first design result may include data flow relationships between macro cells, ports, standard cells, IO cells, IP cores, macro cell groups, port groups, standard cell groups, blocks, block groups, input-output cell groups, and IP core groups, such as the data flow relationship between macro cells and macro cells, the data flow relationship between macro cell groups and port groups, the data flow relationship between block groups and input-output cell groups, etc.

[0011] For example, the user may input chip design information and netlist information through a graphical user interface (GUI) or a tool command language (TCL).

[0012] Exemplarily, the first design result may be displayed on a GUI.

[0013] In combination with the first aspect, in certain implementations of the first aspect, the first design result further includes any one or more of the weight, number of paths, and path length corresponding to the data flow relationship.

[0014] The data flow relationship between two third elements may include at least one path, and the sum of the weights of the at least one path is the weight corresponding to the data flow relationship. The path length is the number of registers included in the path between the two third elements. Exemplarily, the number of paths and the path length between the two third elements can be represented by a numerical combination, where the i-th number separated by " / " in the numerical combination represents the number of paths with a path length of i between the two third elements corresponding to the data flow, where i is an integer greater than or equal to 0. For example, the numerical combination corresponding to a data flow relationship is "1 / 4 / 6", which indicates that there is one path with a path length of 0, four paths with a path length of 1, and six paths with a path length of 2 between the two third elements corresponding to the data flow relationship. The above method of displaying the number of paths and path lengths is only an example. The weight, number of paths, or path length corresponding to the data flow relationship can also be displayed in a list or table. The above example should not be understood as a limitation of this application.

[0015] In one possible implementation, the data flow relationship between two third elements can be displayed on the interface as a flying line. The greater the weight of the data flow relationship, the more paths there are, and the shorter the path length, the thicker the flying line on the interface. The smaller the weight of the data flow relationship, the fewer paths there are, and the longer the path length, the thinner the flying line on the interface.

[0016] This application provides a chip design method, which can also display the weight, number of paths or path length corresponding to the data flow relationship of the elements on the interface, which can help users confirm key data flow relationships, optimize key paths, and improve the efficiency of chip design.

[0017] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: receiving a filtering request input by a user, the filtering request being used to request hiding part of the data flow relationship; and displaying the first design result after hiding on the interface according to the filtering request.

[0018] Exemplarily, the user may input the filtering request through a GUI button or a TCL command, requesting to filter the partial data flow relationships that meet the conditions or do not meet the conditions.

[0019] Exemplarily, the manifestation of hiding on the interface can be that the flying lines corresponding to some data streams completely disappear on the interface, or the flying lines are displayed in an extremely thin form, or the flying lines are displayed in an extremely light color. This application does not impose any restrictions on this.

[0020] The present application provides a chip design method that can selectively hide some data flow relationships, helping users to process the data flow relationships between elements in a targeted manner to avoid the impact of interference signals on valid signals.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the filtering request includes any one or more of special signal filtering, weight filtering, and path length filtering. The special signal filtering is used to indicate the hiding of data flow relationships related to preset signals, the weight filtering is used to indicate the hiding of data flow relationships whose weights are less than a first preset threshold, and the path length filtering is used to indicate the hiding of data flow relationships whose path lengths are greater than a second preset threshold.

[0022] For example, the preset signal may include a clock (CLK) signal, a design for test (DFT) signal, etc. The user may input the preset signal to be filtered through the GUI or TCL.

[0023] For example, the user may input a first preset threshold value through the GUI or TCL, and the interface may hide data flow relationships with weights less than the first preset threshold value according to user needs.

[0024] For example, the user may input a second preset threshold value through the GUI or TCL, and the interface may hide data flow relationships whose path lengths are greater than the second preset threshold value according to user requirements.

[0025] The present application provides a chip design method that can selectively hide some data flow relationships, helping users to process the data flow relationships between elements in a targeted manner to avoid the impact of interference signals on valid signals.

[0026] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: receiving an emphasis request input by a user, the emphasis request being used to request highlighting of part of the data flow relationship; and displaying the first design result after the highlighting on the interface according to the emphasis request.

[0027] Exemplarily, the user may input the emphasis request through a GUI button or a TCL command, requesting to emphasize a portion of the data flow relationship that meets the condition or does not meet the condition.

[0028] Exemplarily, the user may input the emphasis request through the GUI or TCL, requesting to emphasize the display of data flow relationships whose weight is greater than a third preset threshold, or data flow relationships whose path length is less than a fourth preset threshold.

[0029] Exemplarily, the emphasis on the interface can be reflected by highlighting the flying lines corresponding to some data streams on the interface, or displaying the flying lines in bold on the interface, or marking the flying lines with special colors. This application does not impose any restrictions on this.

[0030] This application provides a chip design method that can selectively emphasize some data flow relationships to help users perform targeted optimization of important signals.

[0031] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: receiving a rollback request input by a user, the rollback request being used to request display of a second design result, the first design result being the chip design result at a first moment, the second design result being the chip design result at a second moment, the second moment being earlier than the first moment; and displaying the second design result on the interface according to the rollback request.

[0032] The present application provides a chip design method that supports a rollback operation for displaying data flow relationships, allowing users to view the data flow relationships before changes during the layout process for comparison, and helping users or automated algorithms to evaluate the layout quality.

[0033] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: receiving a data flow relationship change request input by a user, the data flow relationship change request being used to indicate adding or deleting a first path in the first design result, the first path being a path between a fourth element and a fifth element, the fourth element and the fifth element being one of the multiple third elements; and displaying a first data flow relationship on the interface according to the data flow relationship change request, the first data flow relationship being the data flow relationship between the fourth element and the fifth element after adding or deleting the first path.

[0034] It should be understood that there is at least one path between the fourth element and the fifth element. When the user inputs a data flow relationship change request or the automated layout algorithm instructs to add or delete part of the path, the present application can adaptively update the data flow relationship between the fourth element and the fifth element.

[0035] In some possible implementations, the path may be a feedthrough.

[0036] This application provides a chip design method that supports adaptive and rapid updating of data flow relationships when the connection relationship between elements changes, and provides the user with the current latest data flow relationship status, making it convenient for users to perform design quality assessment and other operations.

[0037] In combination with the first aspect, in some implementations of the first aspect, the method further includes: displaying any one or more of the weight, number of paths, and path length corresponding to the first data flow relationship on an interface.

[0038] When the user inputs a request to change the data flow relationship or the automated layout algorithm instructs to add or delete part of the path, the present application can adaptively update the weight, number of paths, and path length corresponding to the data flow relationship between the fourth element and the fifth element, and display the latest design results on the interface.

[0039] The present application provides a chip design method that supports adaptive and rapid updating of data flow relationships and the weights, number of paths, and path lengths corresponding to the data flow relationships when the connection relationship between elements changes, and provides the user with the latest data flow relationship status, making it convenient for the user to perform design quality assessment and other operations.

[0040] In combination with the first aspect, in certain implementations of the first aspect, the value of the first weight is proportional to the number of first paths and inversely proportional to the length of the first path, the first weight is the weight corresponding to the data flow relationship between the sixth element and the seventh element, the first path number is the number of paths between the sixth element and the seventh element, the first path length is the number of registers included in the path between the sixth element and the seventh element, and the sixth element and the seventh element are one of the multiple third elements.

[0041] This application does not limit the proportional or inversely proportional functional relationship, and can be, for example, a linear functional relationship or a quadratic functional relationship. The greater the number of first paths and the shorter the first path lengths, the greater the first weight value; the fewer the number of first paths and the longer the first path lengths, the smaller the first weight value.

[0042] This application provides a chip design method that can define the weights corresponding to data flow relationships, help users identify key data flow relationships, optimize key paths, and improve the efficiency of chip design.

[0043] In combination with the first aspect, in certain implementations of the first aspect, obtaining the first design result of the chip based on the design information, the netlist information and the multiple second elements includes: constructing a data flow relationship directed graph based on the design information, the netlist information and the multiple second elements, the data flow relationship directed graph including the connection relationship between the multiple third elements; obtaining the first design result based on the data flow relationship directed graph.

[0044] The present application provides a chip design method, which can obtain coarse-grained elements based on fine-grained elements, and construct a directed graph based on the relationship between these elements. It not only supports fine-grained data flow display, but also supports coarse-grained data flow display. Users can customize the display of data flow according to their needs, adapt to various application scenarios, and improve the design efficiency of the chip.

[0045] In combination with the first aspect, in some implementations of the first aspect, the third element further includes a sub-pseudo-module, and the sub-pseudo-module is a module obtained by splitting the core area of ​​the chip.

[0046] The embodiment of the present application can split the core area of ​​the chip according to the size of the core area. For example, the splitting is performed when the condition Acells>Adie×ratio, ratio=0.4 is met, and the corresponding information is saved for the subsequent netlist graph modeling. Among them, Acells represents the area of ​​the core area of ​​the chip, Adie represents the area of ​​the wafer, that is, the area within the outer frame of the entire chip, and ratio is a preset ratio. This condition can be understood as when the area of ​​the core area exceeds 40% of the total area of ​​the chip, the core area is split, that is, the core area is split into multiple sub-pseudo modules.

[0047] This application provides a chip design method that can split the core area, refine the connection relationship between elements, and display a more accurate connection relationship between elements on the interface.

[0048] In a second aspect, a computer device is provided, including: an acquisition module for acquiring design information and netlist information of a chip, the design information including multiple first elements for chip design, the netlist information including connection relationships between the multiple first elements, the first elements including any one or more of macro cells, ports, standard cells, input-output cells, and IP cores; a processing module for determining multiple second elements based on the design information, the second elements including any one or more of macro cell groups, port groups, standard cell groups, blocks, block groups, input-output cell groups, and IP core groups; the processing module is also used to obtain a first design result of the chip based on the design information, the netlist information and the multiple second elements, the first design result including a data flow relationship between multiple third elements, the third elements including the first element or the second element; a display module for displaying the first design result on an interface.

[0049] In combination with the second aspect, in certain implementations of the second aspect, the first design result also includes any one or more of the weight, number of paths, and path length corresponding to the data flow relationship.

[0050] In combination with the second aspect, in certain implementations of the second aspect, the acquisition module is further used to receive a filtering request input by a user, and the filtering request is used to request hiding part of the data flow relationship; the display module is further used to display the first design result after hiding on the interface according to the filtering request.

[0051] In combination with the second aspect, in certain implementations of the second aspect, the filtering request includes any one or more of special signal filtering, weight filtering, and path length filtering. The special signal filtering is used to indicate the hiding of data flow relationships related to preset signals, the weight filtering is used to indicate the hiding of data flow relationships whose weights are less than a first preset threshold, and the path length filtering is used to indicate the hiding of data flow relationships whose path lengths are greater than a second preset threshold.

[0052] In combination with the second aspect, in certain implementations of the second aspect, the acquisition module is further used to receive an emphasis request input by a user, and the emphasis request is used to request highlighting of part of the data flow relationship; the display module is further used to display the first design result after the highlighting on the interface according to the emphasis request.

[0053] In combination with the second aspect, in certain implementations of the second aspect, the acquisition module is further used to receive a rollback request input by the user, and the rollback request is used to request display of a second design result, where the first design result is the chip design result at a first moment, and the second design result is the chip design result at a second moment, and the second moment is earlier than the first moment; the display module is further used to display the second design result on the interface according to the rollback request.

[0054] In combination with the second aspect, in certain implementations of the second aspect, the acquisition module is further used to receive a data flow relationship change request input by a user, wherein the data flow relationship change request is used to indicate the addition or deletion of a first path in the first design result, wherein the first path is the path between the fourth element and the fifth element, and the fourth element and the fifth element are one of the multiple third elements; the display module is further used to display a first data flow relationship on the interface according to the data flow relationship change request, wherein the first data flow relationship is the data flow relationship between the fourth element and the fifth element after adding or deleting the first path.

[0055] In combination with the second aspect, in some implementations of the second aspect, the display module is further used to display any one or more of the weight, number of paths, and path length corresponding to the first data flow relationship on the interface.

[0056] In combination with the second aspect, in certain implementations of the second aspect, the value of the first weight is proportional to the number of first paths and inversely proportional to the length of the first path, the first weight is the weight corresponding to the data flow relationship between the sixth element and the seventh element, the first path number is the number of paths between the sixth element and the seventh element, the first path length is the number of registers included in the path between the sixth element and the seventh element, and the sixth element and the seventh element are one of the multiple third elements.

[0057] In combination with the second aspect, in certain implementations of the second aspect, the processing module is specifically used to: construct a data flow relationship directed graph based on the design information, the netlist information and the multiple second elements, the data flow relationship directed graph including the connection relationship between the multiple third elements; and obtain the first design result based on the data flow relationship directed graph.

[0058] In combination with the second aspect, in some implementations of the second aspect, the third element further includes a sub-pseudo-module, and the sub-pseudo-module is a module obtained by splitting the core area of ​​the chip.

[0059] The beneficial effects of the second aspect and any possible implementation of the second aspect correspond to the beneficial effects of the first aspect and any possible implementation of the first aspect, and will not be elaborated on herein.

[0060] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor, wherein the processor is used to couple with a memory, read and execute instructions and / or program codes in the memory to execute the first aspect or any possible implementation of the first aspect.

[0061] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores program code. When the computer storage medium runs on a computer, it enables the computer to execute the first aspect or any possible implementation of the first aspect.

[0062] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 is an exemplary flow chart for physical design implementation.

[0064] Figure 2 This is an exemplary flow chart of a chip design method provided in an embodiment of the present application.

[0065] Figure 3 This is an application architecture diagram of a chip design method provided in an embodiment of the present application.

[0066] Figure 4 This is an application architecture diagram of another chip design method provided in an embodiment of the present application.

[0067] Figure 5 This is a schematic diagram of a chip design result provided in an embodiment of the present application.

[0068] Figure 6 This is an exemplary flowchart of data flow relationship extraction provided in an embodiment of the present application.

[0069] Figure 7 This is a schematic diagram of a chip without a channel.

[0070] Figure 8 This is a schematic diagram of a non-channelless chip.

[0071] Figure 9 This is a schematic diagram of a data flow relationship directed graph provided in an embodiment of the present application.

[0072] Figure 10 This is a schematic diagram of adding a sub-pseudo-module provided in an embodiment of the present application.

[0073] Figure 11 This is a schematic diagram of adding coarse-grained element markings provided in an embodiment of the present application.

[0074] Figure 12 This is a schematic diagram of a path search provided in an embodiment of the present application.

[0075] Figure 13 This is a schematic diagram of path weight confirmation provided in an embodiment of the present application.

[0076] Figure 14 This is a schematic diagram of a feed-through mold provided in an embodiment of the present application.

[0077] Figure 15 This is a schematic diagram of a special signal processing provided in an embodiment of the present application.

[0078] Figure 16 This is an exemplary flowchart of data flow relationship adaptation provided by an embodiment of the present application.

[0079] Figure 17 This is a schematic diagram of an application scenario of a chip design method provided in an embodiment of the present application.

[0080] Figure 18 This is a schematic diagram of an application scenario of another chip design method provided in an embodiment of the present application.

[0081] Figure 19 This is a schematic diagram of an application scenario of another chip design method provided in an embodiment of the present application.

[0082] Figure 20 This is a schematic diagram of a chip design result provided in an embodiment of the present application.

[0083] Figure 21 This is a schematic diagram of another chip design result provided in an embodiment of the present application.

[0084] Figure 22 This is a schematic diagram of an interaction method provided in an embodiment of the present application.

[0085] Figure 23 This is a schematic diagram of another chip design result provided in an embodiment of the present application.

[0086] Figure 24 This is a schematic diagram of another interaction method provided in an embodiment of the present application.

[0087] Figure 25 This is a structural example diagram of a computer device provided in an embodiment of the present application.

[0088] Figure 26 This is a structural example diagram of another computer device provided in an embodiment of the present application.

[0089] Figure 27 This is an example diagram of a computer program product provided in an embodiment of the present application. DETAILED DESCRIPTION

[0090] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts should fall within the scope of protection of this application.

[0091] In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0092] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0093] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0094] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0095] To facilitate understanding of the embodiments of the present application, some definitions involved in the present application are first briefly explained.

[0096] 1. Electronic design automation (EDA): refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large-scale integrated circuit chips.

[0097] 2. Macrocell: A pre-layout, functional block, such as a memory block, an analog component, or a complex digital module (such as a processor core).

[0098] 3. Design for test (DFT) signal: By inserting various hardware logics into the original chip design to improve the chip's testability (including controllability and observability), the chip becomes easier to test.

[0099] The chip design process can be divided into two parts: logic design (also known as front-end design) and physical design (also known as back-end design). The physical design process covers the entire process from register transfer level (RTL) code to the final output of the integrated circuit layout (graphical design system (GDS) file). It is the process of optimizing multiple circuits for various indicators, such as circuit area, trace length, and power consumption.

[0100] Figure 1 It is an exemplary flow chart of physical design implementation. Traditional physical design implementation includes steps such as floorplanning, layout, clock tree synthesis, routing, timing convergence and sign-off. Many of these steps require a high degree of manual intervention, and a large number of manual iterations are required to achieve timing power, performance and area (PPA) convergence. For a long time, this process has been highly dependent on the experience of engineers, and it takes a lot of time to iterate repeatedly to obtain suitable physical design results, which significantly affects the iteration cycle of chip design. In addition, this design method is a design iteration driven by test results, which has many disadvantages, such as a long feedback cycle for downstream task results, a lot of time spent on repeated iterations, and a huge multi-objective optimization search space.

[0101] The embodiments of the present application provide a chip design method that seeks invariants of the physical design process from first principles to guide design optimization. At the same time, the original netlist structure can be semantically reconstructed and reduced to obtain the data flow relationship between fine-grained elements and coarse-grained elements, and the automated algorithm and human-computer interaction can be guided in a forward-driven manner to achieve the optimal PPA suitable for the target application, reduce the layout planning time of back-end engineers, improve the efficiency of chip design, and accelerate the design speed.

[0102] Figure 2 This is an exemplary flow chart of a chip design method provided in an embodiment of the present application.

[0103] 210, obtain chip design information and netlist information.

[0104] The design information includes a plurality of first elements for chip design, and the netlist information includes the connection relationships between the plurality of first elements. The first elements include any one or more of macro cells, ports, standard cells, input and output (IO) cells, and intellectual property (IP) cores.

[0105] For example, the user may input chip design information and netlist information through GUI or TCL.

[0106] 220, determine multiple second elements.

[0107] According to the design information, a plurality of second elements are determined, wherein the second elements include any one or more of a macro cell group, a port group, a standard cell group, a block, a block group, an input / output cell group, and an IP core group.

[0108] The first element is a fine-grained element, the second element is a coarse-grained element, and the second element may include the first element. For example, a macrocell group includes multiple macrocells, a port group includes multiple ports, a standard cell group includes multiple standard cells, an input / output cell group includes multiple input / output cells, and an IP core group includes multiple IP cores. A block may include any one or more of a macrocell, a port, or a standard cell, and a block group may include multiple blocks.

[0109] Exemplarily, the second element may be obtained according to the data flow of the first element or through clustering.

[0110] 230, obtain a first design result of the chip.

[0111] A first design result of the chip is obtained based on the design information, the netlist information and the plurality of second elements. The first design result includes a data flow relationship between a plurality of third elements, and the third elements include the first element or the second element.

[0112] The first design result may include data flow relationships between macro cells, ports, standard cells, IO cells, IP cores, macro cell groups, port groups, standard cell groups, blocks, block groups, input-output cell groups, and IP core groups, such as the data flow relationship between macro cells and macro cells, the data flow relationship between macro cell groups and port groups, the data flow relationship between block groups and input-output cell groups, etc.

[0113] 240. Display the first design result on the interface.

[0114] Exemplarily, the first design result may be displayed on a GUI.

[0115] Figure 3 This is an application architecture diagram of a chip design method provided in an embodiment of the present application.

[0116] The chip design method provided in the embodiment of the present application can obtain the design information and netlist information of the chip, group the fine-grained elements to obtain coarse-grained elements, and extract the data flow relationship between the elements at the same time. By applying automated algorithms, interactive iterations and quality inspection functions, the design results of the chip are obtained.

[0117] The chip design method provided in the embodiments of this application can be applied in the layout planning stage of physical design. The embodiments of this application can apply data flow relationships and corresponding weights to the chip / subsystem layout planning stage, performing interactive iterations to improve design efficiency, or assist various automated algorithms in chip PPA optimization, thereby improving chip layout optimization efficiency and quality.

[0118] Figure 4 This is an application architecture diagram of another chip design method provided in an embodiment of the present application.

[0119] The application architecture of the chip design method provided in this application can be divided into three parts: the application layer, the interface layer, and the algorithm layer. The application layer includes, but is not limited to, fly-line display, path display, estimator, and partitioning. The interface layer includes various user interfaces for easy access. The algorithm layer includes modeling, search, and adaptive data flow relationships after changes to netlist relationships.

[0120] For given netlist information, whether flattened or hierarchical, coarse-grained or fine-grained, the chip design method provided in this application can adopt a unified framework, unified modeling, and a unified model to extract, apply and visualize different hierarchical relationships.

[0121] Figure 5 This is a schematic diagram of a chip design result provided in an embodiment of the present application.

[0122] The diagram includes data flow relationships between different elements, such as data flow relationships between elements at different levels. Elements at different levels include macrocells, ports, standard cells, IO cells, IP cores, macrocell groups, port groups, standard cell groups, blocks, block groups, I / O cell groups, and IP core groups. Figure 5 IP1 and IP2 are different IP cores, and Block1 to Block3 are different blocks.

[0123] The chip design result may also include any one or more of the weights, number of paths, and path lengths corresponding to the data flow relationships between different elements. Figure 5 Middle W IP1-B1 It represents the weight between IP1 and Block1, W IP2-B1 It represents the weight between IP2 and Block1, W B1-B3 It represents the weight between Block1 and Block3, W B2-B3 It represents the weight between Block2 and Block3.

[0124] In a possible implementation, the more paths there are between fine-grained elements, the greater their weights are, and the shorter their path lengths are, the thicker and more obvious the lines between the corresponding coarse-grained elements displayed on the interface will be.

[0125] Figure 6 This is an exemplary flowchart of data flow relationship extraction provided in an embodiment of the present application.

[0126] 610, core area split.

[0127] Figure 7 This is a schematic diagram of a channel-free chip. b1 to b3 represent different modules. This type of chip is very large in scale, but the chip structure and clock structure are relatively simple, with a large number of repeated IP cores. The opposite of the channel-free chip is the non-channel-free chip. Figure 8 This is a schematic diagram of a non-channelless chip. b1 to b3 represent different modules. The blank area in the figure is the core area. The core area refers to the area that does not belong to any module and may contain some standard units.

[0128] The embodiment of the present application can determine the type of chip based on the input netlist information. If the type of the chip is a non-channelless type chip, the core area can be split according to the size of the core area and split into multiple sub-pseudo modules. Optionally, the multiple sub-pseudo modules can also be clustered. For example, when the condition Acells>Adie×ratio and ratio=0.4 are met, splitting and clustering are performed, and the corresponding information is saved for the subsequent step of constructing a directed graph. Among them, Acells represents the area of ​​the core area of ​​the chip, Adie represents the area of ​​the wafer, that is, the area within the outer frame of the entire chip, and ratio is a preset ratio. This condition can be understood as when the area of ​​the core area exceeds 40% of the total area of ​​the chip, the core area is split and clustered, that is, the core area is split into multiple sub-pseudo modules, and cohesive targets are added between the multiple sub-pseudo modules for clustering. It should be understood that ratio=0.4 in the above example is only one possible implementation method, and ratio can also be any value between 0.35 and 0.8. The above example should not be understood as a limitation to the present application.

[0129] 620, directed graph construction.

[0130] The embodiment of the present application can construct a directed graph based on the input netlist information and design information, including the steps of coarse-grained element extraction, netlist diagram establishment, sub-pseudo-module addition, and coarse-grained element marking.

[0131] Coarse-grained elements can be extracted from the fine-grained elements in the design information. Fine-grained elements include any one or more of macrocells, ports, standard cells, I / O cells, and IP cores. Coarse-grained elements include any one or more of macrocell groups, port groups, standard cell groups, blocks, block groups, I / O cell groups, and IP core groups.

[0132] A directed graph can be constructed based on the design information, netlist information and the extracted coarse-grained elements. Figure 9 It is a schematic diagram of a data flow relationship directed graph provided in an embodiment of the present application, where each node in the graph can be a coarse-grained element or a fine-grained element.

[0133] Figure 10 This is a schematic diagram of adding a pseudo-submodule according to an embodiment of the present application. Based on the pseudo-submodules and netlist information obtained by splitting in step 610, corresponding pseudo-submodules and their connection relationships are added to the data flow directed graph. It should be understood that this step is optional, and adding pseudo-submodules can more accurately express the connection relationships between modules.

[0134] Figure 11 This is a schematic diagram of adding coarse-grained element labels provided by an embodiment of the present application. The embodiment of the present application labels the coarse-grained elements in the directed graph and stores the corresponding pin information for querying the fine-grained data stream of the pin corresponding to the coarse-grained data stream in the next step 630.

[0135] 630, path confirmation.

[0136] According to the directed graph constructed in step 620, path confirmation is performed, and the path confirmation includes the steps of path search, path storage, and path weight confirmation.

[0137] Figure 12 This is a schematic diagram of a path search provided by an embodiment of the present application. Based on the directed graph constructed in step 620, a path search is performed starting from the marked coarse-grained element node, all connecting paths between it and other coarse-grained element nodes are obtained, and the paths are saved. Table 1 is an example of path saving.

[0138] Table 1

[0139] path Block-sub-pseudo-module 1 Block-sub-pseudo-module 2 …… Block-Standard Unit 1-Block Group Block group-sub-pseudo-module 2

[0140] Figure 13This is a schematic diagram of a path weight confirmation provided by an embodiment of the present application. Based on the saved path, the path weight between the target nodes is confirmed. This weight is the weight corresponding to the coarse-grained data flow relationship. At the same time, the embodiment of the present application can confirm the path relationship, the number of paths, and the start / end pin data flow relationship (i.e., the fine-grained data flow) corresponding to the coarse-grained data flow relationship.

[0141] 640, Data Flow Relationship Adaptation.

[0142] Adaptation of data flow relationships includes that when a user or algorithm instructs to add or delete a portion of a path, the embodiment of the present application can automatically adjust the data flow relationship between elements corresponding to the changed path.

[0143] Exemplarily, the path change includes feedthrough and related special signal processing. Exemplarily, the special signal may include a clock (CLK) signal, a design for test (DFT) signal, and the like.

[0144] Figure 14 This is a schematic diagram of a feedthrough provided by an embodiment of the present application. Feedthrough means that in the process of obtaining the chip layout, if two modules are connected, but the two modules are not placed adjacent to each other or the length of the adjacent common side cannot accommodate all the pins, then it is necessary to use feedthrough technology to pass through other modules to connect the two modules that have a connection relationship but are not adjacent or cannot be placed adjacent to each other. Since the layout planning process of the entire chip will update the netlist, such as adding feedthrough, deleting feedthrough, or running the feedthrough of the entire chip (add / delete / run feedthrough), the data flow relationship needs to be adaptively updated according to the new feedthrough information. The specific adaptive update process can be found in Figure 16 Description.

[0145] Figure 15 1 is a schematic diagram of a special signal processing provided by an embodiment of the present application. The special signal processing includes filtering and / or emphasizing the special signal. Figure 15 (b) is a schematic diagram of special signal filtering provided in an embodiment of the present application. Figure 15 (c) is a schematic diagram of special signal emphasis provided in an embodiment of the present application. Figure 15 (a) is the original data stream obtained according to step 630, that is, all paths. All paths are marked one by one. If there is a special signal in the path, you can choose to filter the path, that is, hide the flying line on the interface corresponding to the path, such as Figure 15As shown in (b), it helps engineers avoid interference from irrelevant signals and clarify the relationship between valid signals. Optionally, the path can also be emphasized, such as marking the corresponding flying wires of the path with special colors, bolding or highlighting, etc., to help users perform targeted optimization, such as Figure 15 As shown in (c).

[0146] Figure 16 This is an exemplary flowchart of data flow relationship adaptation provided by an embodiment of the present application.

[0147] 810, update the mapping relationship between the ID and name of all pins on the block.

[0148] Map the pin names and identity documents (IDs) in a block, and use IDs instead of pin names to reduce storage space waste.

[0149] 820, update the data flow relationship between blocks.

[0150] Traverse the blocks in the chip design. For each block A, obtain the connection relationship between block A and its adjacent block B, and classify the connection relationship. For example, the classification can be divided into connection relationships from block A to block B and from block B to block A, that is, block A->block B and block B->block A.

[0151] 830, update the data flow relationship between the block and the port.

[0152] Traverse the blocks in the chip design, and for each block A, obtain the connection relationship between block A and the port, and classify the connection relationship. For example, the classification can be from which port group to block A, because the grouping of the port may change as the netlist information is adjusted.

[0153] 840, update the weight, path, and number of paths of the direct connection signal.

[0154] Obtain the original indirect and direct signals in the chip design. Since feedthrough only operates on direct signals, only the paths, weights, and number of paths of the corresponding direct signals need to be updated. In chip design, a direct signal is a signal path that directly connects two or more circuit elements without passing through any intermediate logic gates or registers.

[0155] 850, check whether it has changed and return the change information.

[0156] If the path, weight, or number of paths of the direct connection signal has changed compared to the original direct connection signal, the change information is returned. If there is no change, the data flow relationship adaptation operation ends.

[0157] 860, update the pin connection according to the data flow relationship.

[0158] Update the connection relationship of the pins according to the data flow relationship after feedthrough.

[0159] Figure 17 This is a schematic diagram of an application scenario of a chip design method provided in an embodiment of the present application.

[0160] Figure 17 The following is a schematic diagram of determining the module position in chip design, as shown in Figure 17 As shown in (a), the embodiment of the present application can first convert the directed relationship of the data flow into an undirected relationship to facilitate flexible layout, for example, W A-B =W A->B +W B->A .W A-B The weight of the data flow relationship between block A and block B, W A->B represents the weight of the data flow relationship from block A to block B, W B->A Indicates the weight of the data flow relationship from block B to block A. It should be understood that the step of converting the directed data flow relationship into an undirected relationship is an optional step, and the next placement operation can also be performed directly.

[0161] Based on the data flow relationship between the block and the port, IO unit and IP core, the block can be divided into a strong pull block and a weak pull block. Since the position of the port, IO unit and IP core is determined first in chip design, the block with a data flow relationship with any of the ports, IO units and IP cores is a strong pull block, for example Figure 17 Blocks 1, 2, and 3 in (b) are weakly pulled blocks. Blocks that do not have data flow relationships with any of the ports, IO units, and IP cores are weakly pulled blocks, for example Figure 17 Block 4 in (b). In the chip design method provided in the embodiment of the present application, the strong pulling blocks are placed first, and then the remaining weak pulling blocks are placed.

[0162] Figure 18 This is a schematic diagram of an application scenario of another chip design method provided in an embodiment of the present application.

[0163] Figure 18The figure shows a schematic diagram of pin grouping in chip design. Because the number of pins in chip design is huge, the pin placement problem is highly complex and is basically an NP-hard (deterministic polynomial-time hardness, NP-hard) problem. Therefore, the embodiment of the present application can group pins by utilizing the data flow relationship between directed fine-grained elements. For specific methods, refer to Figure 18 , group pins with the same connection relationship together, for example Figure 18 (a) , multiple pins whose data flow ends at the same standard cell group are grouped together; Figure 18 (b) , multiple pins whose data flow starting points are the same macro unit group are grouped together; Figure 18 (c) Grouping multiple pins whose data flow ends at the same IP core into one group. In the embodiment of the present application, grouping pins can effectively reduce the complexity of the pin placement problem and obtain a better design result.

[0164] Figure 19 This is a schematic diagram of an application scenario of another chip design method provided in an embodiment of the present application.

[0165] Figure 19 (a) is a schematic diagram of the original pin placement. Figure 19 (b) is a schematic diagram of the optimized pin placement. During the pin improvement stage, the embodiment of the present application can find the shortest path between pins based on the obtained chip design results, shorten the connection between pins in the design, and improve PPA.

[0166] Figure 20 This is a schematic diagram of a chip design result provided in an embodiment of the present application.

[0167] The chip design method provided in this application can be implemented by a chip design tool. The chip design tool can parse the input netlist information and design information, obtain coarse-grained elements based on fine-grained elements, and construct a data flow relationship directed graph based on the connection relationship between the elements. In the data flow relationship directed graph, elements of different granularity are nodes, and the edge information is the netlist connection relationship of the elements. Then, according to the data flow relationship directed graph, a search is performed, such as a depth first search (DFS) or a breadth first search (BFS) to obtain all the paths connecting the elements. The data flow relationship directed graph and the layout optimization algorithm are then used to obtain the layout results of the chip, and the flying lines are displayed in a graphical user interface (GUI). The layout optimization algorithm can also consider the fan-in and fan-out connection relationship of the combinational circuit. Finally, the number of paths and the path length are converted into the weight of the data flow relationship and displayed on the GUI. Figure 20 The connections between different blocks, IP / IO units, standard cell groups (cells), macro units (macro), and ports are flying lines. It should be understood that the weight corresponding to the data flow relationship is proportional to the number of paths between elements and inversely proportional to the length of the paths between elements.

[0168] In one possible application scenario, users can customize the maximum width of the fly line. The greater the weight of the data flow relationship, the thicker the fly line. Users can display all or part of the data flow relationship through the GUI.

[0169] The chip design method provided in this application can cover the netlist at the chip / subsystem (block) level, such as Figure 20 As shown, whether flattened or hierarchical, whether coarse-grained or fine-grained, this application can use a unified modeling form to hierarchically display data flow relationships. At the same time, the chip design method provided by this application supports the visualization of full or partial data flow relationships, and can also be customized according to user needs.

[0170] Figure 21 This is a schematic diagram of another chip design result provided in an embodiment of the present application.

[0171] Figure 21 (a) is a schematic diagram of the full or partial data flow relationship of the chip. Figure 20All the extracted paths are classified according to the path length, and the number of paths is displayed in the form of a digital combination based on the classification results. Each data flow corresponds to a digital combination, which represents the number of paths and the path length. The path length refers to the number of registers that the connection between two elements passes through. The i-th number separated by " / " in the digital combination represents the number of paths with a path length of i between the two elements corresponding to the data flow relationship, where i is an integer greater than or equal to 0. For example, the digital combination corresponding to a certain data flow relationship is "1 / 4 / 6", which means that there is 1 path with a path length of 0 between the two elements corresponding to the data flow relationship, 4 paths with a path length of 1, and 6 paths with a path length of 2.

[0172] Figure 21 (b) is a schematic diagram of the chip design result display mode. The embodiment of the present application can also selectively display part of the design results of the chip, for example, only displaying the selected element type. In one possible implementation, the user can choose the percentage of data flow relationships to be displayed, that is, the maximum weight of the data flow relationship can be multiplied by the filtering percentage to obtain the filtered weight threshold, and then hide the data flow relationships whose weight is less than the threshold. In one possible implementation, the user can also choose to display data flow relationships whose path length is less than a specified length threshold, for example, only displaying data flow relationships whose path length is less than 10. The path length of a data flow relationship can be the sum or mean of at least one path corresponding to the data flow relationship.

[0173] The embodiment of the present application can also support the display of a single data flow relationship or a grouped data flow relationship. Figure 21 (c) is a schematic diagram showing the relationship of a single data flow. Figure 21 (d) is a schematic diagram showing the relationship between packet data flows.

[0174] Figure 22 This is a schematic diagram of an interactive method provided by an embodiment of the present application. In the embodiment of the present application, the user can interact with the chip design tool through GUI buttons or tool command language (TCL) to control the filtering and emphasis of special signals. The chip design tool can obtain the format of special signals, such as signal name or port type, and Figure 20 All the extracted paths are marked one by one. If there is a special signal in the path, you can choose to filter the path, that is, hide the flying line on the interface corresponding to the path, such as Figure 15 As shown in (b), it helps engineers avoid interference from irrelevant signals and clarify the relationship between valid signals. Optionally, the path can also be emphasized, such as marking the corresponding flying wires of the path with special colors, bolding or highlighting, etc., to help users perform targeted optimization, such as Figure 15 As shown in (c).

[0175] Figure 23 This is a schematic diagram of another chip design result provided in an embodiment of the present application.

[0176] In the embodiment of the present application, the data flow relationship can be adaptively updated after the netlist changes to reflect the latest data flow relationship. Figure 23 (a) is a schematic diagram of the original data flow relationship, where the weight of the data flow relationship between block 2 and block 3 is 10. Figure 24 This is a schematic diagram of another interactive method provided by an embodiment of the present application. The user can delete or add paths between elements through GUI buttons or TCL commands. For example, Figure 23 As shown in (b), the embodiment of the present application deletes the original connection between block 2 and block 3, and adds a new feedthrough path between block 2 and block 3. The new path is as follows Figure 23 As shown in (c), the path weight from block 2 to block 4 is 10, and the path weight from block 4 to block 3 is 10. Figure 23 Figure (d) shows the adaptively updated data flow relationship. The original weight of the data flow relationship between blocks 2 and 4 was 60, and the adaptively updated weight is 60 + 10 = 70. The original weight of the data flow relationship between blocks 3 and 4 was 90, and the adaptively updated weight is 90 + 10 = 100. The adaptive data flow relationship update process is fully automated and does not require the user to select any buttons or execute any TCL scripts.

[0177] The present application also supports restoring the original data flow through TCL commands or GUI buttons, for example, by using the command set_para use_current_dataflow false to restore the original chip design results. The chip design tool provided by this application saves a complete copy of the original data flow relationship, and users can restore the data flow relationship through TCL commands or GUI buttons, supporting users to compare layout quality.

[0178] The above describes the chip design method according to the embodiment of the present application. Figure 25 and Figure 26 The apparatus and device according to the embodiments of the present application are described.

[0179] The embodiment of the present application further provides a computer storage medium in which program instructions are stored. When the program is executed, the program may include: Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 Part or all of the steps of the chip design method in the corresponding embodiment.

[0180] Figure 25 This diagram illustrates an exemplary structure of a computer device 1000 provided in an embodiment of the present application. The computer device 1000 includes an acquisition module 1010, a processing module 1020, and a display module 1030. Acquisition module 1010, processing module 1020, and display module 1030 can be implemented in software, hardware, or a combination of both. Therefore, the computer device 1000 can be an EDA software tool or a related module or device equipped with the tool.

[0181] The acquisition module 1010 is used to obtain the chip design information and netlist information to perform Figure 2 210 in the method, Figure 3 or Figure 6 Some steps.

[0182] Processing module 1020 is used to determine multiple second elements and obtain the first design result of the chip, and execute Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 Some or all of the steps in the method.

[0183] The display module 1030 is used to display the chip design results.

[0184] Figure 26 This is a diagram illustrating another example of the structure of a computer device 1300 provided in an embodiment of the present application. The computer device 1300 includes a processor 1302, a communication interface 1303, and a memory 1304. An example of the computer device 1300 is a computing device, such as a server for performing EDA simulation.

[0185] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 1302. Processor 1302 can be a central processing unit (CPU), or other general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor can be a microprocessor or any conventional processor. During implementation, each step of the above method can be performed by hardware integrated logic circuits or software instructions in processor 1302. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor.

[0186] The memory 1304 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. The nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0187] The processor 1302, the memory 1304 and the communication interface 1303 can communicate with each other via a bus. The memory 1304 stores executable code, and the processor 1302 reads the executable code in the memory 1304 to execute the corresponding method. The memory 1304 may also include an operating system and other software modules required for running processes. The operating system may be LINUX TM , UNIX TM , WINDOWS TM wait.

[0188] For example, the executable code in memory 1304 is used to implement Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 The method shown, the processor 1302 reads the executable code in the memory 1304 to execute Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 The method shown.

[0189] In some embodiments of the present application, the disclosed methods may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of manufacture. Figure 27 Schematically illustrates a conceptual partial view of an example computer program product, arranged in accordance with at least some embodiments presented herein, comprising a computer program for executing a computer process on a computing device. In one embodiment, the example computer program product 1400 is provided using a signal-bearing medium 1401. The signal-bearing medium 1401 may include one or more program instructions 1402 that, when executed by one or more processors, may provide the above-described instructions for executing a computer process. Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 Thus, for example, reference to Figure 2 、 Figure 3 、 Figure 6 、 Figures 9-19 In the embodiment shown in , one or more features thereof may be borne by one or more instructions associated with the signal bearing medium 1401.

[0190] In some examples, signal-bearing medium 1401 may include computer-readable media 1403, such as, but not limited to, a hard drive, a compact disc (CD), a digital video disc (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), etc. In some embodiments, signal-bearing medium 1401 may include computer-recordable media 1404, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, signal-bearing medium 1401 may include communication media 1405, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Thus, for example, signal-bearing medium 1401 may be communicated via a wireless form of communication media 1405 (e.g., a wireless communication medium that complies with the IEEE 802.11 standard or other transmission protocols). One or more program instructions 1402 may be, for example, computer-executable instructions or logic-implemented instructions. In some examples, the aforementioned computing device can be configured to provide various operations, functions, or actions in response to one or more program instructions 1402 communicated to the computing device by computer-readable media 1403, computer-recordable media 1404, and / or communication media 1405. It should be understood that the arrangement described herein is merely for illustrative purposes. Thus, it will be understood by those skilled in the art that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements can be omitted altogether according to the desired result. In addition, many of the described elements can be implemented as discrete or distributed components or in any appropriate combination and position to implement functional entities in conjunction with other components.

[0191] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0193] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0194] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0195] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0196] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0197] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip design method, characterized in that: include: Obtaining chip design information and netlist information, wherein the design information includes a plurality of first elements for chip design, and the netlist information includes connection relationships between the plurality of first elements, wherein the first elements include any one or more of macro cells, ports, standard cells, input / output cells, and intellectual property IP cores; Determining a plurality of second elements according to the design information, the second elements comprising any one or more of a macro cell group, a port group, a standard cell group, a block, a block group, an input / output cell group, and an IP core group; Obtaining a first design result of the chip according to the design information, the netlist information, and the plurality of second elements, where the first design result includes a data flow relationship between a plurality of third elements, and the third elements include the first element or the second element; The first design result is displayed on the interface.

2. The method according to claim 1, characterized in that The first design result also includes any one or more of the weight, number of paths, and path length corresponding to the data flow relationship.

3. The method according to claim 1 or 2, characterized in that The method further comprises: receiving a filtering request input by a user, wherein the filtering request is used to request hiding a portion of the data flow relationship; According to the filtering request, the first design result after being hidden is displayed on the interface.

4. The method according to claim 3, characterized in that The filtering request includes any one or more of special signal filtering, weight filtering, and path length filtering. The special signal filtering is used to indicate the hiding of data flow relationships related to preset signals. The weight filtering is used to indicate the hiding of data flow relationships whose weights are less than a first preset threshold. The path length filtering is used to indicate the hiding of data flow relationships whose path lengths are greater than a second preset threshold.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: receiving an emphasis request input by a user, wherein the emphasis request is used to request highlighting of a portion of the data flow relationship; According to the emphasis request, the first design result after the highlighting is displayed on the interface.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Receive a rollback request input by a user, the rollback request being used to request display of a second design result, where the first design result is a chip design result at a first moment, and the second design result is a chip design result at a second moment, where the second moment is earlier than the first moment; According to the rollback request, the second design result is displayed on the interface.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: receiving a data flow relationship change request input by a user, the data flow relationship change request being used to instruct to add or delete a first path in the first design result, the first path being a path between a fourth element and a fifth element, the fourth element and the fifth element being one of the plurality of third elements; According to the data flow relationship change request, a first data flow relationship is displayed on the interface, where the first data flow relationship is the data flow relationship between the fourth element and the fifth element after the first path is added or deleted.

8. The method according to claim 7, characterized in that The method further comprises: Any one or more of the weight, number of paths, and path length corresponding to the first data flow relationship is displayed on the interface.

9. The method according to any one of claims 1 to 8, characterized in that The value of the first weight is proportional to the number of first paths and inversely proportional to the length of the first path. The first weight is the weight corresponding to the data flow relationship between the sixth element and the seventh element. The first path number is the number of paths between the sixth element and the seventh element. The first path length is the number of registers included in the path between the sixth element and the seventh element. The sixth element and the seventh element are one of the multiple third elements.

10. The method according to any one of claims 1 to 9, characterized in that Obtaining a first design result of the chip according to the design information, the netlist information, and the plurality of second elements includes: constructing a data flow relationship directed graph according to the design information, the netlist information and the plurality of second elements, wherein the data flow relationship directed graph includes connection relationships between the plurality of third elements; The first design result is obtained according to the data flow relationship directed graph.

11. The method according to any one of claims 1 to 10, characterized in that The third element also includes a sub-pseudo module, which is a module obtained by splitting the core area of ​​the chip.

12. A computer device, characterized in that: include: an acquisition module, configured to acquire chip design information and netlist information, wherein the design information includes a plurality of first elements for chip design, and the netlist information includes connection relationships between the plurality of first elements, wherein the first elements include any one or more of macro cells, ports, standard cells, input / output cells, and intellectual property IP cores; a processing module, configured to determine a plurality of second elements according to the design information, wherein the second elements include any one or more of a macro cell group, a port group, a standard cell group, a block, a block group, an input / output cell group, and an IP core group; The processing module is further configured to obtain a first design result of the chip based on the design information, the netlist information, and the plurality of second elements, where the first design result includes a data flow relationship between a plurality of third elements, and the third elements include the first element or the second element; A display module is used to display the first design result on an interface.

13. The device according to claim 12, characterized in that The first design result also includes any one or more of the weight, number of paths, and path length corresponding to the data flow relationship.

14. The device according to claim 12 or 13, characterized in that The acquisition module is further configured to receive a filtering request input by a user, wherein the filtering request is configured to request hiding a portion of the data flow relationship; The display module is further configured to display the first design result after being hidden on the interface according to the filtering request.

15. The device according to claim 14, characterized in that The filtering request includes any one or more of special signal filtering, weight filtering, and path length filtering. The special signal filtering is used to indicate the hiding of data flow relationships related to preset signals. The weight filtering is used to indicate the hiding of data flow relationships whose weights are less than a first preset threshold. The path length filtering is used to indicate the hiding of data flow relationships whose path lengths are greater than a second preset threshold.

16. The device according to any one of claims 12 to 15, characterized in that The acquisition module is further configured to receive an emphasis request input by a user, wherein the emphasis request is configured to request highlighting of a portion of the data flow relationship; The display module is further configured to display the first design result after the highlighting on the interface according to the emphasis request.

17. The device according to any one of claims 12 to 16, characterized in that The acquisition module is further configured to receive a rollback request input by a user, wherein the rollback request is configured to request display of a second design result, where the first design result is a chip design result at a first moment, and the second design result is a chip design result at a second moment, where the second moment is earlier than the first moment; The display module is further used to display the second design result on the interface according to the rollback request.

18. The device according to any one of claims 12 to 17, characterized in that The acquisition module is further configured to receive a data flow relationship change request input by a user, the data flow relationship change request being used to instruct to add or delete a first path in the first design result, the first path being a path between a fourth element and a fifth element, the fourth element and the fifth element being one of the plurality of third elements; The display module is further configured to display a first data flow relationship on the interface according to the data flow relationship change request, where the first data flow relationship is the data flow relationship between the fourth element and the fifth element after adding or deleting the first path.

19. The device according to claim 18, characterized in that The display module is further used to display any one or more of the weight, path number, and path length corresponding to the first data flow relationship on the interface.

20. The device according to any one of claims 12 to 19, characterized in that The value of the first weight is proportional to the number of first paths and inversely proportional to the length of the first path. The first weight is the weight corresponding to the data flow relationship between the sixth element and the seventh element. The first path number is the number of paths between the sixth element and the seventh element. The first path length is the number of registers included in the path between the sixth element and the seventh element. The sixth element and the seventh element are one of the multiple third elements.

21. The device according to any one of claims 12 to 20, characterized in that The processing module is specifically used to: constructing a data flow relationship directed graph according to the design information, the netlist information and the plurality of second elements, wherein the data flow relationship directed graph includes connection relationships between the plurality of third elements; The first design result is obtained according to the data flow relationship directed graph.

22. The device according to any one of claims 12 to 21, characterized in that The third element also includes a sub-pseudo module, which is a module obtained by splitting the core area of ​​the chip.

23. A computer device, characterized in that: include: A processor, wherein the processor is configured to be coupled to a memory, read and execute instructions and / or program codes in the memory, so as to perform the method according to any one of claims 1 to 11.

24. A computer-readable medium, characterized in that The computer-readable medium stores a computer program code, and when the computer program code is run on a computer, the computer is caused to perform the method according to any one of claims 1 to 11.

25. A computer program product, characterized in that The computer program product comprises a computer program code, which, when run on a computer, causes the computer to perform the method according to any one of claims 1 to 11.

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