A routable linear layout method based on reinforcement learning

Abstract

The present application relates to a routable layout method based on reinforcement learning, which combines a macro cell layout model and a congestion prediction model, introduces a routable layout evaluation mechanism in the layout stage to improve the manufacturability and routing success rate of chip design. Specifically, it includes: using a reinforcement learning driven layout model to perform macro cell layout; using a congestion prediction model to predict the congestion of the layout result; extracting three types of features, macro area, routing density (RUDY) and pin density (Pin RUDY), after each layout iteration, normalizing and combining them into a three-channel feature map as the input of the congestion prediction model; dynamically adjusting the reward function of reinforcement learning according to the prediction result to guide the layout model to avoid high congestion areas. This method can significantly improve the realizability of the layout scheme in the subsequent routing stage, reduce rework, reduce design cost, and has strong engineering practicability and expandability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic design automation, and specifically relates to a routable layout method based on reinforcement learning. BACKGROUND

[0002] With the increasing complexity of integrated circuit (IC) design, especially in the design of modern high-performance computing chips, layout optimization and routing have become crucial steps. Traditional integrated circuit layout and routing methods rely on heuristic algorithms and rule-based methods, although these methods can ensure the manufacturability and performance of the design to some extent, but in the face of increasingly complex design requirements, it is often difficult to effectively predict congestion areas, resulting in serious performance bottlenecks in the routing stage.

[0003] Existing layout optimization algorithms based on deep reinforcement learning usually do not fully consider the problem of routing congestion in the macro cell layout stage. In actual integrated circuit design, routing congestion is one of the key factors affecting circuit performance and manufacturability. Routing congestion occurs in areas where routing resources cannot meet routing demands, which can lead to increased routing delay, decreased signal integrity, and even routing failure. Ignoring the problem of routing congestion may result in problems in the subsequent detailed routing stage of the layout scheme generated by deep reinforcement learning, which cannot meet design requirements, and even needs to return to the upstream for layout reconstruction, prolonging the design cycle and increasing the design cost.

[0004] To solve the above problems, introducing routability analysis in the integrated circuit layout process has become one of the key ways to improve overall design quality. Routability refers to whether the subsequent routing stage can be successfully completed, whether there is a risk of resource conflict or performance degradation under the current layout conditions. By introducing a congestion prediction mechanism in the layout stage, potential congestion hot spot areas are identified in advance, and the macro cell position is optimized, which can significantly reduce the routing failure rate and rework probability, improve layout quality and design convergence efficiency. Especially in high-density and high-complexity design scenarios, routability-driven layout optimization not only can alleviate the pressure on routing resources, but also can improve timing convergence, reduce power consumption and area waste. Although there are several layout optimization methods in existing technologies that introduce routability information, most of the existing methods rely on manually set heuristic rules, lack deep modeling capabilities for local spatial features and routing demand density, and are difficult to accurately respond to congestion hot spots in actual complex layout environments, with limited generalization ability.

[0005] Therefore, there is an urgent need for a new routability optimization method to overcome the deficiencies of existing technologies. SUMMARY

[0006] The purpose of the present application is to solve the problems of the prior art, and provide a routable layout method based on reinforcement learning. The method combines the adaptive optimization capability of reinforcement learning and the congestion prediction model, and can identify and avoid possible congestion areas in the layout stage, thereby reducing conflicts in the routing stage and improving overall design efficiency.

[0007] To solve the above problems, the present application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a routable layout method based on reinforcement learning, comprising the following steps:

[0009] S1, a layout model based on reinforcement learning is constructed to layout the macro units of the chip and obtain a preliminary layout result;

[0010] S2, the position information of the macro units is obtained and layout features are extracted according to the position information of the macro units, the layout features including Macro Region features, RUDY (Rectangular uniform wire density, wire resource demand index rectangular area line density) features and Pin RUDY (rectangular area pin line density map) features;

[0011] S3, the layout features are preprocessed;

[0012] S4, a congestion prediction model is constructed, the preprocessed layout features are input, and a prediction result of the layout congestion is obtained;

[0013] S5, the congestion prediction model is embedded into the layout model based on reinforcement learning, and the layout result is updated according to the prediction result;

[0014] S6, steps S2 to S5 are repeated until the layout model meets the convergence condition, and the final layout result of the chip is output.

[0015] Further, the congestion prediction model is a lightweight neural network model for predicting the congestion situation of chip layout; the model is based on a U-Net structure and includes an encoder and a decoder, wherein:

[0016] The encoder receives three-channel feature maps including Macro Region features, RUDY features and Pin RUDY features as input to fully embody the spatial distribution information of the layout data, which includes four cascaded down-sampling modules, each of which is composed of a convolution layer and a max-pooling layer, for gradually extracting and compressing the spatial information of the input feature maps; at the end of the encoder, an Inception module is introduced, which extracts different features through multi-branch parallel convolution operations and splices the outputs of each branch to enhance the diversity of feature representation and the recognition ability of the model to local and global congestion patterns. The decoder includes four groups of cascaded up-sampling modules, each of which includes an up-sampling layer, a convolution activation module and a feature fusion layer, and the convolution activation module includes a convolution layer and a PReLU activation function. Each up-sampling module first performs an up-sampling operation to gradually restore the spatial resolution of the feature map, then extracts high-level semantic information through the convolution layer and the PReLU activation function, and performs feature fusion to integrate the corresponding layer features from the encoder. After all the structure cascades are completed, a convolution operation is performed on the multi-channel feature map to compress it into a single-channel output for generating the final congestion prediction map.

[0017] The congestion prediction model can effectively guide the timely prediction and optimization of congestion in the chip layout process.

[0018] Further, after the macro unit completes the initial layout, feature maps representing the layout structure and wiring requirements are extracted, including Macro Region feature maps, RUDY feature maps and Pin RUDY feature maps, each of which is a 256x256 two-dimensional matrix.

[0019] Specifically, obtaining the layout features includes the following steps:

[0020] S201: Obtain the layout result information of all macro units, including the coordinates of the lower left corner of each macro unit and its size information.

[0021] S202: According to the layout result information of the macro unit, first calculate the bounding box of each wire net in the layout plane according to the position of the pin connected by the wire net; estimate the wiring resource demand of the wire net for the grid unit according to the overlapping relationship between the bounding box and the grid, and generate the RUDY feature map and the Pin RUDY feature map.

[0022] S203: Traverse all macro units, and according to their positions and sizes on the chip plane, mark the grid units occupied by the macro units as 1 and the unoccupied areas as 0 to form the Macro Region feature map.

[0023] Further, the preprocessing of the layout features includes normalization and splicing, specifically including the following steps:

[0024] S301: Min-Max normalization is performed on the Macro Region feature map, the RUDY feature map and the Pin RUDY feature map obtained in S2, and the Min-Max normalization calculation formula is as follows:

[0025]

[0026] wherein is the feature value of a certain position in the original feature map to be normalized, is the maximum value of all positions in the feature map, is the minimum value of all positions in the feature map, is the normalized feature value.

[0027] Specifically, for the Macro Region feature map, is the label value (0 or 1) indicating whether the pixel is occupied by a macro unit; for the RUDY feature, is the line mesh wiring demand density estimation value corresponding to the current pixel position; for the Pin RUDY feature, is the estimation value of the pin wiring pressure at the position.

[0028] Through the normalization operation, the value range of the three feature maps is unified in the interval [0, 1], which facilitates the unified processing and training of the subsequent prediction model.

[0029] S302: The three normalized two-dimensional images are spliced to form a three-channel image, and the image size is , and the splicing method is as follows:

[0030]

[0031] wherein, represents the grid in the row and the column, the first channel is the macro area occupation map, the second channel is the wiring density map (RUDY), and the third channel is the pin density map (Pin RUDY), is the normalized macro area feature, is the normalized RUDY feature, is the normalized Pin RUDY feature. is the combined three-channel feature map.

[0032] Further, step S4 includes the following steps:

[0033] S401: input the three-channel feature map generated in step S3 into the loaded congestion prediction model, perform model forward inference, and obtain a two-dimensional congestion distribution map corresponding to the current layout. The prediction map expresses the congestion degree of each region on the layout plane in a numerical manner, and the higher the numerical value, the more nervous the wiring resources.

[0034] S402: count the congestion index in the entire two-dimensional congestion distribution map as the performance evaluation index of the current layout scheme in the congestion dimension, that is, the predicted total congestion amount.

[0035] Further, step S5 includes the following steps:

[0036] S501: embed the congestion prediction model into the layout model, and dynamically adjust the reinforcement learning reward function based on the predicted total congestion amount: to guide the macro cell layout to evolve in the direction of simultaneously optimizing the line length and the congestion, a joint reward function combining the wiring length and the predicted congestion amount is constructed. The specific form is:

[0037]

[0038] wherein, is a congestion penalty coefficient, is the total congestion amount output by the congestion prediction model, is a reward item based on line length optimization.

[0039] S502: feed back the updated comprehensive reward to the reinforcement learning training process to guide the optimization direction of the layout strategy network. The reward design can guide the layout model to tend to place macro cells in low congestion areas in subsequent iterations, thereby gradually optimizing the congestion distribution in the layout result, and realizing the collaborative optimization of layout quality and routability.

[0040] In a second aspect, the present application provides a chip layout system for implementing the reinforcement learning-based routability layout method, comprising the following modules:

[0041] A preliminary layout module performs preliminary layout on the macro cells of the chip;

[0042] A feature extraction module extracts layout features from the position information of the macro cells, and then performs preprocessing;

[0043] A layout adjustment module processes the preprocessed layout features using a layout model embedded with a congestion prediction model, and outputs an optimized layout.

[0044] In a third aspect, the present application provides an electronic device comprising a processor and a memory, wherein the memory stores machine executable instructions executable by the processor, and the processor executes the machine executable instructions to implement the method.

[0045] In a fourth aspect, the present application provides a machine-readable storage medium storing machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method.

[0046] Compared with the prior art, the present application has the beneficial effects that:

[0047] The reinforcement learning layout optimization method with routability can embed a congestion prediction model into the layout decision-making process, extract spatial occupation features, routing density features and pin distribution features in real time under the layout state, construct a three-channel routability feature map, and use a lightweight neural network model for congestion prediction. By obtaining the prediction results in time after each round of layout iteration, and introducing the predicted congestion degree into the reward function of the reinforcement learning layout strategy as a dynamic penalty term, the layout model gradually avoids congestion areas during the learning process, and improves the routability of the layout scheme.

[0048] The method can introduce a routability index with higher prediction accuracy during the layout training process, and feed back the prediction results to the reinforcement learning process as an additional penalty term for reward function design, thereby guiding the model to actively avoid potential congestion areas, realizing a layout strategy friendly to the backend routing. Not only does it effectively improve the realizability of the layout results in the subsequent routing stage, reducing the risk of routing failure and rework, but it also realizes the unification of line length optimization and congestion control, significantly improving the intelligence and overall design quality of the layout stage. At the same time, since the congestion prediction model and the layout strategy module are decoupled, they have good generality and scalability, and can adapt to integrated circuit design tasks of different scales and types, having wide engineering application value. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The reinforcement learning routability layout optimization method provided by the present application is shown in the flowchart.

[0050] Figure 2 The congestion prediction model structure provided by the present application is shown in the schematic diagram. DETAILED DESCRIPTION

[0051] The principles and features of the reinforcement learning routability layout optimization method provided by the present application are further described in detail below in conjunction with the accompanying drawings, which are only used to explain the present application and not to limit the scope of the present application. It should be noted that the drawings are greatly simplified and use non-precise proportions, only to facilitate and clarify the purpose of explaining the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used.

[0052] The application provides a routing linear layout optimization method based on reinforcement learning, a scheme flowchart of which is shown in the figure. Figure 1 First, the current layout result is obtained according to the layout model, and the feature processing is performed on the layout result to extract the RUDY, Pin RUDY and Macro Region features. Then, the extracted features are input into the pre-trained congestion prediction model to generate the corresponding congestion map. The congestion map is transmitted to the layout model as feedback information, and the layout model adjusts the macro unit position based on the reinforcement learning strategy to reduce the congestion area and optimize the wire length. The above process is continuously performed in an iterative manner until the reinforcement learning model determines convergence. Finally, the optimized layout result is output, and the layout result is evaluated by using the evaluation index to realize the collaborative optimization of the wire length and the congestion.

[0053] The specific embodiments of the application are described in detail below:

[0054] S1, a layout model based on reinforcement learning is constructed to perform layout on the macro units of a chip to obtain a preliminary layout result;

[0055] S2, the position information of the macro units is obtained, and the layout features are extracted according to the position information of the macro units, including the Macro Region feature, the RUDY (Rectangular uniform wire density, wire density index rectangular area) feature and the Pin RUDY (rectangular area pin wire density map) feature;

[0056] S3, the layout features are preprocessed;

[0057] S4, a congestion prediction model is constructed, the preprocessed layout features are input, and the prediction result of the layout congestion is obtained;

[0058] S5, the congestion prediction model is embedded into the layout model based on reinforcement learning constructed in step S1, and the layout result is updated according to the prediction result;

[0059] S6, steps S2 to S5 are repeated, after each layout iteration of the layout model, the feature map of the current layout is obtained and input into the model to predict the congestion of the current layout;

[0060] According to the congestion degree predicted by the model, the reward function of the reinforcement learning is adjusted to guide the model to avoid the high congestion area in the subsequent layout, so as to optimize the congestion in the layout process, until the layout model meets the convergence condition, and the final layout result of the chip is output.

[0061] After the initial layout of the macrocell is completed, feature maps representing the layout structure and routing requirements are extracted, including: Macro Region feature map, RUDY feature map and Pin RUDY feature map, each of which is a 256×256 two-dimensional matrix.

[0062] (1) The Macro Region feature map is a two-dimensional heatmap, the purpose of which is to mark which locations in the chip layout area are occupied by macro cells. Essentially, it performs grid-based discretization on the macro cells, dividing the chip canvas into... The grid in which The second part represents the second part of the two-dimensional grid. line, number Columns (i=1,2,…,w; j=1,2,…,h) are used to generate a two-dimensional matrix. Each pixel value in the generated two-dimensional matrix represents whether the position is occupied by a macrocell. If it is, it is a region covered by a macrocell. If it is a region not covered by macrocells, .That

[0063]

[0064] (2) RUDY feature map is a two-dimensional grid map based on net geometry information. Its purpose is to estimate the wiring pressure or wiring density at each location in the layout area by analyzing the size of the bounding box of the net connection area without performing actual wiring.

[0065] A net is a set of pins that need to be connected to each other in a circuit, representing the propagation path of an electrical signal.

[0066] A bounding box is the smallest rectangular area on the chip layout plane that encloses all the pins of a net. Its purpose is to estimate the approximate range of influence of the net or the area requiring routing.

[0067] Assume that the network has multiple pins, and their location coordinates are:

[0068]

[0069] The bounding box is then defined as:

[0070]

[0071]

[0072] The width and height of the bezel box are:

[0073]

[0074] This rectangular region is the bounding box of the net.

[0075] Based on the net and the bounding box, RUDY can be further calculated. RUDY is used to estimate the wiring resource demand density of each region without actual wiring. Its core basis is to proportionally map the bounding box area of the net to the grid cell covered by it.

[0076] First, calculate the overlapping area of the net k and the grid cell :

[0077]

[0078] where represents the maximum and minimum coordinate values of the bounding box of the kth net (Net) in the x direction; represents the starting and ending coordinates of the grid cell (i, j) in the x direction; represents the maximum and minimum coordinate values of the bounding box of the kth net (Net) in the y direction; represents the starting and ending coordinates of the grid cell (i, j) in the y direction.

[0079] The area of the grid cell is:

[0080]

[0081] The RUDY value is:

[0082]

[0083] where represents the bounding box width (x direction length) of the kth net; represents the bounding box height (y direction length) of the kth net.

[0084] (3) Pin RUDY feature map is a two-dimensional grid map constructed based on pin distribution density, mainly used to estimate the pin aggregation situation of local area in the chip layout stage, so as to assist in identifying potential wiring congestion areas.

[0085] Similar to RUDY, Pin RUDY also estimates the pin density generated by each pin to the grid cell it belongs to without actual wiring through the bounding box geometric information of the net.

[0086] In the calculation process, first determine the network k to which the pin belongs, and obtain the bounding box boundary information of the network:

[0087]

[0088] in Represents the maximum and minimum coordinates of the bounding box of the k-th net in the x-direction; This represents the maximum and minimum coordinates of the bounding box of the k-th net in the y-direction.

[0089] The width and height of the bounding box are then calculated as follows:

[0090]

[0091] in This represents the width (x-direction length) of the bounding box of the k-th mesh. This represents the height (y-direction length) of the bounding box of the k-th mesh.

[0092] Each pin projects to its corresponding grid cell. When applying the weighted values, the Pin RUDY values ​​of the corresponding network are evenly weighted across the grid cell. The basic formula for Pin RUDY is as follows:

[0093]

[0094] Ultimately, the contributions of all pins are accumulated in a two-dimensional grid to form a continuously numerical two-dimensional Pin RUDY feature map.

[0095] This image can be compared with RUDY feature maps and macro regions. Figure 1 The features are used as three-channel image features and input into the congestion prediction model for congestion prediction.

[0096] S2 includes the following steps:

[0097] S201: After completing a round of layout optimization, obtain the layout result information of all macro cells, including the coordinates of the lower left corner of each macro cell and its size information.

[0098] S202: Based on the macrocell layout results, firstly, calculate the bounding box of each net on the layout plane according to the position of the pins connected to each net; based on the overlap relationship between the bounding box and the mesh, estimate the routing resource requirements of the net for the mesh cells, and generate RUDY feature map and Pin RUDY feature map.

[0099] S203: Traverse all macrocells, and based on their position and size on the chip plane, mark the grid cells they occupy as 1 and the unoccupied areas as 0, forming a Macro Region feature map.

[0100] Optionally, in the reinforcement learning-based routable linear layout optimization method, the third step includes the following sub-steps:

[0101] S301: Min-Max normalization is performed on the Macro Region, RUDY and Pin RUDY feature maps calculated in step S2, and the Min-Max normalization calculation formula is:

[0102]

[0103] wherein is the feature value of a certain position in the original feature map to be normalized, is the maximum value of all positions in the feature map, is the minimum value of all positions in the feature map, is the normalized feature value.

[0104] Specifically, for the Macro Region feature map, is a label value (0 or 1) indicating whether the pixel is occupied by a macro cell; for the RUDY feature, is the wire demand density estimation value corresponding to the current pixel position; for the Pin RUDY feature, is the estimation value of the pin routing pressure at the position.

[0105] Through the normalization operation, the value range of the three feature maps is unified in the interval [0, 1], which facilitates the unified processing and training of the subsequent prediction model.

[0106] S302: The three normalized two-dimensional images are spliced to form a three-channel image, and the image size is , and the splicing method is as follows:

[0107]

[0108] wherein, represents the grid in the row and the column, the first channel is the macro region occupation map, the second channel is the wire density map (RUDY), and the third channel is the pin density map (Pin RUDY). is the combined three-channel feature map.

[0109] In step S4, the architecture of the congestion prediction model is as shown in Figure 2 .

[0110] Optionally, in the reinforcement learning-based routable linear layout optimization method, the fifth step includes the following sub-steps:

[0111] S501: input the three-channel feature map generated in step S4 into the loaded congestion prediction model, perform forward inference of the model, and obtain a two-dimensional congestion distribution map corresponding to the current layout. The prediction map expresses the congestion degree of each region on the layout plane in a numerical manner, and the higher the value, the more nervous the wiring resources.

[0112] S502: count the congestion indicators in the entire predicted congestion map as the performance evaluation indicator of the current layout scheme in the congestion dimension, i.e., the predicted total congestion amount.

[0113] S503: dynamically adjust the reinforcement learning reward function based on the congestion prediction result. To guide the macro cell layout to evolve towards the direction of simultaneously optimizing the line length and the congestion, a joint reward function that combines the wiring length and the predicted congestion amount is constructed, and the specific form is:

[0114]

[0115] wherein, is a congestion penalty coefficient, is the total congestion amount output by the congestion prediction model, is the reward item based on the line length optimization.

[0116] Further, is a congestion penalty coefficient, used to regulate the relative weight of the congestion penalty item in the comprehensive reward function. Specifically, since is usually in the order of , and is usually in the order of , to avoid the dominance of the change of one item due to the inconsistency of the scale, it is necessary to reasonably set to balance the influence of the two items.

[0117] In this embodiment, is set by using the following strategy:

[0118] First, the values of and in the first 10 rounds are counted, and the average values of and are calculated based on the values in the first 10 rounds, which are defined as and , respectively. is defined as follows:

[0119]

[0120] This setting ensures that in the reward function, and have comparable orders of magnitude, so as to realize the coordinated trade-off between connection optimization and congestion control in the training process, and improve the layout quality and routability.

[0121] S505: Embed the comprehensive reward into the reinforcement learning training process to guide the optimization direction of the layout strategy network. The reward design can guide the layout model to tend to place macro cells in low congestion areas in subsequent iterations, thereby gradually optimizing the congestion distribution in the layout result and achieving the coordinated optimization of layout quality and routability.

[0122] Further, the general reinforcement learning convergence condition is usually defined as: when the agent's cumulative reward (Reward) reaches a certain set threshold or the reward curve tends to be stable (such as the standard deviation of the change in Reward tends to zero) in a certain number of consecutive training rounds, it is considered that the strategy has converged. At the same time, some methods also detect the change in behavior strategy network output or the decline trend of performance indicators (such as success rate, loss value) to determine the convergence state.

[0123] In this embodiment, a comprehensive convergence determination method based on reward statistics and target function index trend is proposed in combination with the characteristics of the layout optimization task, which is defined as follows:

[0124] Take the training results of the last 10 consecutive rounds as a sliding window; record the comprehensive reward (Reward), half perimeter wire length index (HPWL), and congestion prediction total amount (TotalCongestion) corresponding to the layout quality after each training round ends; if the reward value fluctuation stability is met, that is, the standard deviation of Reward in the last 10 consecutive rounds is less than a set threshold , the model is determined to have converged.

[0125] Table 1 lists the half perimeter wire length and congestion total amount comparison results of 8 benchmark circuits under two layout processes with or without integrating the congestion prediction module. The results show that after integrating the congestion prediction module, the total congestion of the circuit is significantly reduced, and the half perimeter wire length of some circuits is also improved, verifying the effectiveness of the method in improving the layout routability.

[0126] Table 1

[0127]

[0128] The above content is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be considered as falling within the protection scope of the present application.

Claims

1. A routable floorplanning method based on reinforcement learning, characterized in that, The method comprises the following steps: S1, constructing a layout model based on reinforcement learning, performing layout on macro units of a chip to obtain a preliminary layout result; S2, obtaining position information of the macro units and extracting layout features, the layout features comprising macro area features, wiring resource demand index rectangular area line density features and rectangular area pin line density map features; S3, preprocessing the layout features; S4, constructing a congestion prediction model, inputting the preprocessed layout features to obtain a prediction result of the layout congestion; the congestion prediction model is based on a U-Net structure and comprises an encoder and a decoder, wherein: The encoder comprises four cascaded downsampling modules, each of which is composed of a convolution layer and a max-pooling layer, and a PReLU activation function is connected after each convolution; an Inception module is introduced at the end of the encoder to extract different features through multi-branch parallel convolution operation, and the outputs of the branches are spliced and input into the decoder; The decoder comprises four groups of cascaded upsampling modules, each of which comprises an upsampling layer, a convolution activation module and a feature fusion layer, the convolution activation module comprising a convolution layer and a PReLU activation function; after the last feature fusion, a prediction result is output; S5, embedding the congestion prediction model into the layout model based on reinforcement learning, and updating the layout result according to the prediction result; specifically comprising the following steps: S501: embedding the congestion prediction model into the layout model, dynamically adjusting the reinforcement learning reward function based on the predicted total congestion: to guide the macro unit layout to evolve in the direction of optimizing the line length and congestion, a joint reward function combining the wiring length and the predicted congestion is constructed, expressed as: ； wherein β is a congestion penalty coefficient, is the total congestion amount output by the congestion prediction model, is a reward term based on line length optimization; S502: feeding the updated comprehensive reward back to the reinforcement learning training process to guide the optimization direction of the layout strategy network; S6, repeating steps S2 to S5 until the layout model meets the convergence condition, and outputting the final layout result of the chip.

2. The reinforcement learning based routable floorplanning method of claim 1, wherein, Step S2 comprises the following steps: S201: obtaining layout result information of all macro units, including the lower left corner coordinates and size information of each macro unit; S202: according to the layout result information of the macro units, first calculate the bounding box of each wire net in the layout plane according to the position of the connected pins; estimate the wiring resource demand of the wire net to the grid unit according to the overlapping relationship between the bounding box and the grid, and generate the wiring resource demand index rectangular area line density feature and the rectangular area pin line density map feature; S203: traversing all macro units, according to their positions and sizes on the chip plane, marking the grid units occupied by the macro units as 1 and the unoccupied areas as 0 to form the macro area features.

3. The reinforcement learning based routable floorplanning method of claim 1, wherein, The preprocessing in step S3 comprises normalization and splicing to obtain a three-channel feature map containing the wiring resource demand index rectangular area line density feature and the rectangular area pin line density map feature.

4. The reinforcement learning based routable floorplanning method of claim 1, wherein, Step S4 comprises the following steps: S401: inputting the three-channel feature map into the loaded congestion prediction model to perform forward inference of the model and obtain a two-dimensional congestion distribution map corresponding to the current layout; S402: count the congestion index in the whole two-dimensional congestion distribution map as the performance evaluation index of the current layout scheme in the congestion dimension, i.e. the predicted total congestion amount.

5. A chip placement system implementing the routable placement method based on reinforcement learning according to any one of claims 1-4, characterized in that, The method comprises the following modules: A preliminary layout module, which performs preliminary layout on the macro units of the chip; A feature extraction module, which extracts layout features from the position information of the macro units and then performs preprocessing; A layout adjustment module, which processes the preprocessed layout features by using a layout model embedded with a congestion prediction model and outputs the optimized layout.

6. An electronic device, comprising: The processor executes the machine executable instructions to implement the method according to any one of claims 1-4.

7. A machine-readable storage medium, characterized in that, The machine readable storage medium stores machine executable instructions, which, when called and executed by the processor, cause the processor to implement the method according to any one of claims 1-4.

Images