Power device module and preparation process thereof

Abstract

The invention relates to the technical field of power electronic devices, in particular to a power device module and a preparation process thereof. The preparation process comprises the following steps: S1, welding a chip and a carrier to obtain a chip module; s2, carrying out plastic package molding process treatment on the chip module to obtain a chip module package body; s3, carrying out lamination and lamination processing on the chip module packaging body to obtain a core board; and S4, performing circuit connection processing on the core board to obtain the power device module. Depending on the rigidity of the carrier, the chip is not easy to deform and break when bearing external pressure; based on the heat capacity performance of the carrier, when the chip is impacted by short-time large current, heat can be quickly dissipated through the carrier. And the copper-clad insulating substrate is used as a carrier, so that the insulating effect between the chip and the external conductor is ensured, and the heat dissipation effect of the power device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic devices, and in particular relates to a power device module and a preparation process thereof. Background Art

[0002] With the maturity of third-generation wide-bandgap semiconductor technology based on wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN), the application scenarios of semiconductor power devices are becoming increasingly diverse. Existing semiconductor power device packaging processes typically first create a chip current loop using bonding wires, copper clips, and soldering. The connected power device module is then injection molded or potted with adhesive. Existing power device modules suffer from high stray inductance. For example, in automotive and power supply applications, the inductance of existing power device modules ranges from 5 to 15 nH.

[0003] In addition, the industry has also proposed a solution for embedded power devices, which is to stack the power chip and the PCB circuit board, realize circuit connection through the PCB circuit, and eliminate the use of binding wires.

[0004] The currently known process for embedded power devices involves placing the core layer of the chip directly as a layer of the PCB during production, and then embedding it into the PCB through a PCB lamination process. Due to the fragility of the chip, large power chips are prone to breakage. To avoid damage to the chip during the lamination process, one solution is to use Infineon Technologies' S-cell technology (chip soldered to a copper substrate). However, after the chip is placed in the core layer for lamination, this solution requires the application of an insulating thermal film (thermal conductivity coefficient 8-15W / (m·K)) on the bottom of the chip for insulation. This solution has the problem of high thermal resistance. Summary of the Invention

[0005] In view of the above problems, the present invention provides a process for preparing a power device module, the process comprising:

[0006] S1. Solder the chip to the carrier to obtain a chip module;

[0007] S2, performing a plastic encapsulation molding process on the chip module to obtain a chip module package;

[0008] S3, laminating and pressing the chip module package to obtain a core board;

[0009] S4. Perform circuit connection processing on the core board to obtain a power device module.

[0010] Furthermore, the carrier is a copper-clad insulating substrate, comprising an upper metal layer, an insulating layer and a lower metal layer stacked in sequence;

[0011] The insulating layer can be made of a plate with good insulation and thermal conductivity; the upper metal layer and the lower metal layer can be made of copper.

[0012] Furthermore, welding the chip to the carrier includes:

[0013] One side surface of the chip is welded to the first metal surface on the carrier, and the signal terminal of the chip arranged on the side surface is electrically connected to the first metal surface; the other side surface of the chip and the second metal surface on the carrier are located in the same plane; wherein the first metal surface and the second metal surface are electrically connected.

[0014] Furthermore, a mounting groove matching the thickness of the chip is dug on the side of the upper metal layer away from the insulating layer; one side of the chip is welded to the bottom of the mounting groove, and the signal terminal on the side of the chip is electrically connected to the bottom of the mounting groove;

[0015] Alternatively, a boss having the same thickness as the chip is integrally formed on the side of the upper metal layer away from the insulating layer; the side of the chip is welded to the area of ​​the upper metal layer on the side away from the insulating layer except for the boss, and the signal terminal of the chip on the side is electrically connected to the upper metal layer; the other side of the chip and the top surface of the boss are located in the same plane;

[0016] Alternatively, a raised copper sheet with the same thickness as the chip is welded on the side of the upper metal layer away from the insulating layer; one side of the chip is welded to the area on the side of the upper metal layer away from the insulating layer except for the raised copper sheet, and the signal terminal on the side of the chip is electrically connected to the upper metal layer; the other side of the chip and the top surface of the raised copper sheet are located in the same plane.

[0017] Furthermore, the plastic encapsulation process includes: pouring plastic encapsulation material on the periphery of the chip module, plastic encapsulating the outside of the chip module to form a first plastic encapsulation body, and insulating and encapsulating the internal chip module.

[0018] Furthermore, during the plastic encapsulation process, the upper surface of the chip module package is made higher than the upper surface of the chip module, or is coplanar with the upper surface of the chip module.

[0019] Furthermore, during the plastic encapsulation process, the lower surface of the chip module is made coplanar with the lower surface of the chip module package.

[0020] Furthermore, laminating and pressing the chip module package includes:

[0021] S31. The chip module package is used as the core layer of the PCB. One or more metal films are stacked on the side of the board near the chip according to functional requirements. PP semi-cured films are laid between each metal film and between the metal film and the PCB core layer.

[0022] S32, performing a pressing process to manufacture a core board containing power devices.

[0023] Furthermore, before laminating and pressing the chip module package, the chip module package can be embedded into a groove hollowed out of the initial core board, and the initial core board and the chip module package as a whole serve as the core layer of the PCB.

[0024] The present invention also provides a power device module, which is prepared by the above preparation process.

[0025] The beneficial effects of the present invention are:

[0026] 1. The rigidity of the carrier prevents the chip from deforming or breaking when subjected to external pressure. Due to the carrier's thermal capacity, the chip can quickly dissipate heat when subjected to short-term, high-current surges. Furthermore, the use of a copper-clad insulating substrate as the carrier ensures insulation between the chip and external conductors while also improving the heat dissipation of the power device.

[0027] 2. The lower surface of the chip module is the lower surface of the carrier. Since the lower surface of the carrier can be directly connected to the heat sink, the heat dissipation effect of the power device module can be improved.

[0028] 3. The power device module provided by the present invention can be used as a single-tube power device, enriching its application scenarios and reducing its usage requirements. The single-tube power device produced by the present invention through a plastic encapsulation process is smaller than a single tube in a conventional TO247 or T-PACK package, reducing current conduction losses and improving the power density of integrated applications.

[0029] 4. In the PCB circuit board manufacturing process provided by the present invention, the first plastic package can provide good protection for the chip inside during the lamination process, and the requirements for the process environment during the subsequent PCB pressing process are greatly reduced, which has a great positive effect on ensuring the yield of the module.

[0030] 5. By adding bosses or raising the copper foil on the upper metal layer, or by creating a mounting slot for the power chip in the upper metal layer, the height of the metal vias between the external circuit and the chip module can be reduced in subsequent processes. This prevents the problem of copper-cladding plating solution due to the excessive size of some metal vias during subsequent electroplating. Ensuring that all metal vias in the power device module are of the same or similar height reduces the difficulty of the electroplating process and improves the yield rate.

[0031] 6. Insulating and encapsulating the exposed conductive structure of the power device module through the plastic encapsulation process is easier to implement and has lower cost than ensuring the creepage distance by adjusting the circuit solution.

[0032] 7. In the power device module preparation process provided by the present invention, multiple chip modules can be simultaneously subjected to a plastic encapsulation process to obtain a chip module package containing multiple chip modules; multiple chip module packages can also be simultaneously laminated and pressed to obtain a core board containing multiple chip module packages. The power device module provided by the present invention can include multiple chip modules or multiple chip module packages, thereby constructing various series and parallel structures, forming a power device module with rich and diverse power functions.

[0033] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A flow chart showing a process for preparing a power device module according to an embodiment of the present invention is shown;

[0036] Figure 2 A schematic structural diagram of a chip module according to an embodiment of the present invention is shown;

[0037] Figure 3 A schematic structural diagram of a copper-clad insulating substrate according to an embodiment of the present invention is shown;

[0038] Figure 4 A schematic structural diagram showing a chip installed in a mounting groove on a copper-clad insulating substrate according to an embodiment of the present invention is shown;

[0039] Figure 5 A schematic structural diagram of a copper-clad insulating substrate with bosses integrally formed on an upper metal layer according to an embodiment of the present invention is shown;

[0040] Figure 6 A schematic structural diagram of a copper-clad insulating substrate with a heightened copper foil welded on an upper metal layer according to an embodiment of the present invention is shown;

[0041] Figure 7 A schematic structural diagram of plastic encapsulation of a chip module according to an embodiment of the present invention is shown;

[0042] Figure 8 A schematic structural diagram showing the corresponding process steps of a power device module according to an embodiment of the present invention is shown;

[0043] Figure 9 A schematic diagram showing the structure of metal vias constructed on a chip module according to an embodiment of the present invention is shown;

[0044] Figure 10 A schematic structural diagram of a functional circuit according to an embodiment of the present invention is shown;

[0045] Figure 11 A schematic structural diagram of a single-tube power device according to an embodiment of the present invention is shown.

[0046] In the figure: 1-chip; 2-copper-clad insulating substrate; 3-upper metal layer; 301-mounting slot; 302-boss; 303-heightened copper foil; 4-insulating layer; 5-lower metal layer; 6-first plastic package; 7-mold; 8-metal via; 9-functional circuit; 901-first external circuit; 902-second external circuit; 903-third external circuit; 10-circuit layer; DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0048] The embodiment of the present invention provides a process for preparing a power device module, such as Figure 1 As shown, the preparation process includes:

[0049] S1. Solder the chip 1 to the carrier 2 to obtain a chip module.

[0050] Specifically, such as Figure 2As shown, the chip 1 and the carrier 2 are connected together by tin welding, nano silver sintering or diffusion welding, and the signal terminal on the side panel of the chip 1 is electrically connected to the carrier 2.

[0051] The carrier 2 may be, but is not limited to, a copper block or a copper-clad insulating substrate; the chip 1 may be, but is not limited to, a silicon carbide (SiC) power chip or a gallium nitride (GaN) power chip.

[0052] Preferably, the carrier 2 is a copper-clad insulating substrate. Figure 3 As shown, the carrier 2 includes an upper metal layer 3, an insulating layer 4, and a lower metal layer 5 stacked in sequence. One side surface of the chip 1 is bonded to the upper metal layer 3 and soldered, and the signal terminals on the side surface of the chip 1 are electrically connected to the upper metal layer 3.

[0053] Specifically, the insulating layer 4 may be made of a plate with good insulation and thermal conductivity. For example, the insulating layer 4 may be made of, but not limited to, silicon nitride, aluminum oxide, aluminum nitride, diamond or silicon carbide.

[0054] The upper metal layer 3 and the lower metal layer 5 can be made of, but are not limited to, copper.

[0055] It should be noted that the insulating layer 4 in the copper-clad insulating substrate can achieve insulation between the upper metal layer 3 and the lower metal layer 5. The copper-clad insulating substrate can be, but is not limited to, a thin film ceramic substrate (TFC), a thick film printed ceramic substrate (TPC), a direct bonded copper ceramic substrate (DBC), a directly aluminum-bonded ceramic substrate (DBA), a directly electroplated copper ceramic substrate (DPC), an active metal welding ceramic substrate (AMB), a directly sputtered copper ceramic substrate (DSC) or a laser activated metal ceramic substrate (LAM).

[0056] Exemplarily, the chip 1 is a silicon carbide power chip (SiC MOSFET). One side of the chip 1 is welded to the upper metal layer 3 of the carrier 2, and the drain signal terminal (D terminal) on this side of the chip 1 is electrically connected to the upper metal layer 3. The other side of the chip 1 is provided with a source signal terminal (S terminal) and a gate signal terminal (G terminal).

[0057] The carrier's rigidity prevents the chip from deforming or breaking when subjected to external pressure. Thanks to the carrier's thermal capacity, the chip can quickly dissipate heat when subjected to short, high-current surges. Furthermore, the use of a copper-clad insulating substrate as the carrier ensures effective insulation between the chip and external conductors while also enhancing heat dissipation from the power device.

[0058] Furthermore, welding the chip to the carrier includes:

[0059] One side surface of the chip 1 is welded to the first metal surface on the carrier 2, and the signal terminal of the chip 1 arranged on the side surface is electrically connected to the first metal surface; the other side surface of the chip 1 and the second metal surface on the carrier 2 are located in the same plane; wherein the first metal surface and the second metal surface are electrically connected.

[0060] Specifically, the chip 1 is a silicon carbide power chip (SiC MOSFET), and the carrier 2 is a copper-clad insulating substrate. One side surface of the chip 1 is welded to the first metal surface of the upper metal layer 3, and the drain signal terminal (D pole) on this side surface of the chip 1 is electrically connected to the upper metal layer 3. The other side surface of the chip 1 is provided with a source signal terminal (S pole) and a gate signal terminal (G pole), which are coplanar with the second metal surface of the upper metal layer 3; wherein, the first metal surface and the second metal surface are both provided on the side away from the insulating layer 4.

[0061] For example, Figure 4 As shown, a mounting groove 301 matching the thickness of the chip 1 is dug on the side of the upper metal layer 3 away from the insulating layer 4, and the bottom surface of the mounting groove 301 is the first metal surface; one side of the chip 1 is welded to the bottom surface of the mounting groove 301, and the drain signal terminal (D pole) on the side of the chip 1 is electrically connected to the bottom surface of the mounting groove 301; the area of ​​the side of the upper metal layer 3 except the mounting groove 301 is the second metal surface, which is located in the same plane as the other side of the chip 1.

[0062] For example, Figure 5 As shown, a boss 302 with the same thickness as the chip 1 is integrally formed on the side of the upper metal layer 3 away from the insulating layer 4, and the top surface of the boss 302 is the second metal surface; the area on the side of the upper metal layer 3 except the boss 302 is the first metal surface; one side of the chip 1 is welded to the first metal surface, and the drain signal terminal (D pole) on the side of the chip 1 is electrically connected to the upper metal layer 3; the other side of the chip 1 and the top surface of the boss 302 are in the same plane.

[0063] For example, Figure 6 As shown, a raised copper foil 303 with the same thickness as the chip 1 is welded on the side of the upper metal layer 3 away from the insulating layer 4, and the top surface of the raised copper foil 303 is the second metal surface; the area on the side of the upper metal layer 3 except the raised copper foil 303 is the first metal surface; one side of the chip 1 is welded to the first metal surface, and the drain signal terminal (D pole) on the side of the chip 1 is electrically connected to the upper metal layer 3; the other side of the chip 1 and the top surface of the raised copper foil 303 are located in the same plane.

[0064] By adding bosses or raising the copper foil on the upper metal layer, or by creating a mounting slot for the power chip, the goal is to reduce the height of the metal vias between the external circuitry and the chip module during subsequent processing. This prevents the problem of copper-cladding the plating solution when the metal vias are too high during subsequent electroplating. This ensures that all metal vias in the power device module are of the same or similar height, reducing the complexity of the electroplating process and improving product yield.

[0065] S2. Performing a plastic encapsulation molding process on the chip module to obtain a chip module package.

[0066] Specifically, a molding material such as polyimide, epoxy molding compound or bismaleimide triazine resin is poured around the periphery of the chip module to form a first molding body 6 for insulating and encapsulating the internal chip module.

[0067] Compared with the conventional PP semi-cured film lamination process, the present invention provides a plastic encapsulation molding process for preliminary packaging of the chip module. The chip does not need to withstand high pressure, has low production process requirements and low cost, and has a high product qualification rate.

[0068] Furthermore, during the plastic encapsulation process, the upper surface of the chip module package is made higher than the upper surface of the chip module, or is coplanar with the upper surface of the chip module.

[0069] For example, Figure 7 As shown, the bottom of the chip module is fitted to the bottom of the cavity in the mold 7. Plastic packaging material is injected into the cavity of the mold 7 so that the height a of the first plastic packaging body 6 is greater than or equal to the height b of the chip module.

[0070] In the subsequent pressing process, the first plastic package body can disperse and balance the pressure on the chip surface, thereby protecting the chip and ensuring that the chip will not be squeezed, deformed or broken.

[0071] It should be noted that due to the different structures of different molds, during the actual plastic packaging process, the lower surface of the chip module can be coplanar with the lower surface of the first plastic packaging body, or the lower surface of the chip module can be wrapped in the first plastic packaging body.

[0072] Preferably, during the plastic encapsulation process, the lower surface of the chip module is made coplanar with the lower surface of the chip module package.

[0073] like Figure 7As shown, the lower surface of the chip module is the lower surface of the carrier. Because the lower surface of the carrier can be directly connected to the heat sink, the heat dissipation of the power device module can be improved. Making the lower surface of the chip module coplanar with the lower surface of the first plastic package protects the chip within the chip module package and eliminates the need to remove the plastic packaging material from the bottom of the chip module package when installing the heat sink, thus optimizing the process flow.

[0074] S3. Perform lamination and pressing processing on the chip module package to obtain a core board.

[0075] Furthermore, laminating and pressing the chip module package includes:

[0076] S31. The chip module package is used as the core layer of the PCB. One or more metal films are stacked on the side of the board near the chip according to functional requirements. PP semi-cured films are laid between each metal film and between the metal film and the PCB core layer.

[0077] S32, performing a pressing process to manufacture a core board containing power devices.

[0078] Specifically, the PP semi-cured film may be, but is not limited to, FR4 (containing epoxy resin) or BT (containing bismaleimide triazine resin) semi-cured film; the metal film may be, but is not limited to, copper film.

[0079] During the pressing process, the first plastic package body can disperse and balance the pressure on the chip surface, thereby protecting the chip and ensuring that the chip will not be squeezed, deformed or broken.

[0080] Furthermore, before laminating and pressing the chip module package, the chip module package can be embedded into a pre-hollowed groove of the initial core board, and the initial core board and the chip module package as a whole serve as the PCB core layer.

[0081] Specifically, the initial core board may be a single layer or multiple layers of laminated PP semi-cured films.

[0082] During the subsequent lamination process, the initial core board is subjected to high temperature and high pressure, and the pre-impregnated resin material therein flows and fills various gaps, thereby forming a core board with a dense structure.

[0083] S4. Perform circuit connection processing on the core board to obtain a power device module.

[0084] Specifically, the circuit connection process can adopt a conventional PCB board circuit connection process. For example, the core board is pattern-etched to form each functional circuit. Then, holes or grooves are opened at specific locations on the core board, and then metal via structures are electroplated at the holes or grooves. The electrical connection points on the chip and the carrier are connected to the corresponding functional circuits through the metal via structures, completing the connection of each circuit in the power device module.

[0085] For example, Figure 8 As shown, the chip 1 adopts a silicon carbide power chip (SiC MOSFET); the carrier 2 adopts a copper-clad insulating substrate. One side surface of the chip 1 is welded to the upper metal layer 3 of the carrier 2, and the drain signal terminal (D pole) on the side surface of the chip 1 is electrically connected to the upper metal layer 3. The chip module package is used as the PCB core layer, and a layer of metal film is stacked and laid on the side surface close to the chip 1, wherein a PP semi-cured film is also laid between the metal film and the PCB core layer; a pressing process is performed to obtain a core board. Holes or grooves are opened at specific positions of the core board, and then electroplating is performed to construct a metal via structure. The electrical connection points on the chip and the carrier are connected to the metal film on the core board through the metal via structure. The metal film of the core board is then patterned and etched to form a functional circuit.

[0086] like Figure 9 and Figure 10 As shown, the functional circuit 9 includes a first external circuit 901, a second external circuit 902 and a third external circuit 903; the first external circuit 901 is electrically connected to the upper metal layer 3 through the corresponding metal via 8; the second external circuit 902 is electrically connected to the source signal terminal (S pole) of the chip 1 through the corresponding metal via 8; the third external circuit 903 is electrically connected to the gate signal terminal (G pole) of the chip 1 through the corresponding metal via 8.

[0087] like Figure 11 As shown, during the lamination and lamination process, the chip module package is treated as a PCB core layer, with the multiple metal film layers thereon forming circuit layers 10 for constructing functional circuits. The resulting power device module after lamination is a PCB circuit board. The PCB manufacturing process provided by the present invention provides excellent protection for the chip within by the first plastic encapsulation during the lamination process. Furthermore, the requirements for the process environment during the subsequent PCB lamination process are significantly reduced, significantly contributing to the module's yield.

[0088] It should be noted that in the power device module preparation process provided by the present invention, multiple chip modules can be simultaneously subjected to a plastic encapsulation molding process to obtain a chip module package containing multiple chip modules; multiple chip module packages can also be simultaneously laminated and pressed to obtain a core board containing multiple chip module packages. The power device module provided by the present invention can include multiple chip modules or multiple chip module packages, thereby constructing various series and parallel structures to form a power device module with rich and diverse power functions.

[0089] It should be noted that the power device module provided by the present invention can be used as a single-transistor power device. In this case, the exposed metal film layer on the outermost side of the power device module can be pattern-etched into a pad structure, which can be directly soldered to other PCB functional boards. This enriches the application scenarios of the power device module and reduces the usage requirements of the power device module.

[0090] The single-tube power device produced by the present invention through the plastic packaging molding process is smaller in volume than a single tube in a conventional TO247 or T-PACK package, reduces current conduction loss, and improves the power density of integrated application scenarios.

[0091] Furthermore, the preparation process further comprises:

[0092] S5. Install a heat sink on the lower surface of the power device module.

[0093] If the bottom of carrier 2 is encapsulated with plastic molding material, the lower surface of the chip module package must be grooved and electroplated before installing the heat sink. If the bottom of carrier 2 is not encapsulated with plastic molding material, there is no need to remove the plastic molding material from the bottom of the chip module package when installing the heat sink, thus optimizing the process flow.

[0094] When the carrier adopts a copper-clad insulating substrate, the lower metal layer 5 can be directly connected to the heat sink, which is beneficial to reducing the heat dissipation thermal resistance of the chip.

[0095] Furthermore, the preparation process further comprises:

[0096] Preferably, the preparation process further comprises:

[0097] S6. The power device module is packaged using a plastic packaging process.

[0098] After the circuit connection of the power device module is completed, the power device module is packaged using a plastic packaging process to form a second plastic packaging body outside the power device module.

[0099] The second plastic package body can be made of, but is not limited to, polyimide material, epoxy resin molding compound or bismaleimide triazine resin material.

[0100] Insulating the exposed conductive structure of the power device module through plastic encapsulation is easier to implement and less costly than ensuring creepage distance by adjusting the circuit solution.

[0101] It should be noted that the lower surface of the chip module is the lower surface of the carrier. Because the lower surface of the carrier can be directly connected to the heat sink, the heat dissipation of the power device module can be improved. Enabling the lower surface of the chip module to be coplanar with the lower surface of the second plastic encapsulation body not only insulates the conductive structures within the power device module but also eliminates the need to remove the plastic encapsulation material from the bottom of the power device module when installing the heat sink, thus optimizing the process flow.

[0102] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A process for preparing a power device module, characterized in that: The preparation process comprises: S1. Soldering the chip to the carrier to obtain a chip module; S2, performing a plastic encapsulation molding process on the chip module to obtain a chip module package; S3, laminating and pressing the chip module package to obtain a core board; S4. Perform circuit connection processing on the core board to obtain a power device module.

2. The process for preparing a power device module according to claim 1, wherein: The carrier is a copper-clad insulating substrate, comprising an upper metal layer, an insulating layer and a lower metal layer stacked in sequence; The insulating layer can be made of a plate with good insulation and thermal conductivity; the upper metal layer and the lower metal layer can be made of copper.

3. The process for preparing a power device module according to claim 1, wherein: Welding the chip to the carrier includes: One side surface of the chip is welded to the first metal surface on the carrier, and the signal terminal of the chip arranged on the side surface is electrically connected to the first metal surface; the other side surface of the chip and the second metal surface on the carrier are located in the same plane; wherein the first metal surface and the second metal surface are electrically connected.

4. The process for preparing a power device module according to claim 2, wherein: A mounting groove matching the thickness of the chip is dug on the side of the upper metal layer away from the insulating layer; one side of the chip is welded to the bottom of the mounting groove, and the signal terminal on the side of the chip is electrically connected to the bottom of the mounting groove; Alternatively, a boss having the same thickness as the chip is integrally formed on the side of the upper metal layer away from the insulating layer; the side of the chip is welded to the area of ​​the upper metal layer on the side away from the insulating layer except for the boss, and the signal terminal of the chip on the side is electrically connected to the upper metal layer; the other side of the chip and the top surface of the boss are located in the same plane; Alternatively, a raised copper sheet with the same thickness as the chip is welded on the side of the upper metal layer away from the insulating layer; one side of the chip is welded to the area on the side of the upper metal layer away from the insulating layer except for the raised copper sheet, and the signal terminal on the side of the chip is electrically connected to the upper metal layer; the other side of the chip and the top surface of the raised copper sheet are located in the same plane.

5. The process for preparing a power device module according to claim 1, wherein: The plastic encapsulation process includes: pouring plastic encapsulation material around the periphery of the chip module, plastic encapsulating the outside of the chip module to form a first plastic encapsulation body, and insulating and encapsulating the internal chip module.

6. The process for preparing a power device module according to claim 5, characterized in that: During the plastic encapsulation process, the upper surface of the chip module package body is made higher than the upper surface of the chip module, or is coplanar with the upper surface of the chip module.

7. The process for preparing a power device module according to claim 5, characterized in that: During the plastic encapsulation process, the lower surface of the chip module is made coplanar with the lower surface of the chip module package.

8. The process for preparing a power device module according to claim 1, wherein: The lamination and pressing process of the chip module package includes: S31. The chip module package is used as the core layer of the PCB. One or more metal films are stacked on the side of the board near the chip according to functional requirements. PP semi-cured films are laid between each metal film and between the metal film and the PCB core layer. S32, performing a pressing process to manufacture a core board containing power devices.

9. The process for preparing a power device module according to claim 8, wherein: Before laminating and pressing the chip module package, the chip module package can be embedded into the hollowed-out groove of the initial core board, and the initial core board and the chip module package as a whole serve as the core layer of the PCB.

10. A power device module, characterized in that: The power device module is prepared by any preparation process in claims 1-9.

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