Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure. The semiconductor structure comprises a first semiconductor structure layer and a second semiconductor structure layer which are bonded together, the first semiconductor structure layer comprises a first substrate, the second semiconductor structure layer comprises a second substrate, and a fourth interconnection structure of the second substrate is aligned with a second interconnection structure of the first substrate and forms direct electric connection with the second interconnection structure of the first substrate. On one hand, a new three-dimensional metal interconnection integration thought that the drain electrode power supply and the source electrode power supply are separated up and down is provided, and the layout area can be effectively reduced. The invention further discloses a corresponding method.

Description

Technical Field

[0001] The present application relates to a semiconductor structure and a manufacturing method, and in particular to a three-dimensional interconnect structure within a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Historically, transistors have been formed in one plane using microfabrication with wiring / metal formed on top, and thus the transistors have been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, but scaling is becoming more challenging as scaling enters single-digit nanometer semiconductor device fabrication nodes. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor devices in which devices, transistors, and standard cells are stacked on top of each other as a means of continuing scaling. The fabrication of 3D semiconductor devices presents many new and unique challenges associated with new process integration, novel hardware and process capabilities, design, post-fabrication processing, electronic design automation, and other aspects of the 3D manufacturing process.

[0003] The integration of 3D semiconductor devices is widely recognized as one of the leading candidates for further chip area reduction. Traditional 3D integration designs include 1) PFET on NFET (P-type field-effect transistor on N-type field-effect transistor), or NFET on PFET (N-type field-effect transistor on P-type field-effect transistor), both of which are called complementary field-effect transistors, or CFETs. Alternatively, 2) a specially designed N-type field-effect transistor on N-type field-effect transistor and P-type field-effect transistor on P-type field-effect transistor.

[0004] Based on the current integration method of metal interconnection, the layout area reduction is less than expected and the performance is also reduced. Summary of the Invention

[0005] One of the objectives of the present application is to provide a three-dimensional metal interconnect structure with a smaller layout area while ensuring its performance.

[0006] To this end, some embodiments of the present application provide a semiconductor structure comprising a first semiconductor structure layer and a second semiconductor structure layer bonded together, wherein the first semiconductor structure layer comprises a first surface having a first orientation and a second surface having a second orientation opposite to the first surface, and the second semiconductor structure layer comprises a third surface having a first orientation and a fourth surface having a second orientation opposite to the third surface; the first semiconductor structure layer comprises a first substrate, at least one first active region formed on the first substrate of the first surface, a first gate structure formed on the first active region, and a first doped region and a second doped region of a first conductivity type formed at positions on both sides of the first gate structure; and further comprising a first interconnect structure extending from the second surface and electrically connected to the first doped region, extending from the first surface and electrically connected to a second interconnect structure of the second doped region; the second semiconductor structure layer includes a second substrate, at least one second active region formed on the second substrate on the third surface, a second gate structure formed on each of the second active regions, and a third doped region and a fourth doped region of a second conductive type different from the first conductive type formed on both sides of the second gate structure; also including a third interconnect structure extending from the side of the fourth surface and electrically connected to the third doped region, and a fourth interconnect structure, the fourth interconnect structure extending from the third surface and electrically connected to the fourth doped region; wherein the fourth surface of the second semiconductor structure layer is bonded to the first surface of the first semiconductor structure layer, and the fourth interconnect structure passes through the second semiconductor structure layer and is electrically connected to the second interconnect structure.

[0007] In some embodiments, the first interconnect structure includes a first buried power rail and a first contact portion electrically connected to the first doped region, and a first contact doped region is provided at a position of the first substrate corresponding to the first buried power rail, and the first contact doped region has a second conductivity type different from the first conductivity type.

[0008] Some other embodiments of the present application provide a semiconductor structure, which includes a first semiconductor structure layer and a second semiconductor structure layer bonded together, wherein the first semiconductor structure layer includes a first surface with a first orientation and a second surface with a second orientation opposite to the first surface, and the second semiconductor structure layer includes a third surface with a first orientation and a fourth surface with a second orientation opposite to the third surface; the first semiconductor structure layer includes a first substrate, at least one first active region formed on the first surface of the first substrate, a first gate structure formed on each of the first active regions, and a first doped region and a second doped region of a first conductivity type formed on both sides of the first gate structure; and further includes a first interconnect structure extending from the second surface and electrically connected to the first doped region. and a second interconnect structure extending from the first surface and electrically connected to the second doped region; the second semiconductor structure layer includes a second substrate, at least one second active region formed on the second substrate on the third surface, a second gate structure formed on each of the second active regions, and a third doped region and a fourth doped region of a second conductive type different from the first conductive type formed on both sides of the second gate structure; also including a third interconnect structure extending from the fourth surface to and electrically connected to the third doped region, and a fourth interconnect structure extending from the third surface to and electrically connected to the fourth doped region; wherein the third surface of the second semiconductor structure layer is bonded to the first surface of the first semiconductor structure layer, and after bonding, the fourth interconnect structure is electrically connected to the second interconnect structure.

[0009] In some embodiments, the first interconnect structure includes a first buried power rail and a first contact portion electrically connected to the first doped region, a first contact doped region is provided at a position of the first substrate corresponding to the first buried power rail, and the first contact doped region has a second conductivity type different from the first conductivity type; the third interconnect structure includes a second buried power rail and a second contact portion electrically connected to the third doped region, a second contact doped region is provided at a position of the second substrate corresponding to the second buried power rail, and the second contact doped region has a first conductivity type different from the second conductivity type.

[0010] In some embodiments, when the first semiconductor structure layer and the second semiconductor structure layer are configured to be bonded together, the fourth interconnect structure and the second interconnect structure are bonded facing each other to form a direct electrical connection.

[0011] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes the following steps: providing a first substrate for forming a first semiconductor structure layer, forming at least one mutually isolated first active region in the first substrate from a first surface of the first substrate; forming a first gate structure on each of the first active regions; etching to form a first deep groove on one side of the first gate structure; forming a first sacrificial material portion by epitaxially growing a sacrificial material in the first deep groove; forming a first doping region groove and a second doping region groove on both sides of the first gate structure, respectively, wherein the first doping region groove is connected to the first sacrificial material portion, forming a doped epitaxial layer of a first conductive type in the first doping region groove and the second doping region groove to grow a first doping region and a second doping region to form the first semiconductor structure layer; forming a second contact hole extending from the first surface to the second doping region, and filling the second contact hole to form a second interconnection structure electrically connected to the second doping region; bonding a second interconnection structure for forming a second doping region on the surface of the first substrate where the second interconnection structure is located. A second substrate of two semiconductor structure layers; forming at least one second active region on the second substrate, forming a second gate structure in each of the second active regions, and forming a third doped region and a fourth doped region of a second conductivity type different from the first conductivity type on both sides of the second gate structure; forming a third interconnection structure electrically connected to the third doped region and a fourth interconnection structure electrically connected to the fourth doped region, respectively; wherein, forming the fourth interconnection structure includes etching the second semiconductor structure layer to form a fourth contact hole connecting the fourth doped region and the second interconnection structure; and after any one of the above steps, exposing the first sacrificial material portion from the second surface of the first substrate; forming a first contact hole on the first sacrificial material portion; removing the first sacrificial material portion; filling the first contact hole and the first deep trench to form a first interconnection structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region to form the first semiconductor structure layer.

[0012] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes the following steps: providing a first substrate for forming a first semiconductor structure layer, forming at least one mutually isolated first active region in the first substrate from a first surface of the first substrate, and forming a first gate structure on each of the first active regions; etching on one side of the first gate structure to form a first deep trench; forming a first sacrificial material portion by epitaxially growing a sacrificial material in the first deep trench; forming a first doping region groove and a second doping region groove on both sides of the first gate structure, respectively, wherein the first doping region groove is connected to the first sacrificial material portion, forming a first conductive type doped epitaxial layer in the first doping region groove and the second doping region groove to grow a first doping region and a second doping region; forming a second contact hole extending from the first surface to the second doping region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doping region; providing a second substrate for forming a second semiconductor structure layer, forming a buried oxide layer on the second substrate, forming at least one second active region on the buried oxide layer, and forming a second gate structure on each of the second active regions; forming a second conductive type different from the first conductive type on both sides of the second gate structure. The method further comprises: forming a third doped region and a fourth doped region of the second semiconductor structure layer from the third surface of the second semiconductor structure layer, respectively connecting the third doped region and the fourth doped region to form the second semiconductor structure layer, wherein the fourth interconnection structure forms the second semiconductor structure layer based on the fourth contact hole etched into the fourth doped region; thinning the second substrate to expose the buried oxide layer, adding a bonding dielectric layer to the buried oxide layer, bonding the second semiconductor structure layer to a surface of the second interconnection structure of the first substrate through the bonding dielectric layer, forming a metal connection trench penetrating the second semiconductor structure layer, and forming a metal connection structure therein to electrically connect the second interconnection structure and the fourth interconnection structure; and after any one of the above steps, exposing the first sacrificial material portion from the second surface of the first substrate; forming a first contact hole on the first sacrificial material portion; removing the first sacrificial material portion; and filling the first contact hole and the first deep trench to form a first interconnection structure, wherein the metal in the first contact hole forms a first buried power rail, and the metal in the first deep trench forms a first contact portion connecting the first buried power rail to the first doped region to form the first semiconductor structure layer.

[0013] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes the following steps: providing a first substrate for forming a first semiconductor structure layer, forming at least one mutually isolated first active region in the first substrate from a first surface of the first substrate, and forming a first gate structure on each of the first active regions; etching on one side of the first gate structure to form a first deep groove; forming a first sacrificial material portion by epitaxially growing a sacrificial material in the first deep groove; forming a first doped region groove and a second doped region groove on both sides of the first gate structure, respectively, wherein the first doped region groove is connected to the first sacrificial material portion, forming a first conductive type doped epitaxial layer in the first doped region groove and the second doped region groove to grow a first doped region and a second doped region to form the first semiconductor structure layer; forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; forming a buried oxide layer on the second substrate for forming the second semiconductor structure layer, forming at least one second active region on the buried oxide layer, and forming a second gate on each of the second active regions. structure; forming a third doped region and a fourth doped region of a second conductivity type different from the first conductivity type on both sides of the second gate structure; thinning the second substrate to expose the buried oxide layer, adding a bonding dielectric layer to the buried oxide layer, and bonding the second semiconductor structure layer to one side of the second interconnect structure of the first substrate through the bonding dielectric layer; forming a third interconnect structure electrically connected to the third doped region and forming a fourth interconnect structure electrically connected to the fourth doped region and the second interconnect structure to form a second semiconductor structure layer, wherein forming the fourth interconnect structure includes etching the second semiconductor structure layer to connect a fourth contact hole of the second interconnect structure; and after any of the above steps, exposing the first sacrificial material portion from the second side of the first substrate; forming a first contact hole on the first sacrificial material portion; removing the first sacrificial material portion; filling the first contact hole and the first deep trench to form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region to form the first semiconductor structure layer.

[0014] In some embodiments, the method includes forming the first sacrificial material portion by etching the first surface of the first active region to the bottom of the shallow trench isolation to form a first deep trench; and forming the first sacrificial material portion by epitaxially growing silicon germanium material in the first deep trench.

[0015] In some embodiments, the method of forming the first interconnect structure includes processing the second surface of the first active area until the first sacrificial material portion is exposed; forming a first buried power rail isolation layer; opening a hole in the first buried power rail isolation layer and performing ion implantation to form a first contact implantation region of a second conductivity type; patterning the contact hole and etching the first sacrificial material portion to form the first deep trench; filling the contact hole and the first deep trench with metal, forming silicide, and planarizing to form the first contact portion and the first buried power rail to constitute the first interconnect structure.

[0016] In some embodiments of the method, forming the fourth interconnect structure includes filling the fourth contact hole with metal, performing metal backetching so that the height of the metal layer in the fourth contact hole is reduced to below the height of the upper surface of the second gate but still covers the fourth doped region, and backfilling the fourth contact hole with insulating material to form the fourth interconnect structure.

[0017] In some embodiments, the method includes forming the third interconnect structure and the fourth interconnect structure in sequence.

[0018] In some embodiments, the method includes forming the second interconnect structure including forming the second interconnect structure using a self-aligned contact process.

[0019] In the method of some embodiments, exposing the first sacrificial material portion includes thinning the first substrate as a whole or locally etching the first sacrificial material portion of the first substrate using a through silicon via process.

[0020] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes the following steps: providing a first substrate for forming a first semiconductor structure layer, forming at least one mutually isolated first active region in the first substrate, and forming a first gate structure on each of the first active regions; etching one side of the first gate structure to form a first deep trench; forming a first sacrificial material portion by epitaxially growing a sacrificial material in the first deep trench; forming a first doped region groove and a second doped region groove on both sides of the first gate structure, wherein the first doped region groove is connected to the first sacrificial material portion, and forming a first conductive region groove in the first doped region groove and the second doped region groove. The method further comprises: forming a first doped region and a second doped region by growing an electrically doped epitaxial layer of an electrical type; forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; providing a second substrate for forming a second semiconductor structure layer, forming at least one second active region isolated from each other in the second substrate, and forming a second gate structure on each second active region; etching one side of the second gate structure to form a second deep groove; forming a second sacrificial material portion by epitaxially growing a sacrificial material in the second deep groove; forming a third doped region groove and a fourth doped region groove on both sides of the second gate structure; a third doping region groove, wherein the third doping region groove is connected to the second sacrificial material portion, and a doped epitaxial layer of a second conductivity type different from the first conductivity type is formed in the third doping region groove and the fourth doping region groove respectively to grow a third doping region and a fourth doping region; a third contact hole is formed extending from the third surface to the third doping region, and the third contact hole is filled to form a third interconnect structure electrically connected to the third doping region; after any of the above steps, the first sacrificial material portion is exposed from the second surface of the first substrate; a first contact hole is formed on the first sacrificial material portion; the first sacrificial material portion is removed; the first contact hole and the first deep The grooves form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep groove forms a first contact portion connecting the first buried power rail and the first doped region; and after any of the above steps, exposing the second sacrificial material portion from the fourth side of the second substrate; forming a third contact hole on the second sacrificial material portion; removing the second sacrificial material portion; filling the third contact hole and the second deep groove to form a third interconnect structure, wherein the metal in the third contact hole forms a second buried power rail and the metal in the second deep groove forms a third contact portion connecting the second buried power rail and the third doped region.

[0021] In some embodiments of the method, forming the first sacrificial material portion includes performing deep trench etching in the first active area to form a first deep trench at the bottom of a first shallow trench isolation; forming the first sacrificial material portion by epitaxially growing silicon germanium material in the first deep trench; forming the second sacrificial material portion includes performing deep trench etching in the second active area to form a second deep trench at the bottom of a second shallow trench isolation; and forming the second sacrificial material portion by epitaxially growing silicon germanium material in the second deep trench.

[0022] In some embodiments of the method, forming the first interconnect structure includes processing the first active area until the first sacrificial material portion is exposed; forming a first isolation layer; opening the first isolation layer and performing ion implantation of the second conductive type to form a first contact implantation region; patterning the contact hole and etching the first sacrificial material portion to form a first contact hole; filling the first contact hole and the first deep trench with metal, forming silicide, and planarizing to form a first interconnect structure; forming the third interconnect structure includes processing the second active area until the second sacrificial material portion is exposed; forming a second isolation layer; opening the second isolation layer and performing ion implantation of the first conductive type to form a second contact implantation region; patterning the contact hole and etching the second sacrificial material portion to form a second contact hole; filling the second contact hole and the second deep trench with metal, forming silicide, and planarizing to form a third interconnect structure.

[0023] The beneficial effects of this application are as follows: on the one hand, the proposed novel three-dimensional metal interconnect integration strategy using vertically separated drain power supply VDD and source power supply VSS can effectively reduce the layout area; on the other hand, in some embodiments, the contact hole connection method using a self-aligned contact process can fully expand the patterning process space. Still another aspect is that in some embodiments, three-dimensional metal interconnection of a three-dimensional CFET can be realized, reducing the layout area and improving the process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a power supply interconnection layout of a semiconductor structure according to the present application.

[0025] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E and Figure 2F Schematic diagram of a front-end process structure of a first semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0026] Figure 3A 、 Figure 3B 、 Figure 3B1 、 Figure 3C 、 Figure 3D、 Figure 3E 、 Figure 3F and Figure 3G Schematic diagram of a BPR process structure of a first semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0027] Figure 4A 、 Figure 4B ,and Figure 4C Schematic diagram of a mid-stage process structure of a first semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0028] Figure 5A and Figure 5B Schematic diagram of a front-end process structure of a second semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0029] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 6E and Figure 6F Schematic diagram of a middle-stage process structure of a second semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0030] Figure 7A 、 Figure 7B and Figure 7C Schematic diagram of a bonding process structure of a first semiconductor structure layer and a second semiconductor structure layer of a semiconductor structure according to an embodiment of the present application.

[0031] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D Schematic diagram of a bonding process structure of a first semiconductor structure layer and a second semiconductor structure layer of a semiconductor structure according to another embodiment of the present application.

[0032] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D Schematic diagram of a bonding process structure of a first semiconductor structure layer and a second semiconductor structure layer of a semiconductor structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0033] The specific implementation scheme of this application is described in detail below with reference to the accompanying drawings.

[0034] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0035] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0036] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0037] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0038] In addition, ordinal numbers such as "first" and "second" are used herein to distinguish components or regions with the same name, and these ordinal numbers do not limit the importance or existing order of these components or regions.

[0039] According to embodiments of the present application, a three-dimensional (3D) semiconductor structure may be composed of multiple layers, for example, two layers, which may include a first semiconductor structure layer 100, i.e., layer A, and a second semiconductor structure layer 200, i.e., layer B. Each layer is formed based on a substrate material and may include active devices such as transistors, interconnects, and power rails. The first semiconductor structure layer 100 and the second semiconductor structure layer 200 may be bonded together to form a three-dimensional semiconductor structure, for example, to form a complementary semiconductor device, such as a CFET semiconductor device or a CMOSFET device.

[0040] The first semiconductor structure layer 100 may include a first surface 100A in a first orientation and a second surface 100B oriented opposite to the first surface 100A. The second semiconductor structure layer 200 may include a third surface 200A in a first orientation and a fourth side 200B oriented opposite to the third surface 200A. One side of the first semiconductor structure layer, such as the first surface or the second surface, is bonded to one side of the second semiconductor structure layer, such as the third surface and the fourth surface. The first substrate used to form the first semiconductor structure layer includes a first surface and a second surface oriented in the same direction as the first semiconductor structure layer, and the second substrate used to form the second semiconductor structure layer also includes a third surface and a fourth surface oriented in the same direction.

[0041] The first semiconductor structure layer 100 may include a first surface 100A having a first orientation during the formation process and a second surface 100B having a second orientation opposite to the first surface 100A. The second semiconductor structure layer 200 may include a third surface 200A having a first orientation during the formation process and a fourth surface 200B having a second orientation opposite to the third surface 200A. One side of the first semiconductor structure layer, such as the first surface or the second surface, is bonded to one side of the second semiconductor structure layer, such as the third surface and the fourth surface. The first substrate used to form the first semiconductor structure layer includes a first surface and a second surface having the same orientation as the first semiconductor structure layer, and the second substrate used to form the second semiconductor structure layer also includes a third surface and a fourth surface having the same orientation.

[0042] The specific implementation scheme of this application is described below using the CFET inverter structure design and process integration design of PFET on NFET.

[0043] Figure 2A This is a diagram of the initial state of the front-end-of-line (A-FEOL) process of the first semiconductor structure layer 100, i.e., the A layer, which includes forming, for example, an N-MOSFET device on a first substrate, such as a first wafer. To form the N-MOSFET device, consistent with conventional processes, the first semiconductor structure layer 100 first forms at least one, preferably multiple, first active regions 110 on the first substrate. Adjacent first active regions are separated by a shallow trench isolation structure (STI structure) 120, and a first gate structure 111, a dummy gate or a real gate, is formed on the first surface of the first substrate. The upper layer of the first gate structure can be provided with a hard mask of, for example, silicon nitride (Si3N4) material. In addition, in order to protect the surface of the first gate structure, an isolation sidewall, such as an isolation sidewall of silicon oxide or silicon nitride material, can be provided to prevent it from short-circuiting with the source or drain.

[0044] Then as Figure 2A 、 Figure 2B As shown, a hard mask 130 is patterned to open the source terminal 1102 in the first active region 110, and then a deep trench is etched at the location where the source terminal 1102 is opened to the bottom of the STI structure 120 to form a deep trench 114a. Figure 2C As shown, a first sacrificial material portion 114 for a buried power rail (BPR) is formed in the etched deep trench 114a using a SiGe epitaxial growth process. For example, after an undoped SiGe material is epitaxially grown in the deep trench 114a, the hard mask 130 is removed. Figure 2D As shown, the first source region groove 112 a and / or the first drain region groove 113 a are formed, and the formation process may be the same as the traditional process. Figure 2EA semiconductor structure is shown in which a first source region 112 and a first drain region 113 are formed by epitaxial growth (Epi) in the first source region groove 112a and / or the first drain region groove 113a. The material of the first source region 112 and / or the first drain region 113 can be an N-type semiconductor material such as SiAs, SiP, phosphorus-doped SiC, arsenic-doped SiC, or a stacked combination thereof, or a combination of their elemental materials, or doped with other elements.

[0045] Figure 2F The formation of the first gate structure 111 is shown, which includes isolating the first source region 112 / the first drain region 113, and then forming the first gate 111a using a high-K metal gate (HK-MG) process, followed by forming a first gate protection cap 111b on the first gate 111a, forming a first sidewall 111c structure on both sides, and then covering the middle isolation oxide layer, or a stacked isolation of the oxide layer and the silicon nitride layer. At this point, a first conductive channel is formed below the first gate structure 111 in the first semiconductor structure layer 100, between the first drain region and the first source region. The first drain region and the first source region need to be doped to provide corresponding functions, and therefore are also referred to as the first doping region and the second doping region. In addition to the above method, the first doping region and the second doping region can also be formed by epitaxial self-doping. Figure 2A The first conductive channel structure of the device shown in FIG can be a planar structure or a three-dimensional structure; the first gate structure 111 can be a traditional polycrystalline gate (PolyGate) or a HK-MG structure.

[0046] Following the front-end process is the process step of forming the first interconnect structure, such as an interconnect structure based on buried power rails. Although described separately here, in actual processing, there may be no clear dividing line between the two. For example, the process step of forming the first interconnect structure can exist as part of the front-end process.

[0047] Figure 3A The initial state diagram of the process A-BPR for forming the first interconnect structure of the first semiconductor structure layer 100 includes applying a protective layer 140 to the surface of the first wafer, flipping the first wafer, and starting the process from the back layer of the wafer, i.e., the second side. Figure 3B The structure diagram after the back silicon layer of the first wafer is thinned by the CMP process is shown. The silicon layer of the first wafer can be thinned as a whole by the CMP process until the SiGe material of the first sacrificial material part 114 is exposed. Figure 3B1 As shown, a nano-through silicon via (TSV) process may be used to etch the SiGe material until the first sacrificial material portion 114 is exposed. Figure 3CFIG. 1 is a structural diagram of a buried power rail isolation layer (BPR isolation layer) 150 after deposition. The BPR isolation layer 150 may be SiO 2 , SiN, Low-K material, or a combination of the above materials. Figure 3D The steps of patterning and opening a BPR contact hole, i.e., a first source terminal contact hole, or a first contact hole 151 , on the BPR isolation layer, and performing P+ ion implantation on the first substrate below the first contact hole 151 to form a contact doping region 160 are shown. Figure 3E 、 Figure 3F The structure after removing the first sacrificial material portion of SiGe material in the deep trench 114a is shown. The process may include: etching the SiGe material of the first sacrificial material portion 114. This etching process can have a high selectivity ratio with respect to Si and SiO2, so that the etching can directly reach the drain region 112 without damaging the surrounding structures of the deep trench 114a. In this process, the patterning and etching can be self-aligned, such as a self-aligned contact process (SAC process). Using this process in combination with the structure of providing a contact hole on each side of the first substrate proposed in this application can fully expand the patterning process space. Other processes similar to the SAC process can also be used to achieve self-alignment.

[0048] Figure 3F 、 3G The diagram shows the steps for forming a first interconnect structure 170, including a buried power rail 172 and a first contact portion 171 electrically connecting the buried power rail to the first source region 112. Specifically, an oxide layer 152, such as silicon oxide, is formed on the sidewalls of the first contact hole 151 to isolate the metal in the first contact hole 151 from the first substrate. A single metal or a mixed stack of multiple metals is then filled into the deep trench 114a and the first contact hole 151 to form the first interconnect structure 170. The first interconnect structure 170 can be a single metal structure or a mixed stack of multiple metals. A CMP process is then performed for planarization. Thus, the first interconnect structure is formed.

[0049] Figures 4A to 4C The figure shows the middle stage process A-MEOL of the first semiconductor structure layer 100, wherein: Figure 4A As shown, a protective layer is formed on the first interconnect structure after it is formed; the first wafer of the first semiconductor structure layer 100 is then turned over and the protective layer 140 on the surface of the wafer is removed. Figure 4B The diagram shows the self-aligned patterning and etching of the first drain terminal contact hole 181, i.e., the second contact hole. For example, a self-aligned contact (SAC) process or similar processes may be used. In this case, only one side of the second contact hole 181 is open, thereby fully expanding the process space, i.e., improving the scaling space. Figure 4CThe structure diagram shows the structure after filling the second contact hole 181 to form the first drain connection structure 180. Filling the second contact hole 181 to form the first drain connection structure 180, or the second interconnect structure, may include multi-layer metal filling, forming silicide, and CMP planarization.

[0050] Figure 5A 、 Figure 5B The process flow of the second semiconductor structure layer 200, namely the front-end B-layer, B-FEOL is shown. Figure 5A Shown in Figure 4C A bonding dielectric layer 301, an insulating layer 302, and a surface silicon layer 201 are formed on the A layer structure. The surface silicon layer can be subjected to surface treatments such as low-temperature annealing and CMP to facilitate subsequent processes. In some embodiments, the formation of the bonding dielectric layer 301 can include SICN deposition and annealing.

[0051] Figure 5B The second semiconductor structure layer 200 is shown as a device portion complementary to an N-MOSFET, such as a PFET device based on a second silicon-on-insulator (SOI) substrate formed by the aforementioned insulating layer 302 and the surface silicon layer 201. The PFET device includes a second active region 210, a second gate structure 211, a second source region 212, and a second drain region 213. The structures and specific steps for forming each component can be the same as those in conventional processes and will not be repeated here. For example, a polysilicon second gate 211a, a second gate protection cap 211b, and second gate spacers 211c on both sides can be formed. As a result, a second conductive channel is formed in the second semiconductor structure layer 200 below the second gate structure 211 and between the second drain region 212 and the second source region 212. Because the second drain region and the second source region require doping to provide corresponding functions, they are also referred to as the third doping region and the fourth doping region, respectively. Figure 5B Such a structure is illustrated using SOI-PFET as an example, but it should be understood that similar embodiments also include SOI-FinFET-PFET, SOI-P-TFET, SOI-PD or FD-PFET, etc., which may be implemented using SOI-based PFET device formation processes, but must comply with the low-temperature process requirements of 3D-CFET. Figure 5B The conductive channel structure of the device can be a planar structure or a three-dimensional structure; the second gate structure can be a traditional polycrystalline gate or a HK-MG structure.

[0052] Figures 6A to 6E FIG. 2 shows the middle stage process B-MEOL of the second semiconductor structure layer 200. Figure 6AAs shown, a second drain terminal contact hole 281, i.e., a fourth contact hole, is patterned and etched from the upper surface, i.e., the third surface 200A, of the second drain terminal of the second semiconductor structure layer 200 to the lower surface, i.e., the fourth surface 200B, of the second semiconductor structure layer 200. Similarly, a SAC process can be used, and only a single-sided contact hole is formed, i.e., either the second source region contact hole, i.e., the third contact hole, or the second drain region contact hole is opened to allow for larger process space, thereby improving scaling space. Figure 6B The figure shows a structure diagram of the second drain terminal metal layer 280 formed after the second drain region contact hole 281 of the SOI-PFET is filled. As shown in the figure, the second drain terminal metal layer 280 connects the second drain region of the PMOSFET in the upper second semiconductor structure layer 200, that is, the P-type semiconductor material region (P+) and the first drain region of the NMOSFET in the lower first semiconductor structure layer 100, that is, the metal structure of the N-type semiconductor material (N+) region, also known as the first drain connection structure 180, or the second interconnection structure; filling the second drain terminal contact hole 281 to form the second drain terminal metal layer 280, or the fourth interconnection structure, can include multi-layer metal filling, formation of silicide, and CMP planarization processes. Figure 6C The figure shows the metal etching back step after filling the second drain terminal contact hole 281 of the SOI-PFET. Through the metal etching back, the height of the metal layer 280 in the second drain terminal contact hole is reduced to below the height of the upper surface of the second gate protection cover 211b of the second gate and separated by the second sidewall 211c, but still covering the second drain region, that is, the P+ doped region of the second drain region. Figure 6D The figure shows the step of backfilling the insulating material 282 in the second drain terminal contact hole to form a fourth interconnect structure, wherein, in addition to backfilling SiO2, low-K material, SiN, or a combination thereof can also be used.

[0053] Figure 6E 6F is the formation and processing steps of the second source contact hole 271 and the second source connection structure 270, that is, the third interconnection structure. Figure 6E As shown, a second source contact hole 271 is formed in the source region of the SOI-PFET by patterning and etching. The SAC process can be used as described above. Similarly, only one side of the contact hole is opened to fully expand the process space and improve the scaling space. Figure 6F The second source contact hole 271 shown is filled to form a second source connection structure 270 , or referred to as a third interconnect structure. The filling process may include multi-layer metal filling, silicide formation, and CMP planarization.

[0054] It should be understood that the processing method proposed in this application is not limited to the above process sequence. For example, in addition to the sequence described in the first embodiment above, namely, sequentially performing the front-end process A-FEOL of the first semiconductor structure layer 100, the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100, the middle-end process A-MEOL of the first semiconductor structure layer 100, the front-end process B-FEOL of the second semiconductor structure layer 200, and the middle-end process B-MEOL of the second semiconductor structure layer 200, other sequences described below may also be used.

[0055] As a second embodiment, the order of the middle-end process A-MEOL of the first semiconductor structure layer 100 and the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100 can be interchanged to obtain the following processing sequence: the front-end process A-FEOL of the first semiconductor structure layer 100, the middle-end process A-MEOL of the first semiconductor structure layer 100, the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100, the front-end process B-FEOL of the second semiconductor structure layer 200, and the middle-end process B-MEOL of the second semiconductor structure layer 200. The definitions of each part, such as the first surface, the second surface, the third surface, and the fourth surface, are the same as those in the previous embodiment.

[0056] As a third embodiment, the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100 can be placed after the process B-FEOL of the front end of the second semiconductor structure layer 200, resulting in the following processing sequence: the front end process A-FEOL of the first semiconductor structure layer 100, the middle end process A-MEOL of the first semiconductor structure layer 100, the front end process B-FEOL of the second semiconductor structure layer 200, the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100, and the middle end process B-MEOL of the second semiconductor structure layer 200. The definitions of each part, such as the first surface, the second surface, the third surface, and the fourth surface, are the same as those in the previous embodiment.

[0057] As a fourth embodiment, the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100 can be placed after the middle process B-MEOL of the second semiconductor structure layer 200, resulting in the following processing sequence: the front-end process A-FEOL of the first semiconductor structure layer 100, the middle process A-MEOL of the first semiconductor structure layer 100, the front-end process B-FEOL of the second semiconductor structure layer 200, the middle process B-MEOL of the second semiconductor structure layer 200, and the process A-BPR for forming the buried power rail of the first semiconductor structure layer 100. The definitions of each part, such as the first surface, the second surface, the third surface, and the fourth surface, are the same as those in the previous embodiment.

[0058] In some embodiments of the present application, the structure of the second semiconductor structure layer 200 can be completed before the bonding process, or can be manufactured after the bonding process is completed, as described in the above embodiments.

[0059] like Figure 7A As shown, for a first semiconductor structure layer 100 having an N-MOSFET device and a first source connection structure 170 (first interconnection structure) including a first buried power rail 172 and a first contact portion 171, and a first drain connection structure 180 (second interconnection structure), a second semiconductor structure layer 200 having a symmetrical structure of a P-MOSFET device and a second source connection structure 270 (third interconnection structure) including a second buried power rail 272 and a second contact portion 271, and a second drain connection structure 280 (fourth interconnection structure) can be formed.

[0060] In this way, Figure 7B As shown, when the second semiconductor structure layer 200 is flipped and directly bonded to the first semiconductor structure layer 100 using, for example, a hybrid bonding technique, the first drain connection structure 180 (second interconnect structure) and the second drain connection structure 280 (fourth interconnect structure) can be aligned and bonded to form a structure as shown in FIG. Figure 7C The structure shown.

[0061] In some embodiments, as Figure 8A As shown, for a first semiconductor structure layer 100 having an N-MOSFET device and a buried first source connection structure 170 and a first drain connection structure 180, a PFET device can be formed on the second semiconductor structure layer 200 by a standard SOI process, and a second source connection structure 270 and a second drain connection structure 280 of the PFET device can be formed on the same side. In this embodiment, the bonding of the first semiconductor structure layer 100 and the second semiconductor structure layer 200 includes the following process steps. Figure 8B As shown, after adding an insulating layer to the top layer of the first surface 200A of the second semiconductor structure layer 200, the bottom substrate of the second surface 200B thereof can be thinned and removed to expose the buried oxide layer (BOX) at the bottom, and then a bonding dielectric layer can be added to the bottom of the buried oxide layer, for example, after a flipping operation.

[0062] like Figure 8CAs shown, the second surface 200B of the second semiconductor structure layer 200 is aligned and bonded to the first surface 100A of the first semiconductor structure layer 100 through a bonding dielectric layer. During the bonding process, the first drain connection structure 180 of the first semiconductor structure layer 100 can be aligned vertically with the second drain connection structure 280 of the second semiconductor structure layer 200, and a connection groove is formed vertically through the second semiconductor structure layer 200, and a metal connection structure is formed therein to connect the first drain connection structure 180 and the second drain connection structure 280, as shown in FIG. Figure 8D shown.

[0063] In some embodiments, as Figure 9A As shown, for the first semiconductor structure layer 100 having an N-MOSFET device and a buried first source connection structure 170 and a first drain connection structure 180, a PFET device can be formed on the second semiconductor structure layer 200 using a standard SOI process, but the second source connection structure 270 and the second drain connection structure 280 of the PFET device are not formed at this time. In this embodiment, the bonding of the first semiconductor structure layer 100 and the second semiconductor structure layer 200 may include the following process: first, an insulating layer is added to the top layer of the second semiconductor structure layer 200 to provide protection, then the bottom substrate is thinned and removed to expose the buried oxide layer (BOX), and then a bonding dielectric layer is added to the bottom of the buried oxide layer, thereby forming the following. Figure 9B Then the insulating layer is stripped off and removed, and the first semiconductor structure layer 100 and the second semiconductor structure layer 200 are aligned and bonded, as shown in FIG. Figure 9C As shown. Figure 9D As shown, a second source connection structure 270 and a second drain connection structure 280 are formed for the second semiconductor structure layer 200, wherein the second drain connection structure 280 is aligned with the first drain connection structure 180, and a connection groove is formed through the second semiconductor structure layer, and a metal connection structure 290 is formed therein to connect the second drain connection structure 280 with the first drain connection structure 180.

[0064] It should be understood that the above description is based on the inverter semiconductor device of PFET on NFET. Those skilled in the art can understand that if other semiconductor devices or other forms of inverter semiconductor devices are to be implemented, the formation of the first conductive channel, the second conductive channel, and the setting of the source region / drain region will be adjusted accordingly.

[0065] In the above embodiment, for the CFET inverter, the first source connection structure, i.e., the first interconnection structure, can be grounded as the source power supply VSS, and the second source connection structure, i.e., the third interconnection structure, can be connected to the power supply as the drain power supply VDD. The two are stacked vertically to reduce the occupied area. Figure 1 shown.

[0066] As used herein, a "dummy" structure such as a dummy gate is understood to refer to a structure that is used to simulate the physical characteristics of another structure (e.g., such as simulating the physical dimensions of a trench, gate, and / or other structure) and is a non-functional circuit (i.e., not part of the circuit current path) in the final manufactured device. In various embodiments, the "dummy" structure may include a single layer or a combination of multiple layers.

[0067] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, their practical applications, or technical improvements in the marketplace, or to enable other persons skilled in the art to understand the embodiments disclosed herein. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that: The invention comprises a first semiconductor structure layer and a second semiconductor structure layer bonded together, wherein the first semiconductor structure layer comprises a first surface (100A) of a first orientation and a second surface (100B) of a second orientation opposite to the first surface (100A), and the second semiconductor structure layer (200) comprises a third surface (200A) of a first orientation and a fourth surface (200B) of a second orientation opposite to the third surface (200A); The first semiconductor structure layer includes a first substrate, at least one first active region formed on the first surface of the first substrate (100), a first gate structure formed on the first active region, a first doping region (112) and a second doping region (113) of a first conductivity type formed at positions on both sides of the first gate structure; and a first interconnect structure (170) extending from the second surface (100B) and electrically connected to the first doping region (112), and a first interconnect structure (170) extending from the first surface (100A) and electrically connected to the second a second interconnect structure (180) of the doped region (113); The second semiconductor structure layer includes a second substrate (200), at least one second active region formed on the second substrate on the third surface, a second gate structure formed on each second active region, and a third doping region and a fourth doping region of a second conductivity type different from the first conductivity type formed on both sides of the second gate structure; further comprising a third interconnect structure (270) extending from a side of the fourth surface (200A) and electrically connected to the third doping region (212), and a fourth interconnect structure (280), the fourth interconnect structure extending from the third surface (200A) and electrically connected to the fourth doping region (213); wherein the fourth surface of the second semiconductor structure layer is bonded to the first surface of the first semiconductor structure layer, and the fourth interconnect structure (280) passes through the second semiconductor structure layer and is electrically connected to the second interconnect structure (180).

2. The semiconductor structure according to claim 1, wherein: The first interconnect structure comprises a first buried power rail (172) and a first contact portion (171) electrically connected to a first doped region, wherein a first contact doped region is provided at a position of the first substrate corresponding to the first buried power rail (172), and the first contact doped region has a second conductivity type different from the first conductivity type.

3. A semiconductor structure, characterized in that: The invention comprises a first semiconductor structure layer and a second semiconductor structure layer bonded together, wherein the first semiconductor structure layer comprises a first surface (100A) of a first orientation and a second surface (100B) of a second orientation opposite to the first surface (100A), and the second semiconductor structure layer (200) comprises a third surface (200A) of a first orientation and a fourth surface (200B) of a second orientation opposite to the third surface (200A); The first semiconductor structure layer comprises a first substrate (100), at least one first active region formed on the first surface of the first substrate (100), a first gate structure formed on each of the first active regions, and first doping regions (112) and second doping regions (113) of a first conductivity type formed on both sides of the first gate structure. doped region (113); further comprising a first interconnect structure (170) extending from the second surface (100B) and electrically connected to the first doped region (112), and a second interconnect structure (180) extending from the first surface (100A) and electrically connected to the second doped region (113); The second semiconductor structure layer comprises a second substrate (200), at least one second active region formed on the second substrate on the third surface, a second gate structure formed on each of the second active regions, and a third doping region and a fourth doping region of a second conductivity type different from the first conductivity type formed on both sides of the second gate structure; further comprising a third interconnect structure (270) extending from the fourth surface (200A) to and electrically connected to the third doping region (212), and a fourth interconnect structure (280) extending from the third surface (200B) to and electrically connected to the fourth doping region (213); The third surface of the second semiconductor structure layer is bonded to the first surface of the first semiconductor structure layer, and after bonding, the fourth interconnection structure (280) is electrically connected to the second interconnection structure (180).

4. The semiconductor structure according to claim 3, wherein: The first interconnect structure comprises a first buried power rail (172) and a first contact portion (171) electrically connected to the first doping region, a first contact doping region is provided at a position of the first substrate corresponding to the first buried power rail (172), and the first contact doping region has a second conductivity type different from the first conductivity type; the third interconnect structure comprises a second buried power rail (272) and a second contact portion (271) electrically connected to the third doping region, a second contact doping region is provided at a position of the second substrate corresponding to the second buried power rail (272), and the second contact doping region has a first conductivity type different from the second conductivity type.

5. The semiconductor structure according to claim 3, wherein: When the first semiconductor structure layer and the second semiconductor structure layer are configured to be bonded together, the fourth interconnect structure and the second interconnect structure are bonded facing each other to form a direct electrical connection.

6. A method for manufacturing a semiconductor structure, characterized in that: Including steps: A first substrate for forming a first semiconductor structure layer is provided, at least one mutually isolated first active region is formed in the first substrate from a first surface of the first substrate; a first gate structure is formed on each of the first active regions; a first deep trench is formed by etching on one side of the first gate structure; a first sacrificial material portion is formed by epitaxially growing a sacrificial material in the first deep trench; a first doped region trench and a second doped region trench are formed on both sides of the first gate structure, respectively, wherein the first doped region trench is connected to the first sacrificial material portion; a doped epitaxial layer of a first conductivity type is formed in the first doped region trench and the second doped region trench, respectively, to grow a first doped region and a second doped region to form the first semiconductor structure layer; forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; A second substrate for forming a second semiconductor structure layer is bonded to the surface of the first substrate where the second interconnect structure is located; at least one second active region is formed on the second substrate, a second gate structure is formed in each of the second active regions, and a third doped region and a fourth doped region of a second conductivity type different from the first conductivity type are formed on both sides of the second gate structure; forming a third interconnect structure electrically connected to the third doped region and a fourth interconnect structure electrically connected to the fourth doped region, respectively; wherein forming the fourth interconnect structure comprises etching the second semiconductor structure layer to form a fourth contact hole connecting the fourth doped region and the second interconnect structure; After any one of the above steps, the first sacrificial material portion is exposed from the second surface of the first substrate; a first contact hole is formed on the first sacrificial material portion; the first sacrificial material portion is removed; and the first contact hole and the first deep trench are filled to form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region to form the first semiconductor structure layer.

7. A method for manufacturing a semiconductor structure, characterized in that: Including steps: A first substrate for forming a first semiconductor structure layer is provided. At least one mutually isolated first active region is formed in the first substrate from a first surface of the first substrate, and a first gate structure is formed on each first active region. A first deep trench is formed by etching on one side of the first gate structure. A first sacrificial material portion is formed by epitaxially growing a sacrificial material in the first deep trench. A first doped region trench and a second doped region trench are formed on both sides of the first gate structure, respectively, wherein the first doped region trench is connected to the first sacrificial material portion. A doped epitaxial layer of a first conductivity type is formed in the first doped region trench and the second doped region trench, respectively, to grow a first doped region and a second doped region. forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; Providing a second substrate for forming a second semiconductor structure layer, forming a buried oxide layer on the second substrate, forming at least one second active region on the buried oxide layer, and forming a second gate structure on each of the second active regions; forming a third doping region and a fourth doping region of a second conductivity type different from the first conductivity type on both sides of the second gate structure; forming a third interconnect structure and a fourth interconnect structure connecting the third doping region and the fourth doping region, respectively, from a third surface of the second semiconductor structure layer to form the second semiconductor structure layer, wherein the fourth interconnect structure forms the second semiconductor structure layer based on the fourth contact hole etched into the fourth doping region; Thinning the second substrate to expose the buried oxide layer, adding a bonding dielectric layer to the buried oxide layer, bonding the second semiconductor structure layer to one side of the second interconnect structure of the first substrate through the bonding dielectric layer, forming a metal connection groove penetrating the second semiconductor structure layer, and forming a metal connection structure therein to electrically connect the second interconnect structure and the fourth interconnect structure; and After any one of the above steps, exposing the first sacrificial material portion from the second surface of the first substrate; forming a first contact hole on the first sacrificial material portion; The first sacrificial material portion is removed; the first contact hole and the first deep trench are filled to form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region to form the first semiconductor structure layer.

8. A method for manufacturing a semiconductor structure, characterized in that: Including steps: A first substrate for forming a first semiconductor structure layer is provided. At least one mutually isolated first active region is formed in the first substrate from a first surface of the first substrate, and a first gate structure is formed on each first active region. A first deep trench is formed by etching on one side of the first gate structure. A first sacrificial material portion is formed by epitaxially growing a sacrificial material in the first deep trench. A first doped region trench and a second doped region trench are formed on both sides of the first gate structure, respectively, wherein the first doped region trench is connected to the first sacrificial material portion. A doped epitaxial layer of a first conductivity type is formed in the first doped region trench and the second doped region trench, respectively, to grow a first doped region and a second doped region to form the first semiconductor structure layer. forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; forming a buried oxide layer on a second substrate for forming a second semiconductor structure layer, forming at least one second active region on the buried oxide layer, and forming a second gate structure on each of the second active regions; forming a third doping region and a fourth doping region of a second conductivity type different from the first conductivity type on both sides of the second gate structure; Thinning the second substrate to expose the buried oxide layer, adding a bonding dielectric layer to the buried oxide layer, and bonding the second semiconductor structure layer to one side of the second interconnect structure of the first substrate through the bonding dielectric layer; forming a third interconnect structure electrically connected to the third doped region and forming a fourth interconnect structure electrically connected to the fourth doped region and the second interconnect structure to form a second semiconductor structure layer, wherein forming the fourth interconnect structure includes etching the second semiconductor structure layer to form a fourth contact hole connected to the second interconnect structure; After any of the above steps, exposing the first sacrificial material portion from the second surface of the first substrate; forming a first contact hole on the first sacrificial material portion; The first sacrificial material portion is removed; the first contact hole and the first deep trench are filled to form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region to form the first semiconductor structure layer.

9. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: The forming of the first sacrificial material portion includes etching the first surface of the first active region to the bottom of the shallow trench isolation to form a first deep trench; and forming the first sacrificial material portion by epitaxially growing silicon germanium material in the first deep trench.

10. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: Forming the first interconnect structure includes processing the second surface of the first active area until the first sacrificial material portion is exposed; forming a first buried power rail isolation layer; opening a hole in the first buried power rail isolation layer and performing ion implantation to form a first contact implantation region of a second conductivity type; patterning the contact hole and etching the first sacrificial material portion to form the first deep trench; The contact hole and the first deep trench are metal-filled, silicide-formed, and planarized to form a first contact portion and the first buried power rail, thereby constituting the first interconnection structure.

11. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: Forming the fourth interconnection structure includes filling the fourth contact hole with metal, performing metal backetching so that the height of the metal layer in the fourth contact hole is reduced to below the height of the upper surface of the second gate but still covers the fourth doped region, and backfilling the fourth contact hole with insulating material to form the fourth interconnection structure.

12. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: The third interconnect structure and the fourth interconnect structure are formed in sequence.

13. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: Forming the second interconnect structure includes forming the second interconnect structure using a self-aligned contact process.

14. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein: Exposing the first sacrificial material portion includes thinning the first substrate as a whole or locally etching the position of the first sacrificial material portion of the first substrate using a through silicon via process.

15. A method for manufacturing a semiconductor structure, characterized in that: Including steps: A first substrate for forming a first semiconductor structure layer is provided, at least one mutually isolated first active region is formed in the first substrate, and a first gate structure is formed on each first active region; a first deep trench is formed by etching on one side of the first gate structure; a first sacrificial material portion is formed by epitaxially growing a sacrificial material in the first deep trench; a first doped region trench and a second doped region trench are formed on both sides of the first gate structure, respectively, wherein the first doped region trench is connected to the first sacrificial material portion; and a doped epitaxial layer of a first conductivity type is formed in the first doped region trench and the second doped region trench, respectively, to grow a first doped region and a second doped region. forming a second contact hole extending from the first surface to the second doped region, and filling the second contact hole to form a second interconnect structure electrically connected to the second doped region; Providing a second substrate for forming a second semiconductor structure layer, forming at least one mutually isolated second active region in the second substrate, and forming a second gate structure on each second active region; etching to form a second deep trench on one side of the second gate structure; forming a second sacrificial material portion by epitaxially growing a sacrificial material in the second deep trench; forming a third doping region trench and a fourth doping region trench on both sides of the second gate structure, respectively, wherein the third doping region trench is connected to the second sacrificial material portion; and forming a doped epitaxial layer of a second conductivity type different from the first conductivity type in the third doping region trench and the fourth doping region trench, respectively, to grow a third doping region and a fourth doping region; forming a third contact hole extending from the third surface to the third doped region, and filling the third contact hole to form a third interconnect structure electrically connected to the third doped region; After any of the above steps, exposing the first sacrificial material portion from the second surface of the first substrate; forming a first contact hole on the first sacrificial material portion; removing the first sacrificial material portion; filling the first contact hole and the first deep trench to form a first interconnect structure, wherein the metal in the first contact hole forms a first buried power rail and the metal in the first deep trench forms a first contact portion connecting the first buried power rail and the first doped region; After any of the above steps, the second sacrificial material portion is exposed from the fourth surface of the second substrate; a third contact hole is formed on the second sacrificial material portion; the second sacrificial material portion is removed; and the third contact hole and the second deep trench are filled to form a third interconnect structure, wherein the metal in the third contact hole forms a second buried power rail and the metal in the second deep trench forms a third contact portion connecting the second buried power rail and the third doped region.

16. The method for manufacturing a semiconductor structure according to claim 12, wherein: in, Forming the first sacrificial material portion includes performing deep trench etching in the first active area to form a first deep trench at the bottom of the first shallow trench isolation; forming the first sacrificial material portion by epitaxially growing silicon germanium material in the first deep trench; forming the second sacrificial material portion includes performing deep trench etching in the second active area to form a second deep trench at the bottom of the second shallow trench isolation; and forming the second sacrificial material portion by epitaxially growing silicon germanium material in the second deep trench.

17. The method for manufacturing a semiconductor structure according to claim 12, wherein: Forming the first interconnect structure includes processing the first active area until the first sacrificial material portion is exposed; forming a first isolation layer; opening the first isolation layer and performing ion implantation of a second conductivity type to form a first contact implantation area; performing contact hole patterning and etching the first sacrificial material portion to form a first contact hole; The first contact hole and the first deep trench are metal-filled, silicide-formed, and planarized to form a first interconnect structure; forming the third interconnect structure includes processing the second active area until the second sacrificial material portion is exposed; forming a second isolation layer; opening a hole in the second isolation layer and implanting ions of the first conductivity type to form a second contact implantation region; patterning the contact hole and etching the second sacrificial material portion to form a second contact hole; The second contact hole and the second deep trench are filled with metal, silicide is formed, and planarization is performed to form a third interconnection structure.

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