Modulator and electronic equipment

Abstract

The embodiment of the invention provides a modulator and electronic equipment, the modulator comprises a quantizer, a selection circuit and a second-stage comparator, the quantizer comprises a plurality of first-stage comparators, and the first-stage comparators are used for receiving a signal of a first clock when the signal of the first clock is converted from a low-level signal to a high-level signal. Acquiring an analog signal of an input signal port, and determining a first comparison result corresponding to the first-stage comparator according to the analog signal and a first reference signal value corresponding to the first-stage comparator; the selection circuit is used for determining a second reference signal value corresponding to the second-stage comparator according to the first comparison results corresponding to the plurality of first-stage comparators respectively; the second-stage comparator is used for determining a second comparison result of the second-stage comparator according to the analog signal and a second reference signal value, the second comparison result is used for determining a digital signal corresponding to the analog signal, and the accuracy of the analog-to-digital converter is improved under the condition that the chip area and the efficacy overhead are relatively saved.

Description

Technical Field

[0001] The present application belongs to the technical field of communications, and specifically relates to a modulator and an electronic device. Background Art

[0002] With the continuous advancement of communication technology, high-speed communication systems are placing increasingly stringent demands on signal processing. As a crucial component for digitizing analog signals in communication systems, the performance of analog-to-digital converters (ADCs) directly impacts the quality of the entire communication link. For example, continuous-time sigma-delta ADCs (ADCs) are widely used in various communication systems due to their high sampling rate and high resolution.

[0003] Currently, under limited oversampling rates, the quantization accuracy of the analog-to-digital converter can be improved in the following ways: 1. Increasing the out-of-band noise gain by fitting an aggressive noise transfer function (NTF) can improve quantization accuracy while maintaining low in-band noise, but this will increase the power consumption of the integrator and increase the system's sensitivity to jitter and inter-symbol interference; 2. Increasing the number of modulator stages and relying on more cascaded integrators to reduce quantization noise will reduce system stability due to the introduction of additional delays; 3. Increasing the number of quantizer bits to reduce out-of-band noise and improve the signal-to-noise ratio, but as the number of quantization bits increases, the number of comparators increases exponentially, resulting in a significant increase in chip area and power consumption.

[0004] When improving the quantization accuracy of the analog-to-digital converter, there is a contradiction between accuracy and power consumption and chip area, which makes it impossible to improve the accuracy of the analog-to-digital converter while saving chip area and power consumption. Summary of the Invention

[0005] Embodiments of the present application relate to a modulator and an electronic device to address the defect in the prior art that the accuracy of an analog-to-digital converter cannot be improved while saving chip area and power consumption.

[0006] In a first aspect, an embodiment of the present application provides a modulator, the modulator including a quantizer, a selection circuit, and a second-stage comparator, the quantizer including a plurality of first-stage comparators, the plurality of first-stage comparators being arranged in the modulator in ascending order according to the corresponding first reference signal values, the first-stage comparators being connected to an input signal port and a first clock, wherein:

[0007] The first-stage comparator is configured to obtain an analog signal from the input signal port when the signal of the first clock is converted from a low-level signal to a high-level signal, and determine a first comparison result corresponding to the first-stage comparator according to the analog signal and a first reference signal value corresponding to the first-stage comparator;

[0008] The selection circuit is used to determine the second reference signal value corresponding to the second-stage comparator according to the first comparison results respectively corresponding to the plurality of first-stage comparators;

[0009] The second-stage comparator is used to determine a second comparison result of the second-stage comparator according to the analog signal and the second reference signal value, and the second comparison result is used to determine a digital signal corresponding to the analog signal.

[0010] In one possible implementation, the selection circuit includes a plurality of AND gates and a plurality of first switches, the first-stage comparator includes a non-inverting output port and an inverting output port, the first comparison result includes a first non-inverting result and a first inverting result, the first non-inverting result is a result output by the non-inverting output port, and the first inverting result is a result output by the inverting output port;

[0011] The selection circuit is specifically configured to generate a plurality of switch trigger signals respectively through a plurality of AND gates according to a plurality of first in-phase results and a plurality of first inverted results, wherein the switch trigger signals include a high-level signal and a low-level signal; determine a target switch among the plurality of first switches in which the switch trigger signal is a high-level signal, and determine the to-be-selected reference signal value corresponding to the target switch as the second reference signal value.

[0012] In a possible implementation, for any adjacent first comparator and second comparator among the plurality of first-stage comparators, a first reference signal value corresponding to the first comparator is greater than a first reference signal value corresponding to the second comparator;

[0013] The input port of the AND gate is connected to the inverting output port of the first comparator and the non-inverting output port of the second comparator respectively, and the output port of the AND gate is connected to the control port of the first switch;

[0014] One end of the first switch is connected to the signal end corresponding to the reference signal value to be selected, and the other end of the first switch is connected to the reference signal end of the second-stage comparator, and the reference signal value to be selected is between the first reference signal value corresponding to the first comparator and the first reference signal value corresponding to the second comparator.

[0015] In a possible implementation, the AND gate is configured to determine a switch trigger signal generated by an output port of the AND gate according to an inverting output result of the first comparator and a non-inverting output result of the second comparator;

[0016] The first switch is used to control the connection relationship between the signal terminal corresponding to the to-be-selected reference signal value and the reference signal terminal of the second-stage comparator according to the switch trigger signal, so as to determine the second reference signal value corresponding to the second-stage comparator.

[0017] In one possible embodiment, the first-stage comparator is specifically used to determine whether the signal value corresponding to the analog signal is greater than the first reference signal value; if so, the first comparison result of the first-stage comparator is determined to include: the first in-phase result is a high-level signal, and the first inverted result is a low-level signal; if not, the first comparison result of the first-stage comparator is determined to include: the first in-phase result is a low-level signal, and the first inverted result is a high-level signal.

[0018] In a possible implementation, the modulator further includes an OR gate, wherein two input ports of the OR gate are respectively connected to a non-inverting output port and an inverting output port of any one of the first-stage comparators, and an output port of the OR gate is connected to a clock signal port of the second-stage comparator;

[0019] The OR gate is used to provide a second clock signal to the second-stage comparator.

[0020] In one possible implementation, the second-stage comparator is specifically configured to obtain an analog signal through the second-stage comparator when the second clock signal changes from a low-level signal to a high-level signal; and determine a second comparison result of the second-stage comparator based on the analog signal obtained by the second-stage comparator and the second reference signal value.

[0021] In a possible implementation, the second-stage comparator further includes a first capacitor and a second switch, wherein a first end of the second switch is connected to a port corresponding to the analog signal, a second end of the second switch is connected to a signal input port of the second-stage comparator, a trigger port of the second switch is connected to a NOT gate of a first clock, one end of the first capacitor is connected to the second end of the second switch, and the other end of the first capacitor is connected to a ground line.

[0022] In a possible implementation, obtaining the analog signal through the second-stage comparator includes:

[0023] In response to the first clock signal switching from a high-level signal to a low-level signal, controlling the second switch to be in a connected state so that the port corresponding to the analog signal charges the first capacitor and the second-stage comparator obtains a signal value corresponding to the analog signal, or

[0024] In response to the first clock signal switching from a low-level signal to a high-level signal, the second switch is controlled to be in an off state so that the first capacitor discharges to the signal input port of the second-stage comparator, so that the second-stage comparator obtains the signal value corresponding to the analog signal.

[0025] In a second aspect, the present application provides a chip, comprising a modulator as described in any one of the first aspects.

[0026] In a third aspect, the present application provides a chip module, comprising a modulator as described in any one of the first aspects.

[0027] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a modulator as described in any one of the first aspects.

[0028] The present application provides a modulator and an electronic device, wherein the modulator includes a quantizer, a selection circuit, and a second-stage comparator, wherein the quantizer includes a plurality of first-stage comparators, the plurality of first-stage comparators being arranged in ascending order of corresponding first reference signal values ​​in the modulator, the first-stage comparator being connected to an input signal port and a first clock, wherein the first-stage comparator is configured to obtain an analog signal from the input signal port when a signal received by the first clock is converted from a low-level signal to a high-level signal, and to determine a first comparison result corresponding to the first-stage comparator based on the analog signal and the first reference signal value corresponding to the first-stage comparator; the selection circuit is configured to determine a second reference signal value corresponding to the second-stage comparator based on the first comparison results respectively corresponding to the plurality of first-stage comparators; the second-stage comparator is configured to determine a second comparison result of the second-stage comparator based on the analog signal and the second reference signal value, and the second comparison result is used to determine a digital signal corresponding to the analog signal. In this way, by adding one comparator and a small amount of logic circuitry, quantization of one more bit can be achieved, thereby improving the accuracy of the analog-to-digital converter while relatively saving chip area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in this application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A schematic structural diagram of an analog-to-digital converter provided in an embodiment of the present application;

[0031] Figure 2 A schematic structural diagram of a modulator provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of a selection circuit provided in an embodiment of the present application;

[0033] Figure 4 A schematic structural diagram of a second-stage comparator provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0035] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] It should be noted that although the terms "first" and "second" are used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from each other. Alternatively, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0038] It should be understood that the terms "comprise" and "include" indicate the presence of the previously mentioned features, steps, or operations, but do not exclude the presence, occurrence, or addition of one or at least one other feature, step, or operation. The terms "and / or" and the like used in this application may be interpreted as inclusive, or may mean any one or any combination. Alternatively, "A and / or B" means "any of the following: A; B; A and B." In addition, the character " / " in this document generally indicates that the preceding and following objects are in an "or" relationship.

[0039] With the continuous advancement of communication technology, high-speed communication systems are placing increasingly stringent demands on signal processing. As a crucial component for digitizing analog signals in communication systems, the performance of analog-to-digital converters (ADCs) directly impacts the quality of the entire communication link. For example, continuous-time sigma-delta ADCs (ADCs) are widely used in various communication systems due to their high sampling rate and high resolution.

[0040] Currently, under limited oversampling rates, the quantization accuracy of the analog-to-digital converter can be improved in the following ways: 1. Increasing the out-of-band noise gain by fitting an aggressive noise transfer function (NTF) can improve quantization accuracy while maintaining low in-band noise, but this will increase the power consumption of the integrator and increase the system's sensitivity to jitter and inter-symbol interference; 2. Increasing the number of modulator stages and relying on more cascaded integrators to reduce quantization noise will reduce system stability due to the introduction of additional delays; 3. Increasing the number of quantizer bits to reduce out-of-band noise and improve the signal-to-noise ratio, but as the number of quantization bits increases, the number of comparators increases exponentially, resulting in a significant increase in chip area and power consumption.

[0041] When improving the quantization accuracy of the analog-to-digital converter, there is a contradiction between accuracy and power consumption and chip area, which makes it impossible to improve the accuracy of the analog-to-digital converter while saving chip area and power consumption.

[0042] Next, combine Figure 1 , the existing analog-to-digital converter is explained.

[0043] Figure 1 This is a schematic diagram of the structure of an analog-to-digital converter provided in an embodiment of the present application. Figure 1 , Figure 1 An analog-to-digital converter may be included. The analog-to-digital converter may be a 4-bit flash analog-to-digital converter. The analog-to-digital converter may include 16 comparators.

[0044] The comparator may include an input signal port, a reference signal port, a clock signal port, a non-inverting output port, and an inverting output port.

[0045] The input signal port can be connected to an input signal, which can be a quantized analog signal.

[0046] like Figure 1 As shown, the input signal is Vip.

[0047] The reference signal port can be connected to the signal port corresponding to the reference signal value. The reference signal values ​​corresponding to the 16 comparators can be arranged in equal intervals from small to large. The reference signal can be used to compare with the input signal to achieve quantization of the input signal.

[0048] like Figure 1 As shown, 16 comparators are arranged in sequence, and the reference signal terminals corresponding to the 16 comparators are Vref <0> 、Vref <1> ,……,Vref <15> , Vref <0> to Vref <15> The corresponding reference signal values ​​are increased by the preset values ​​in sequence.

[0049] The clock signal port can be used to control the comparator to compare the input signal with the reference signal value corresponding to the comparator at the appropriate time, synchronize the entire quantization process, and ensure that the comparison operation is carried out in an orderly and accurate manner.

[0050] like Figure 1 As shown, the clock signal is φc.

[0051] The non-inverting output port and the inverting output port can be used to output the comparison result between the input signal and the reference signal value of the comparator.

[0052] like Figure 1 As shown, the non-inverting output ports corresponding to the 16 comparators are Voutp <0> 、Voutp <1> ,……,Voutp <15> , the inverting output ports corresponding to the 16 comparators are Voutn <0> 、Voutn <1> 、……、Voutn <15> .

[0053] When the input signal Vip is greater than the reference voltage Vref, the in-phase output port outputs a high level signal and the inverting output port outputs a low level signal. When the input signal Vip is less than the reference voltage Vref, the in-phase output port outputs a low level signal and the inverting output port outputs a high level signal.

[0054] If a 4-bit flash ADC is upgraded to a 5-bit flash ADC, 16 additional comparators are needed to achieve the extra bit of quantization. The higher the number of quantization bits, the more comparators are needed, which in turn requires a larger area.

[0055] To solve the above technical problems, an embodiment of the present application provides a modulator that adds a selection circuit and a second-stage comparator. The selection circuit is used to determine the reference signal value corresponding to the second-stage comparator based on the first comparison results corresponding to multiple first-stage comparators. The second-stage comparator is used to determine the comparison result of the second comparator based on the analog signal and the reference signal value corresponding to the second-stage comparator. The comparison result of the second comparator is used to determine the digital signal corresponding to the analog signal. In this way, by adding a comparator and a small amount of logic circuitry, quantization of one more bit can be achieved, thereby improving the accuracy of the analog-to-digital converter while relatively saving chip area and power consumption.

[0056] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0057] Example 1

[0058] Figure 2This is a schematic diagram of the structure of a modulator provided in an embodiment of the present application. Figure 2 , Figure 2 At least a modulator is included.

[0059] The modulator includes a quantizer, a selection circuit, and a second-stage comparator. The quantizer includes a plurality of first-stage comparators. The plurality of first-stage comparators are arranged in the modulator in ascending order according to the corresponding first reference signal values. The first-stage comparators are connected to the input signal port and the first clock, wherein:

[0060] The first-stage comparator is configured to obtain an analog signal from the input signal port when the signal of the first clock is converted from a low-level signal to a high-level signal, and determine a first comparison result corresponding to the first-stage comparator according to the analog signal and a first reference signal value corresponding to the first-stage comparator;

[0061] The selection circuit is used to determine the second reference signal value corresponding to the second stage comparator according to the first comparison results respectively corresponding to the plurality of first stage comparators;

[0062] The second-stage comparator is used to determine a second comparison result of the second-stage comparator according to the analog signal and the second reference signal value, and the second comparison result is used to determine a digital signal corresponding to the analog signal.

[0063] The quantizer may be used to map the amplitude of the continuous analog signal obtained by sampling into a plurality of discrete digital level signals, ie, the first comparison results corresponding to the plurality of first-stage comparators.

[0064] The first-stage comparator includes a non-inverting output port and an inverting output port.

[0065] The first comparison result may include a first in-phase result and a first inverted result.

[0066] The first in-phase result is the result output by the in-phase output port.

[0067] The first inversion result is the result outputted by the inversion output port.

[0068] The first in-phase result may include a high level signal and a low level signal.

[0069] The first inversion result may include a high level signal and a low level signal.

[0070] Optionally, the selection circuit is specifically used to generate multiple switch trigger signals through multiple AND gates based on multiple first in-phase results and multiple first inverted results, and the switch trigger signals include high-level signals and low-level signals; determine the target switch whose switch trigger signal is a high-level signal among the multiple first switches, and determine the selected reference signal value corresponding to the target switch as the second reference signal value.

[0071] Optionally, the first-stage comparator is specifically used to determine whether the signal value corresponding to the analog signal is greater than the first reference signal value; if so, the first comparison result of the first-stage comparator is determined to include: the first in-phase result is a high-level signal, and the first inverted result is a low-level signal; if not, the first comparison result of the first-stage comparator is determined to include: the first in-phase result is a low-level signal, and the first inverted result is a high-level signal.

[0072] A plurality of first-stage comparators are arranged in the modulator in ascending order of corresponding first reference signal values, and the first reference signal values ​​corresponding to two adjacent first-stage comparators differ by a preset value.

[0073] The first-stage comparator may be connected to an input signal port, and the input signal port may be used to provide an analog signal to be converted.

[0074] The first-stage comparators may be connected to a first clock, and the first clock may be used to control the timings at which the plurality of first-stage comparators perform quantization.

[0075] The selection circuit is used to determine the second reference signal value corresponding to the second stage comparator from a plurality of reference signal values ​​to be selected.

[0076] Optionally, the selection circuit may include multiple AND gates and multiple first switches. The selection circuit may also be any logic circuit for determining the second reference signal value corresponding to the second-stage comparator from multiple reference signal values ​​to be selected, which is not limited here.

[0077] The second-stage comparator can be connected to the input signal port.

[0078] The input signal port to which the second-stage comparator is connected is the same as the input signal port to which the plurality of first-stage comparators are connected.

[0079] Optionally, the second-stage comparator is specifically used to determine whether the signal value corresponding to the analog signal is greater than the second reference signal value; if so, the second comparison result of the second-stage comparator is determined to include: the second in-phase result is a high-level signal, and the second inverted result is a low-level signal; if not, the second comparison result of the second-stage comparator is determined to include: the second in-phase result is a low-level signal, and the second inverted result is a high-level signal.

[0080] This embodiment provides a modulator comprising a quantizer, a selection circuit, and a second-stage comparator. The quantizer comprises a plurality of first-stage comparators, which are arranged in ascending order of corresponding first reference signal values ​​in the modulator. The first-stage comparator is connected to an input signal port and a first clock. The first-stage comparator is configured to obtain an analog signal from the input signal port upon receiving the first clock signal, when the signal is converted from a low-level signal to a high-level signal, and to determine a first comparison result corresponding to the first-stage comparator based on the analog signal and the first reference signal value corresponding to the first-stage comparator. The selection circuit is configured to determine a second reference signal value corresponding to the second-stage comparator based on the first comparison results respectively corresponding to the plurality of first-stage comparators. The second-stage comparator is configured to determine a second comparison result of the second-stage comparator based on the analog signal and the second reference signal value, and the second comparison result is used to determine a digital signal corresponding to the analog signal. In this way, by adding one comparator and a small amount of logic circuitry, quantization of one more bit can be achieved, thereby improving the accuracy of the analog-to-digital converter while relatively saving chip area and power consumption.

[0081] Example 2

[0082] Figure 3 This is a schematic diagram of a selection circuit provided in an embodiment of the present application. Figure 3 , Figure 3 The system at least comprises a plurality of first-stage comparators and a selection circuit, wherein the selection circuit comprises a plurality of AND gates and a plurality of first switches.

[0083] For any adjacent first comparator and second comparator in the plurality of first-stage comparators, a first reference signal value corresponding to the first comparator is greater than a first reference signal value corresponding to the second comparator;

[0084] The input port of the AND gate is connected to the inverting output port of the first comparator and the non-inverting output port of the second comparator respectively, and the output port of the AND gate is connected to the control port of the first switch;

[0085] One end of the first switch is connected to the signal end corresponding to the reference signal value to be selected, and the other end of the first switch is connected to the reference signal end of the second-stage comparator. The reference signal value to be selected is between the first reference signal value corresponding to the first comparator and the first reference signal value corresponding to the second comparator.

[0086] The AND gate is used to determine the switch trigger signal generated by the output port of the AND gate according to the inverting output result of the first comparator and the non-inverting output result of the second comparator;

[0087] The first switch is used to control the connection relationship between the signal terminal corresponding to the reference signal value to be selected and the reference signal terminal of the second-stage comparator according to the switch trigger signal, so as to determine the second reference signal value corresponding to the second-stage comparator.

[0088] For example, suppose the analog signal corresponds to a value between Vref <0> The corresponding first reference signal value and Vref <1> The corresponding first reference signal value, Vref <1> The first comparison result of the corresponding first-stage comparator (the first comparator of the two adjacent first-stage comparators) is that the in-phase output port outputs a low-level signal and the inverting output port outputs a high-level signal; Vref <0> The first comparison result of the corresponding first-stage comparator (the second comparator in the two adjacent first-stage comparators) is that the in-phase output port outputs a high-level signal, and the inverting output port outputs a low-level signal;

[0089] Vref <1> —Vref <15> The first comparison results of the corresponding first-stage comparators are that the non-inverting output port outputs a low-level signal, and the inverting output port outputs a high-level signal.

[0090] The input ports of the first AND gate are connected to Vref <1> The corresponding first-stage comparator inverting output port and Vref <0> The corresponding non-inverting output port of the first-stage comparator, that is, the switch trigger signal generated by the AND gate is a high-level signal;

[0091] The i-th AND gate is connected to Vref<i+1> The corresponding first-stage comparator inverting output port and Vref The corresponding non-inverting output port of the first-stage comparator, where i ranges from 2 to 14, and the switch trigger signals generated by the i-th AND gate are all low-level signals.

[0092] The first switch connected to the first AND gate can control the connection between the signal terminal corresponding to the selected reference signal value corresponding to the first switch and the reference signal terminal of the second-stage comparator in response to the switch trigger signal being a high-level signal.

[0093] The reference signal value to be selected corresponding to the first switch is between Vref <0> The corresponding first reference signal value and Vref <1> The corresponding first reference signal values ​​are used as the second reference signal values ​​of the second-stage comparator to further quantize the analog signal.

[0094] In this way, multiple AND gates and multiple first switches can achieve quantization of more than 1 bit, thereby improving the accuracy of the analog-to-digital converter while relatively saving chip area and power consumption.

[0095] Example 3

[0096] In a possible implementation manner, the modulator further includes an OR gate.

[0097] Figure 4 This is a schematic diagram of the structure of a second-stage comparator provided in an embodiment of the present application. Figure 4 , Figure 4 It at least includes an OR gate and a second-stage comparator.

[0098] The two input ports of the OR gate are respectively connected to the in-phase output port and the inverting output port of any first-stage comparator, and the output port of the OR gate is connected to the clock signal port of the second-stage comparator.

[0099] The OR gate is used for providing a second clock signal to the second-stage comparator.

[0100] The second-stage comparator is specifically used to obtain an analog signal through the second-stage comparator when the second clock signal changes from a low-level signal to a high-level signal; and determine the second comparison result of the second-stage comparator based on the analog signal obtained by the second-stage comparator and the second reference signal value.

[0101] The OR operation between the first in-phase result and the first inverted result corresponding to the first-stage comparator is a high-level signal.

[0102] After the first-stage comparator performs the comparison process, the signal corresponding to the OR gate is converted from a low-level signal to a high-level signal, and the signal corresponding to the OR gate can be used as a clock signal for the second-stage comparator.

[0103] Among them, the two input ends of the second-stage comparator are respectively connected to the input signal port and the signal end corresponding to the second reference signal value, the second-stage comparator includes a non-inverting output port and an inverting output port, the non-inverting output port of the second-stage comparator is used to output the second non-inverting result, and the inverting output port of the second-stage comparator is used to output the second inverted result.

[0104] If the analog signal is greater than the second reference signal value, the second in-phase result is a high-level signal and the second inverted result is a low-level signal; if the analog signal is less than the second reference signal value, the second in-phase result is a low-level signal and the second inverted result is a high-level signal.

[0105] Optionally, the second-stage comparator also includes a first capacitor and a second switch, the first end of the second switch is connected to the port corresponding to the analog signal, the second end of the second switch is connected to the signal input port of the second-stage comparator, the trigger port of the second switch is connected to the NOT gate of the first clock, one end of the first capacitor is connected to the second end of the second switch, and the other end of the first capacitor is connected to the ground line.

[0106] The trigger signal of the second switch is a signal obtained by performing a negation operation on the first clock signal.

[0107] Optionally, obtaining an analog signal through a second-stage comparator includes:

[0108] In response to the first clock signal switching from a high level signal to a low level signal, the second switch is controlled to be in a connected state, so that the port corresponding to the analog signal charges the first capacitor, and the second-stage comparator obtains the signal value corresponding to the analog signal, or

[0109] In response to the first clock signal switching from a low level signal to a high level signal, the second switch is controlled to be in an off state, so that the first capacitor discharges to the signal input port of the second stage comparator, so that the second stage comparator obtains a signal value corresponding to the analog signal.

[0110] In this way, it is ensured that the analog signals acquired by the first-stage comparator and the second-stage comparator are the same analog signal, thereby avoiding sampling errors between the first-stage comparator and the second-stage comparator.

[0111] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 , Figure 5 It may include the modulator described in any one of the above embodiments.

[0112] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship; in the formula, the character " / " indicates that the previous and next associated objects are in a "division" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or plural.

[0113] It is understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. In the embodiments of the present application, the order of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A modulator, characterized in that: The modulator includes a quantizer, a selection circuit, and a second-stage comparator. The quantizer includes a plurality of first-stage comparators. The plurality of first-stage comparators are arranged in the modulator in ascending order according to the corresponding first reference signal values. The first-stage comparators are connected to the input signal port and the first clock, wherein: The first-stage comparator is configured to obtain an analog signal from the input signal port when the signal of the first clock is converted from a low-level signal to a high-level signal, and determine a first comparison result corresponding to the first-stage comparator according to the analog signal and a first reference signal value corresponding to the first-stage comparator; The selection circuit is used to determine the second reference signal value corresponding to the second-stage comparator according to the first comparison results respectively corresponding to the plurality of first-stage comparators; The second-stage comparator is used to determine a second comparison result of the second-stage comparator according to the analog signal and the second reference signal value, and the second comparison result is used to determine a digital signal corresponding to the analog signal.

2. The modulator according to claim 1, wherein The selection circuit includes a plurality of AND gates and a plurality of first switches, the first-stage comparator includes a non-inverting output port and an inverting output port, the first comparison result includes a first non-inverting result and a first inverting result, the first non-inverting result is the result output by the non-inverting output port, and the first inverting result is the result output by the inverting output port; The selection circuit is specifically configured to generate a plurality of switch trigger signals respectively through a plurality of AND gates according to a plurality of first in-phase results and a plurality of first inverted results, wherein the switch trigger signals include a high-level signal and a low-level signal; determine a target switch among the plurality of first switches in which the switch trigger signal is a high-level signal, and determine the to-be-selected reference signal value corresponding to the target switch as the second reference signal value.

3. The modulator according to claim 2, wherein: For any adjacent first comparator and second comparator in the plurality of first-stage comparators, a first reference signal value corresponding to the first comparator is greater than a first reference signal value corresponding to the second comparator; The input port of the AND gate is connected to the inverting output port of the first comparator and the non-inverting output port of the second comparator respectively, and the output port of the AND gate is connected to the control port of the first switch; One end of the first switch is connected to the signal end corresponding to the reference signal value to be selected, and the other end of the first switch is connected to the reference signal end of the second-stage comparator, and the reference signal value to be selected is between the first reference signal value corresponding to the first comparator and the first reference signal value corresponding to the second comparator.

4. The modulator according to claim 2, wherein: The AND gate is used to determine the switch trigger signal generated by the output port of the AND gate according to the inverting output result of the first comparator and the non-inverting output result of the second comparator; The first switch is used to control the connection relationship between the signal terminal corresponding to the to-be-selected reference signal value and the reference signal terminal of the second-stage comparator according to the switch trigger signal, so as to determine the second reference signal value corresponding to the second-stage comparator.

5. The modulator according to any one of claims 1 to 4, characterized in that The first-stage comparator is specifically configured to determine whether a signal value corresponding to the analog signal is greater than the first reference signal value; If so, it is determined that the first comparison result of the first-stage comparator includes: the first in-phase result is a high-level signal, and the first inverted result is a low-level signal; if not, it is determined that the first comparison result of the first-stage comparator includes: the first in-phase result is a low-level signal, and the first inverted result is a high-level signal.

6. The modulator according to any one of claims 1 to 4, characterized in that: The modulator further includes an OR gate, wherein two input ports of the OR gate are respectively connected to the in-phase output port and the inverting output port of any one of the first-stage comparators, and the output port of the OR gate is connected to the clock signal port of the second-stage comparator; The OR gate is used to provide a second clock signal to the second-stage comparator.

7. The modulator according to claim 6, wherein The second-stage comparator is specifically used to obtain an analog signal through the second-stage comparator when the second clock signal changes from a low-level signal to a high-level signal; and determine the second comparison result of the second-stage comparator based on the analog signal obtained by the second-stage comparator and the second reference signal value.

8. The modulator according to claim 7, wherein: The second-stage comparator also includes a first capacitor and a second switch, wherein the first end of the second switch is connected to the port corresponding to the analog signal, the second end of the second switch is connected to the signal input port of the second-stage comparator, the trigger port of the second switch is connected to the NOT gate of the first clock, one end of the first capacitor is connected to the second end of the second switch, and the other end of the first capacitor is connected to the ground line.

9. The modulator according to claim 8, wherein The analog signal is obtained through the second-stage comparator, including: In response to the first clock signal switching from a high-level signal to a low-level signal, controlling the second switch to be in a connected state so that the port corresponding to the analog signal charges the first capacitor and the second-stage comparator obtains a signal value corresponding to the analog signal, or In response to the first clock signal switching from a low-level signal to a high-level signal, the second switch is controlled to be in an off state so that the first capacitor discharges to the signal input port of the second-stage comparator, so that the second-stage comparator obtains the signal value corresponding to the analog signal.

10. An electronic device, characterized in that: The electronic device comprises a modulator according to any one of claims 1-9.

Images