Method for manufacturing printed wiring board

Abstract

The invention provides a method for manufacturing a printed wiring board. The printed wiring board has high quality. A method of manufacturing a printed wiring board according to an embodiment includes the steps of: forming a resin insulating layer; forming a protective film on the first surface of the resin insulating layer; forming an opening for a via conductor; removing the protective film; cleaning the first surface; forming a second conductor layer; and forming a via conductor. The resin insulating layer contains a resin and inorganic particles, and the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin. The cleaning comprises the step of forming the first inorganic particles from the second inorganic particles. The step of forming the second conductor layer includes: forming a seed layer on a first surface of the resin insulating layer; forming a plating resist on the seed layer using DI exposure; forming an electroplated layer; removing an anti-plating agent; and removing the seed layer exposed from the electroplated layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a printed wiring board. Background Art

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board. The examples in Patent Document 1 disclose a manufacturing method comprising the following steps: forming non-through holes in an insulating resin layer; forming fine irregularities on the surface of the insulating resin layer; forming a power supply layer using electroless copper plating; and forming a plating resist using a photomask. The plating resist is removed using an oxidizing agent.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2001-217526

[0004] [Problems of Patent Document 1]

[0005] According to the embodiment of patent document 1, the power supply layer (seed layer) is a chemically plated copper film formed on the surface of the insulating resin layer having projections and depressions. It is considered that the power supply layer follows the projections and depressions on the surface of the insulating resin layer. It can be considered that the upper surface of the power supply layer has projections and depressions. Due to the projections and depressions of the power supply layer, the embodiment of patent document 1 cannot reduce the transmission loss of the wiring. It can be considered that due to the projections and depressions on the upper surface of the power supply layer, the contact area between the photoresist used for forming the plating resist and the power supply layer is small. It is considered that the plating resist is peeled off from the power supply layer by development. It is considered that peeling is likely to occur particularly when the width of the plating resist is small. It is considered that the embodiment of patent document 1 has difficulty in forming fine wiring. Summary of the Invention

[0006] The present invention provides a method for manufacturing a printed wiring board, comprising the following steps: forming a resin insulating layer having a first surface and a second surface opposite the first surface on a first conductor layer; forming a protective film on the first surface of the resin insulating layer; forming an opening for a via conductor that penetrates both the protective film and the resin insulating layer and reaches the first conductor layer; removing the protective film from the resin insulating layer after forming the opening; cleaning the first surface of the resin insulating layer; forming a second conductor layer on the first surface of the resin insulating layer; and forming a via conductor in the opening that connects the first and second conductor layers. The resin insulating layer comprises resin and inorganic particles, the inorganic particles comprising first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles being approximately spherical in shape, and the second inorganic particles being approximately spherical in shape. Cleaning comprises the step of selectively removing the resin so that a portion of the second inorganic particles protrudes from the first surface of the resin insulating layer. By selectively removing the resin, the first inorganic particles are formed from the second inorganic particles. The first inorganic particles are formed of a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed of the upper surface of the resin and the exposed surface of the first portion that is exposed from the upper surface. The step of forming the second conductive layer includes the following steps: forming a seed layer on the first surface of the resin insulating layer by sputtering; forming a plating resist on the seed layer using DI exposure; forming an electroplating layer on the seed layer exposed from the plating resist; removing the plating resist; and removing the seed layer exposed from the electroplating layer.

[0007] According to the method for manufacturing a printed wiring board according to an embodiment of the present invention, almost no recess is formed on the first surface of the resin insulating layer. The first surface of the resin insulating layer has almost no recess. The upper surface of the seed layer formed by sputtering on the first surface of the resin insulating layer also has almost no recess. For example, when an electrical signal propagates in a signal wiring, the embodiment can reduce transmission loss. The embodiment can reduce transmission loss of the wiring. Since the seed layer is formed by sputtering, the bonding strength between the resin insulating layer and the seed layer is high. The conductor circuit is difficult to peel off from the resin insulating layer. Even if the thickness of the sputtering film is thin, the embodiment can form a continuous seed layer. When removing the seed layer, the embodiment can reduce the amount of etching used to remove the seed layer. In addition, since the upper surface of the seed layer has almost no recess, the embodiment can form a fine plating resist having a size close to the target value by using DI exposure. The embodiment can form fine signal wiring. The embodiment can form a high-quality printed wiring board. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1It is a cross-sectional view schematically showing a printed wiring board according to the embodiment.

[0009] Figure 2 This is an enlarged cross-sectional view schematically showing a portion of a printed wiring board according to the embodiment.

[0010] Figure 3 This is an enlarged cross-sectional view schematically showing a portion of a printed wiring board according to the embodiment.

[0011] Figure 4 This is an enlarged cross-sectional view schematically showing a portion of a printed wiring board according to the embodiment.

[0012] Figure 5 This is an enlarged cross-sectional view schematically showing a portion of a printed wiring board according to the embodiment.

[0013] Figure 6A It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0014] Figure 6B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0015] Figure 6C It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0016] Figure 6D It is an enlarged cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0017] Figure 6E It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0018] Figure 6F It is an enlarged cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0019] Figure 6G It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0020] Figure 7 It is an enlarged cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0021] Label Description

[0022] 2: printed wiring board; 4: insulating layer; 10: first conductor layer; 20: resin insulating layer; 22: first surface; 24: second surface; 26: opening; 27: inner wall surface; 30: second conductor layer; 30a: seed layer; 31a: first layer; 31b: second layer; 40: via conductor; 80: resin; 90: inorganic particles; 91: first inorganic particles; 92: second inorganic particles; 93: third inorganic particles. DETAILED DESCRIPTION

[0023] [Printed wiring board 2 according to the embodiment]

[0024] Figure 1 2 is a cross-sectional view showing a printed wiring board 2 according to the embodiment. Figures 2 to 5 1 is an enlarged cross-sectional view showing a portion of the printed wiring board 2 according to the embodiment. Figure 1 As shown, the printed wiring board 2 includes an insulating layer 4, a conductor layer (first conductor layer) 10, a resin insulating layer (first resin insulating layer) 20, a conductor layer (second conductor layer) 30, a via conductor 40, a resin insulating layer (second resin insulating layer) 120, a conductor layer (third conductor layer) 130, and a via conductor 140.

[0025] The insulating layer 4 is formed of a resin. The insulating layer 4 may also contain inorganic particles such as silicon dioxide. The insulating layer 4 may also contain a reinforcing material such as glass cloth. The insulating layer 4 has a third surface 6 and a fourth surface 8 opposite to the third surface 6.

[0026] The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes signal wiring 12 and pads 14. Although not shown in the figure, the first conductor layer 10 also includes a conductor circuit other than the signal wiring 12 and the pads 14. The first conductor layer 10 is mainly formed of copper. The first conductor layer 10 is formed by a seed layer 10a on the insulating layer 4 and a plating layer 10b on the seed layer 10a. The thickness of the seed layer 10a is less than 0.5μm. The seed layer 10a is formed by a first layer 11a on the third surface 6 and a second layer 11b on the first layer 11a. The first layer 11a is in contact with the insulating layer 4. The ratio of the thickness of the first layer 11a to the thickness of the second layer 11b (thickness of the first layer / thickness of the second layer) is greater than 0.25 and less than 0.7. The thickness of the second layer 11b is preferably thicker than the thickness of the first layer 11a.

[0027] The first layer 11a is formed of an alloy containing copper and a metal other than copper (copper alloy). For example, the first layer 11a is formed of an alloy containing copper and aluminum. The first layer 11a is formed of an alloy containing copper, aluminum and a specific metal. Examples of specific metals are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one specific metal, two specific metals, or three specific metals. An example of a specific metal is silicon. The aluminum content in the alloy is greater than 1.0 at% and less than 15.0 at%. When the alloy contains a specific metal, the specific metal content in the alloy is greater than 0.5 at% and less than 10.0 at%. The first layer 11a may also contain impurities. Examples of impurities are oxygen and carbon. The first layer 11a may contain oxygen or carbon. The first layer 11a may contain oxygen and carbon. In an embodiment, the alloy further contains carbon. The carbon content in the alloy is less than 50 ppm. The alloy further contains oxygen. The oxygen content in the alloy is less than 100 ppm. The values ​​of the contents of the above-mentioned elements are examples. Among the elements forming first layer 11a, copper is present in the largest amount. Next, aluminum is present in the largest amount. If the alloy contains a specific metal, the amount of the specific metal is smaller than that of aluminum. Therefore, copper is the primary metal, aluminum is the first secondary metal, and the specific metal is the second secondary metal. The amount of impurities is smaller than that of the specific metal.

[0028] The second layer 11b is formed of copper. The electroplated layer 10b is formed of copper.

[0029] The copper content of the copper alloy forming first layer 11a is greater than 90 at%. The copper content of the alloy is less than 99 at%. The copper content of the copper alloy is 98 at% or less. The copper content of second layer 11b is 99.9 at% or greater. The copper content of second layer 11b is preferably 99.95 at% or greater. Electroplated layer 10b is formed of copper. The copper content of electroplated layer 10b is 99.9 at% or greater. The copper content of electroplated layer 10b is preferably 99.95 at% or greater.

[0030] The resin insulating layer (first resin insulating layer) 20 is formed on the third surface 6 of the insulating layer 4 and the first conductive layer 10. The first resin insulating layer 20 has a first surface 22 and a second surface 24 opposite to the first surface 22. The second surface 24 of the first resin insulating layer 20 is opposite to the first conductive layer 10. The first resin insulating layer 20 has an opening (an opening for a via conductor) 26 that exposes the pad 14. The diameter of the bottom of the opening 26 is greater than or equal to 20 μm and less than or equal to 50 μm. The resin insulating layer (first resin insulating layer) 20 is formed from a resin 80 and a plurality of inorganic particles 90 dispersed within the resin 80. The resin 80 has an upper surface 80R and a lower surface 80S opposite to the upper surface 80R. The upper surface 80R forms the first surface 22, and the lower surface 80S forms the second surface 24. The resin 80 is an epoxy resin. Examples of the resin include thermosetting resins and photocurable resins. The inorganic particles 90 are, for example, glass particles or aluminum oxide particles. The inorganic particles 90 preferably contain oxygen. The average particle size of the inorganic particles 90 is 0.5 μm or less. The amount of the inorganic particles 90 in the resin insulating layer 20 is 75 wt % or more.

[0031] like Figure 1 and Figure 2 As shown, the inorganic particles 90 include first inorganic particles 91 partially embedded in the resin 80 and second inorganic particles 92 embedded in the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are substantially spherical in shape. Figure 2 As shown, first inorganic particles 91 are formed of first portions 91a protruding from resin 80 and second portions 91b embedded in resin 80. First surface 22 of resin insulating layer 20 is formed of upper surface 80R of resin 80 and the exposed surface of first portion 91a exposed from the upper surface of resin 80.

[0032] The ratio R of the volume of the first portion 91a to the volume of the first inorganic particles 91 (volume of the first portion / volume of the first particles) is greater than 0 and is less than 0.4. The ratio R is preferably less than 0.2. The ratio R is more preferably less than 0.1. The ratio R is most preferably less than 0.05. When the first portion 91a protrudes from the resin 80, the first surface 22 of the resin insulating layer 20 has tiny unevenness. However, the upper surface 80R of the resin 80 is not roughened. Therefore, the first surface 22 has almost no concave portion. The arithmetic mean roughness (Ra) of the first surface 22 is less than 0.08μm. The roughness Ra of the first surface 22 is preferably less than 0.05μm. The roughness Ra of the first surface 22 is more preferably less than 0.03μm.

[0033] like Figure 1 and Figure 3As shown, the inorganic particles 90 further include third inorganic particles 93 that form the inner wall surface (first inner wall surface) 27 of the opening (opening for the via conductor) 26. The shape of the third inorganic particle 93 is obtained by cutting a sphere in a plane. The shape of the third inorganic particle 93 is obtained by cutting the second inorganic particle 92 in a plane. The third inorganic particle 93 is formed by the second inorganic particle 92. The third inorganic particle 93 is obtained by removing a portion of the second inorganic particle 92. The shape of the third inorganic particle 93 is essentially a spherical segment. A spherical segment is a solid obtained by cutting a sphere in a roughly flat plane. The solid obtained by cutting a sphere in a plane passing through the center of the sphere is a hemisphere, which is a type of spherical segment. In the embodiment, the surface exposed by cutting the sphere in a roughly flat plane is referred to as a cut surface. The third inorganic particle 93 has a flat portion 93a. The flat portion 93a forms the inner wall surface 27. The inner wall surface 27 is formed by the resin 80 and the flat portion 93a. The flat portion 93a and the surface of the resin 80 that forms the inner wall surface 27 (the first resin surface) 80a form a substantially common surface. No irregularities are formed on the resin 80 that forms the inner wall surface 27. The surface 80a of the resin 80 that forms the inner wall surface 27 is substantially smooth. No irregularities are formed on the exposed surface (the surface that forms the inner wall surface 27) 93b of the flat portion 93a. The exposed surface (the first exposed surface) 93b of the flat portion 93a is smooth. The inner wall surface 27 is smoothly formed. The arithmetic mean roughness (Ra) of the inner wall surface 27 is 1.0 μm or less. The roughness (Ra) of the surface 80a of the resin 80 that forms the inner wall surface 27 is 1.0 μm or less.

[0034] The inner wall surface 27 may have a step (first step) between the flat portion 93a and the surface 80a of the resin 80 forming the inner wall surface 27. The exposed surface (first exposed surface) 93b of the flat portion 93a protrudes relative to the surface 80a of the resin 80 forming the inner wall surface 27. Alternatively, the exposed surface 93b of the flat portion 93a is recessed relative to the surface 80a of the resin 80 forming the inner wall surface 27. Preferably, it protrudes. The size of the step (first step) (the distance between the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 forming the inner wall surface 27) is 5 μm or less. The size of the first step is preferably 3 μm or less. More preferably, the size of the first step is 1.5 μm or less. Even if a step (first step) is formed, since the step is small, the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 forming the inner wall surface 27 form a roughly common surface.

[0035] like Figure 1As shown, the second conductor layer 30 is formed on the first surface 22 of the resin insulation layer (first resin insulation layer) 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a pad 36. Although not shown in the figure, the second conductor layer 30 also includes a conductor circuit other than the first signal wiring 32, the second signal wiring 34, and the pad 36. The first signal wiring 32 and the second signal wiring 34 form a pair of wiring. The first signal wiring 32 is adjacent to the second signal wiring 34.

[0036] The conductor layer (second conductor layer) 30 is primarily formed of copper. The second conductor layer 30 is formed from a seed layer 30a on the first surface 22 and an electroplated layer 30b on the seed layer 30a. The seed layer 30a is formed from a first layer 31a on the first surface 22 and a second layer 31b on the first layer 31a. The thickness of the seed layer 30a is less than 0.5 μm. The first conductor layer 10 and the second conductor layer 30 are identical. The relationship between the thickness of the first layer 31a and the thickness of the second layer 31b is similar to the relationship between the thickness of the first layer 11a and the thickness of the second layer 11b. The first layer 31a and the second layer 31b form the second conductor layer 30, and the first layer 11a and the second layer 11b form the first conductor layer 10. The first layer 31a is formed from the same alloy (copper alloy) as the first layer 11a. The second layer 31b is formed from copper. The electroplated layer 30b is formed from copper. The first layer 31a is in contact with the first surface 22.

[0037] The via conductor (first via conductor) 40 is formed in the opening (opening for the via conductor) 26. The opening 26 passes through the first resin insulating layer 20 and reaches the first conductor layer 10. The via conductor (first via conductor) 40 connects the first conductor layer 10 and the second conductor layer 30. Figure 1 In the embodiment, via conductor 40 connects pad 14 and land 36. Via conductor 40 is formed by seed layer 30a and plating layer 30b on seed layer 30a. Seed layer 30a forming via conductor 40 and seed layer 30a forming second conductor layer 30 are common. First layer 31a forming via conductor 40 and first layer 31a forming second conductor layer 30 are common. First layer 31a contacts inner wall surface 27. Second layer 31b forming via conductor 40 and second layer 31b forming second conductor layer 30 are common. Plating layer 30b forming via conductor 40 and plating layer 30b forming second conductor layer 30 are common.

[0038] The first layer 11a forming the first conductor layer 10, the first layer 31a forming the second conductor layer 30, and the first layer 31a forming the via-hole conductor 40 are identical. Both 11a and 31a are formed from the same element. The elements forming both 11a and 31a are in the same amounts. The second layer 11b forming the first conductor layer 10, the second layer 31b forming the second conductor layer 30, and the second layer 31b forming the via-hole conductor 40 are identical. The second layers 11b and 31b are each formed from the same element. The second layers 11b and 31b are each formed from substantially the same amount of elements. The electroplated layer 10b forming the first conductor layer 10, the electroplated layer 30b forming the second conductor layer 30, and the electroplated layer 30b forming the via-hole conductor 40 are identical. The electroplated layers 10b and 30b are each formed from the same element. The electroplated layers 10b and 30b are each formed from substantially the same amount of elements.

[0039] like Figure 4 As shown, the seed layer 30a forming the via conductor 40 may also include a generally smooth first portion (first film) 60 and a generally smooth second portion (second film) 70. The first portion 60 is electrically connected to the second portion 70. The first portion 60 is continuous with the second portion 70. A portion of the first portion 60 is formed on the second portion 70. The front end 62 of the first portion 60 is formed on the rear end 72 of the second portion 70. The first portion 60 and the second portion 70 are formed simultaneously. The cross-section of the seed layer 30a covering the inner wall surface 23 has a generally stepped shape.

[0040] like Figure 4 As shown, the first layer 31a of the seed layer 30a includes a first portion (first film) 60a and a second portion (second film) 70a. The first portion 60a is electrically connected to the second portion 70a. The first portion 60a is continuous with the second portion 70a. The front end 62a of the first portion 60a is formed on the rear end 72a of the second portion 70a. The cross-section of the first layer 31a covering the inner wall surface 23 has a generally stepped shape. The first layer 31a on the inner wall surface 27 is in contact with the inner wall surface 27.

[0041] The second layer 31b of the seed layer 30a includes a first portion (first film) 60b and a second portion (second film) 70b. The first portion 60b is electrically connected to the second portion 70b. The front end 62b of the first portion 60b is formed on the rear end 72b of the second portion 70b. The cross-section of the second layer 31b formed on the inner wall surface 23 has a substantially stepped shape.

[0042] A portion of the first portion 60 is stacked on the second portion 70. A portion of the first portion 60 is overlapped on the second portion 70. A front end 62 of the first portion 60 is stacked on a rear end 72 of the second portion 70. A front end 62 of the first portion 60 is overlapped on a rear end 72 of the second portion 70.

[0043] A second resin insulating layer 120 is formed on the second conductive layer 30 and the first surface 22 of the first resin insulating layer 20. The second resin insulating layer 120 has a first surface 122 and a second surface 124 opposite to the first surface 122. The second surface 124 of the second resin insulating layer 120 faces the second conductive layer 30. The second resin insulating layer 120 has an opening (opening for a via conductor) 126. The opening 126 penetrates the second resin insulating layer 120 and reaches the second conductive layer 30.

[0044] The second resin insulating layer 120 is formed from a resin 80 and inorganic particles 90. The first resin insulating layer 20 is identical to the second resin insulating layer 120. Therefore, the resin 80 forming the second resin insulating layer 120 is identical to the resin 80 forming the first resin insulating layer 20. The inorganic particles 90 forming the second resin insulating layer 120 are identical to the inorganic particles 90 forming the first resin insulating layer 20. Similar to the first resin insulating layer 20, the inorganic particles 90 forming the second resin insulating layer 120 include first inorganic particles 91, second inorganic particles 92, and third inorganic particles 93. The first inorganic particles 91 in the first resin insulating layer 20 are identical to the first inorganic particles 91 in the second resin insulating layer 120. The second inorganic particles 92 in the first resin insulating layer 20 are identical to the second inorganic particles 92 in the second resin insulating layer 120. The third inorganic particles 93 in the first resin insulating layer 20 are identical to the third inorganic particles 93 in the second resin insulating layer 120.

[0045] First surface 22 of first resin insulating layer 20 is identical to first surface 122 of second resin insulating layer 120. First surface 122 of resin insulating layer (second resin insulating layer) 120 is formed by the upper surface of resin 80 forming resin insulating layer (second resin insulating layer) 120 and the exposed surface of first portion 91a exposed from the upper surface of resin 80.

[0046] The opening (opening for the via conductor) 126 that passes through the second resin insulating layer 120 is identical to the opening (opening for the via conductor) 26 that passes through the first resin insulating layer 20. Therefore, the inner wall surface (second inner wall surface) 127 of the opening 126 is identical to the inner wall surface (first inner wall surface) 27 of the opening 26. Second inner wall surface 127 is formed by the resin 80 and the flat portion 93a of the third inorganic particle 93. Similar to the first inner wall surface 27, second inner wall surface 127 is formed by the surface of the resin 80 (the second resin surface) that forms the second inner wall surface 127 and the flat portion 93a of the third inorganic particle 93 that forms the second resin insulating layer 120. Similar to the flat portion 93a of the third inorganic particle 93 that forms the first resin insulating layer 20, the flat portion 93a of the third inorganic particle 93 that forms the second resin insulating layer 120 has an exposed surface (the second exposed surface). The surface of the second resin and the second exposed surface that forms the inner wall surface 127 form a substantially common surface. Similar to the first inner wall surface 27, the second inner wall surface 127 can have a step (second step) between the second resin surface and the second exposed surface. The first step and the second step are identical. The size of the second step is the same as the size of the first step. Therefore, even if the second inner wall surface 127 has the second step, the second resin surface and the second exposed surface form a substantially common surface.

[0047] like Figure 1As shown, a third conductor layer 130 is formed on the first surface 122 of the second resin insulation layer 120. A via conductor (second via conductor) 140 is formed in the opening 126, connecting the second conductor layer 30 and the third conductor layer 130. The third conductor layer 130 is identical to the second conductor layer 30. The second via conductor 140 is identical to the first via conductor 40. The third conductor layer 130 and the second via conductor 140 are formed from a seed layer 130a and a plating layer 130b on the seed layer 130a. The seed layer 130a is composed of a first layer 131a and a second layer 131b on the first layer 131a. The first layer 131a forming the third conductor layer 130 and the second via conductor 140 is identical to the first layer 31a of the second conductor layer 30. The second layer 131b forming the third conductor layer 130 and the second via conductor 140 is identical to the second layer 31b of the second conductor layer 30. The plating layer 130b forming the third conductor layer 130 and the second via conductor 140 is identical to the plating layer 30b of the second conductor layer 30. The first layer 131a is in contact with the first surface 122 of the second resin insulation layer 120. The first layer 131a is in contact with the inner wall surface (second inner wall surface) 127. The layers forming the second conductor layer 30 (the first layer 31a, the second layer 31b, and the plating layer 30b) and the layers forming the third conductor layer 130 (the first layer 131a, the second layer 131b, and the plating layer 130b) have the same thickness and composition. The layers forming the second conductor layer 30 (the first layer 31a, the second layer 31b, and the plating layer 30b) and the layers forming the third conductor layer 130 (the first layer 131a, the second layer 131b, and the plating layer 130b) are formed from the same elements. The elements contained in the layers forming the second conductor layer 30 (first layer 31a, second layer 31b, plating layer 30b) are the same in amount as the elements contained in the layers forming the third conductor layer 130 (first layer 131a, second layer 131b, plating layer 130b).

[0048] Figure 5 FIG. 4 is an enlarged cross-sectional view of the first signal wiring 32 of the second conductor layer 30. Figure 5 As shown, the first signal wiring 32 is formed by a seed layer 30a on the first surface 22 of the first resin insulation layer 20 and a plating layer 30b on the seed layer 30a. The seed layer 30a includes a first layer 31a on the first surface 22 and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 22. The plating layer 30b is formed directly above the second layer 31b.

[0049] like Figure 5As shown, the width (left-right length in the figure) of the seed layer 30a of the first signal wiring 32 is smaller than the width of the plating layer 30b. The width of the first signal wiring 32 is smallest at the boundary B between the seed layer 30a and the plating layer 30b. The width D2 of the first layer 31a is greater than the width D3 of the second layer 31b, and the width D1 of the plating layer 30b is greater than the width D2 of the first layer 31a.

[0050] like Figure 5 As shown, widths D1, D2, and D3 are the distances between the side surfaces of the wiring. Width D1 is the distance between the side surfaces of the first signal wiring 32. Width D1 is measured near the top surface of the first signal wiring 32. The top surface of the first signal wiring 32 is separated from the first surface 22. Width D2 is measured on the first surface 22. Width D3 is measured at the interface between the second layer 31b and the plating layer 30b.

[0051] Figure 5 The first signal wiring 32 is shown as an example, but the other conductor circuits (second signal wiring 34 and pad 36) in the second conductor layer 30 also have the same structure as the first signal wiring 32. The conductor circuit in the third conductor layer 130 also has the same structure as the first signal wiring 32.

[0052] The length of each side of the printed wiring board 2 is 50 mm or longer, preferably 100 mm or longer, and 250 mm or shorter.

[0053] The printed wiring board 2 may include a solder resist layer on the first surface 122 of the second resin insulating layer 120 and the third conductor layer 130. The insulating layer 4 may also form a core material.

[0054] [Method for Manufacturing Printed Wiring Board 2 According to Embodiment]

[0055] Figures 6A to 6G and Figure 7 A method for manufacturing the printed wiring board 2 according to the embodiment will be described. Figures 6A to 6C 、 Figure 6E as well as Figure 6G It is a cross-sectional view. Figure 6D and Figure 6F 、 Figure 7 It is an enlarged cross-sectional view. Figure 6A The insulating layer 4 and the conductive layer (first conductive layer) 10 formed on the third surface 6 of the insulating layer 4 are shown. The first conductive layer 10 is formed by a semi-additive process. The first layer 11a and the second layer 11b are formed by sputtering. The first layer 11a and the second layer 11b are formed in a vacuum. The plated layer 10b is formed by electroplating.

[0056] like Figure 6BAs shown, a resin insulation layer (first resin insulation layer) 20 and a protective film 50 are formed on the insulation layer 4 and the first conductor layer 10. The step of forming the resin insulation layer 20 and the protective film 50 on the insulation layer 4 and the first conductor layer 10 includes the steps of forming the resin insulation layer 20 on the insulation layer 4 and the first conductor layer 10 and forming the protective film 50 on the resin insulation layer 20. The step of forming the resin insulation layer 20 and the protective film 50 on the insulation layer 4 and the first conductor layer 10 includes the step of forming the resin insulation layer 20 with the protective film 50 on the insulation layer 4 and the first conductor layer 10. The manufacturing method including the steps of forming the resin insulation layer 20 on the first conductor layer 10 and forming the protective film 50 on the resin insulation layer 20 includes the steps of preparing the resin insulation layer 20 with the protective film 50 and forming the resin insulation layer 20 with the protective film 50 on the first conductor layer 10. The second surface 24 of the resin insulation layer 20 faces the third surface 6 of the insulation layer 4. A protective film 50 is formed on the first surface 22 of the first resin insulating layer 20. The resin insulating layer 20 includes a resin 80 and inorganic particles 90. The inorganic particles 90 are embedded in the resin 80. An example of the inorganic particles 90 is glass particles.

[0057] The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. An example of the protective film 50 is a film made of polyethylene terephthalate (PET). A mold release agent is formed between the protective film 50 and the resin insulating layer 20.

[0058] like Figure 6C As shown, laser light L is irradiated from above protective film 50. Laser light L penetrates both protective film 50 and resin insulating layer 20. An opening 26 (an opening for a via conductor) is formed, reaching pad 14 of first conductor layer 10. Inner wall surface 27b of opening 26 after laser irradiation is formed. Laser light L can be, for example, a UV laser or a CO2 laser. Pad 14 is exposed through opening 26. When forming opening 26, first surface 22 is covered by protective film 50. Therefore, even if resin scatters during the formation of opening 26, adhesion of the resin to first surface 22 can be suppressed.

[0059] Figure 6D The figure shows the inner wall surface 27b of the opening 26 after laser irradiation. By irradiating the resin insulating layer 20 with laser light L, a portion of the second inorganic particles 92 embedded in the resin 80 forms the inner wall surface 27b after laser irradiation. The inner wall surface 27b is formed by the resin 80 and the inorganic particles 90 protruding from the resin 80. Several of the second inorganic particles embedded in the resin insulating layer 20 partially protrude from the inner wall surface 27b. The second inorganic particles 92 forming the inner wall surface 27b after laser irradiation are formed by the protruding portions P protruding from the resin 80 and the portions E embedded in the resin 80.

[0060] The inner wall surface 27b is formed by the resin 80 and the inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 27b after laser irradiation is processed. It is preferred to selectively remove the inorganic particles 90 protruding from the resin 80. Thus, the third inorganic particles 93 are formed from the inorganic particles 90. For example, by treating the inner wall surface 27b after laser irradiation with chemicals, the inorganic particles 90 protruding from the resin 80 are selectively removed. Alternatively, by treating the inner wall surface 27b after laser irradiation with plasma, the inorganic particles 90 protruding from the resin 80 are selectively removed. The etching speed of the selective removal of the inorganic particles 90 is greater than the etching speed of the resin 80. For example, the difference in etching speed between the two is more than 10 times. Alternatively, the difference in etching speed between the two is more than 50 times. Alternatively, the difference in etching speed between the two is more than 100 times. By treating the inner wall surface 27b after laser irradiation, a material having a flat portion 93a ( Figure 3 ) third inorganic particles 93. By controlling the conditions for treating inner wall surface 27b after laser irradiation, the shape of inner wall surface 27 can be controlled. Examples of these conditions include temperature, concentration, time, gas type, and pressure. The etching rates of inorganic particles 90 and resin are controlled.

[0061] By irradiating the resin insulating layer 20 with laser light L, a portion of the second inorganic particles 92 embedded in the resin 80 forms the inner wall surface 27b after laser irradiation. The second inorganic particles 92 forming the inner wall surface 27b after laser irradiation are formed by a protruding portion P protruding from the resin 80 and a portion E embedded in the resin 80. The inner wall surface 27b after laser irradiation is treated. For example, the inner wall surface 27b is treated with a plasma of a gas containing tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 27b of the embodiment ( Figure 1 、 Figure 3). By processing the inner wall surface 27b, the third inorganic particles 93 are formed from the second inorganic particles 92. By selectively removing the protruding portion P, the third inorganic particles 93 having a flat portion 93a are formed. The flat portion 93a is a plane. When the second inorganic particle 92 having a roughly spherical shape is cut by a plane, the shape of the third inorganic particle 93 is obtained. The inner wall surface 27 is formed by the flat portion 93a and the surface 80a of the resin 80. The exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on approximately the same plane. For example, when the seed layer 30a is formed on the inner wall surface 27b by sputtering, the protruding portion P hinders the growth of the sputtering film. For example, a continuous seed layer 30a is not formed on the inner wall surface 27b. Alternatively, the thickness of the seed layer 30a needs to be increased. It is impossible to form a fine conductor circuit. In an embodiment, the protruding portion P is removed. The embodiment can make the thickness of the seed layer 30a formed by sputtering thinner. Even if the seed layer 30 a formed by sputtering is thin, a continuous seed layer 30 a can be obtained. The thickness of the seed layer 30 a is 0.05 μm or more and less than 0.5 μm.

[0062] Forming the opening 26 includes forming inorganic particles (second inorganic particles 92) 90 having a protrusion P. The protrusion P protrudes from the resin 80 forming the inner wall surface 27b of the opening 26. The third inorganic particles 93 are formed by removing the protrusion P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 27 of the opening 26 includes an exposed surface 93b of the third inorganic particles 93. The exposed surface 93b of the third inorganic particles 93 is formed by removing the protrusion P.

[0063] The shape of the third inorganic particle 93 obtained by cutting the second inorganic particle 92 having a substantially spherical shape along a plane includes removing the protruding portion P of the inorganic particle 90. The inner wall surface 27 of the actual opening 26 is a substantially curved surface. The flat portion 93a is formed by removing the protruding portion P, so the exposed surface 93b of the flat portion 93a includes a curved surface. In other words, the surface formed by the flat portion 93a and the resin 80 includes forming an inner wall surface 27 that is substantially curved.

[0064] No irregularities are formed on the inner wall surface 27. The inner wall surface 27 is formed smoothly. The size of the irregularities can be controlled by controlling the conditions for processing the inner wall surface 27b after laser irradiation.

[0065] The opening 26 is cleaned. By cleaning the opening 26, resin residue generated when the opening 26 is formed is removed. Cleaning the opening 26 is performed using plasma. That is, the cleaning is performed in a dry process. Cleaning includes desmearing. Since the first surface 22 of the resin insulating layer 20 is covered by the protective film 50, it is not affected by the plasma. At this point, no unevenness is formed on the first surface 22 of the resin insulating layer 20. The inorganic particles 90 are not exposed on the first surface 22. The first surface 22 is not roughened.

[0066] When the treatment of the inner wall surface 27 b after laser irradiation includes cleaning the inside of the opening 26 , the embodiment can eliminate the step of cleaning the inside of the opening 26 .

[0067] like Figure 6E As shown, after cleaning the inside of opening 26, protective film 50 is removed from resin insulating layer 20. When processing inner wall surface 27b after laser irradiation includes cleaning the inside of opening 26, protective film 50 is removed from resin insulating layer 20 after processing inner wall surface 27b after laser irradiation. While inner wall surface 27b after laser irradiation is being processed, protective film 50 covers first surface 22 of resin insulating layer 20.

[0068] After the protective film 50 is removed, the first surface 22 of the resin insulating layer 20 is cleaned. The first surface 22 is dry-etched. The dry etching is performed by sputtering using argon gas (argon sputtering). Figure 6F (a) and (b) schematically show the first surface 22 of the resin insulating layer 20 before and after dry etching. Figure 6F As shown in (a) and (b), the resin 80 forming the resin insulating layer 20 is removed by dry etching by about 20 nm. For example, the adhesive material used to bond the protective film 50 to the resin insulating layer 20 is removed. The resin 80 is selectively removed by dry etching. The thickness of the resin 80 becomes thinner. A portion of the inorganic particles 90 (second inorganic particles 92) is partially exposed from the upper surface of the resin 80 by dry etching. By exposing the second inorganic particles 92 buried in the resin 80 from the upper surface of the resin 80, the first inorganic particles 91 are obtained. The first inorganic particles 91 are formed by the second inorganic particles 92. The shape of the first inorganic particle 91 is the same as that of the second inorganic particle 92. Both are spherical in shape. As shown Figure 6FAs shown in (b), first inorganic particles 91 are formed from first portions 91a protruding from resin 80 and second portions 91b embedded in resin 80. First surface 22 of resin insulating layer 20 is formed from upper surface 80R of resin 80 and exposed surface 91aR of first portion 91a protruding from upper surface 80R of resin 80. Exposed surface 91aR of first portion 91a is exposed by dry etching. First surface 22 of resin insulating layer 20 is not roughened. Therefore, there are almost no recesses formed on first surface 22.

[0069] For example, use Figure 6F The cross-sectional view of the first inorganic particle 91 shown in (b) is calculated. Figure 6F (b) is obtained by cutting the resin insulating layer 20 at a plane perpendicular to the upper surface 80R. Figure 6F In (b), the second conductor layer 30 is omitted. Figure 6F The second conductive layer 30 is formed on the first inorganic particles 91 in (b). Figure 6F The exposed surface 91aR in (b) is covered by the second conductor layer 30. Figure 6F (b) Calculate the cross-sectional area 91aS of the first portion 91a. Similarly, calculate the cross-sectional area 91S of the first inorganic particle 91. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (cross-sectional area 91aS of the first portion 91a / cross-sectional area 91S of the first inorganic particle 91). For example, when evaluating the ratio R, 50 first inorganic particles 91 are observed. All 50 first inorganic particles 91 satisfy the ratio R.

[0070] like Figure 6GAs shown, a seed layer 30a is formed on the first surface 22 of the resin insulating layer 20. The seed layer 30a is formed by sputtering. The formation of the seed layer 30a is performed using a dry process. The first layer 31a is formed on the first surface 22 by sputtering. Simultaneously, the first layer 31a is formed on the inner wall surface 27 exposed from the opening 26 and on the pad 14 by sputtering. There are almost no recesses on the first surface 22. Therefore, the first layer 31a on the first surface 22 is formed to be roughly flat. Subsequently, the second layer 31b is formed on the first layer 31a by sputtering. The second layer 31b is formed roughly flat. The first layer 31a and the second layer 31b are formed in a vacuum. The seed layer 30a is also formed on the upper surface of the pad 14 exposed from the opening 26 and on the inner wall surface 27 of the opening 26. The first layer 31a is formed from an alloy containing copper and aluminum. Aluminum has high ductility and elongation. Therefore, the adhesion between the resin insulating layer 20 and the first layer 31a is high. It is believed that even if the resin insulating layer 20 expands and contracts due to thermal cycling, the seed layer 30a containing aluminum can follow the expansion and contraction. Even if the first surface 22 of the resin insulating layer 20 is smooth, the seed layer 30a is difficult to peel off from the resin insulating layer 20. It is believed that aluminum is easily oxidized. It is believed that if the third inorganic particles 93 are inorganic particles 90 containing oxygen (oxygen element), the first layer 31a formed on the inner wall surface 27 is closely attached to the third inorganic particles 93 via the oxygen in the inorganic particles 90 forming the inner wall surface 27. The first layer 31a is firmly bonded to the inner wall surface 27. The embodiment can improve the adhesion between the inner wall surface 27 and the first layer 31a. The seed layer 30a is difficult to peel off from the inner wall surface 27. The third inorganic particles 93 forming the inner wall surface 27 preferably contain oxygen element. It is believed that if the first inorganic particles 91 are inorganic particles 90 containing oxygen (oxygen element), the first layer 31a formed on the first surface 22 is closely bonded to the first inorganic particles 91 via the oxygen in the inorganic particles 90 forming the first surface 22. The first layer 31a is firmly bonded to the first surface 22. The embodiment can improve the adhesion between the first surface 22 and the first layer 31a. The seed layer 30a is difficult to peel off from the first surface 22. The first inorganic particles 91 forming the first surface 22 preferably contain oxygen element. The first layer 31a may further contain silicon. In this case, silicon is a specific metal, and the first layer 31a is formed from an alloy containing copper, aluminum, and silicon. When the inorganic particles 90 are glass particles, the first layer 31a and the first inorganic particles 91 both contain silicon. It is believed that the two are firmly bonded via silicon. It is believed that the embodiment can further improve the adhesion between the first layer 31a and the first surface 22. The first layer 31a and the third inorganic particles 93 both contain silicon. It is believed that the two are firmly bonded via silicon. It is considered that the embodiment can further improve the adhesive force between the first layer 31a and the inner wall surface 27. The second layer 31b is formed of copper.

[0071] First surface 22 has almost no recesses. Inner wall surface 27 has almost no recesses. First surface 22 is formed substantially smoothly. Inner wall surface 27 is formed substantially smoothly. Therefore, even when the thickness of the sputtering film (first layer 31a and second layer 31b) is thin, embodiments can form a continuous seed layer 30a. As a result, embodiments can form fine wiring. For example, embodiments can form high-density wiring groups such as L / S = 3 / 3μm and 2 / 2μm.

[0072] The first layer 31a formed on the inner wall surface 27 may also include a first portion 60a and a second portion 70a ( Figure 4 ). The first part 60a and the second part 70a are formed at the same time. The first part 60a is electrically connected to the second part 70a. The front end 62a of the first part 60a is formed on the rear end 72a of the second part 70a. The cross-section of the first layer 31a covering the inner wall surface 27 has a roughly stepped shape. If the inner wall surface 27 has a step (first step), the first layer 31a is easily formed on the inner wall surface 27 in such a way that the cross-section of the first layer 31a has a stepped shape. An example of sputtering conditions is as follows. The distance between the target and the first surface 22 of the resin insulating layer 20 is greater than 50 mm and less than 250 mm. The voltage is greater than 15 eV and less than 50 eV. The gas concentration is greater than 0.1 Pa and less than 1.0 Pa.

[0073] The second layer 31b formed on the first layer 31a covering the inner wall surface 27 includes a first portion 60b and a second portion 70b. The first portion 60b and the second portion 70b are formed simultaneously. The first portion 60b and the second portion 70b are electrically connected. The front end 62b of the first portion 60b is formed on the rear end 72b of the second portion 70b. The cross-section of the second layer 31b formed on the inner wall surface 27 has a substantially stepped shape. The sputtering conditions are substantially the same as described above.

[0074] In the printed wiring board 2 of the embodiment, a portion of the first portion 60 of the seed layer 30a, which covers the inner wall surface 27 of the opening 26, is formed on the second portion 70. The first portion 60 and the second portion 70 partially overlap. Therefore, the embodiment can improve the strength of the seed layer 30a. The seed layer 30a is less susceptible to breakage. The seed layer 30a is formed from the substantially smooth first portion 60 and the substantially smooth second portion 70. Therefore, when transmitting high-frequency signals, transmission loss is reduced. This provides a high-quality printed wiring board 2.

[0075] A resin layer for forming a plating resist is formed on the seed layer 30a. The resin layer is formed by attaching a photosensitive resin film (plating resist film) to the seed layer 30a. Alternatively, the resin layer can be formed by applying a liquid photosensitive resin to the seed layer 30a.

[0076] After the resin layer is formed, pressure is applied to the resin layer with the aid of a gas. The step of applying pressure and the step of forming the resin layer are performed separately. For example, when a film for a plating resist is pasted on the seed layer 30a, pressure is applied to the film for a plating resist. The pressure at this time is different from the pressure applied with the aid of a gas. When pressure is applied to the resin layer with the aid of a gas, pressure is not applied to the resin layer with the aid of a medium other than a gas. An example of a medium other than a gas is a vacuum. The resin layer is further heated. The step of applying pressure to the resin layer and the step of applying heat to the resin layer are performed simultaneously. Heat is applied to the resin layer with the aid of a gas. By applying pressure to the resin layer, the embodiment can eliminate, reduce or reduce the gap between the seed layer 30a and the resin layer. By applying heat and pressure to the resin layer, the embodiment can eliminate, reduce or reduce the gap between the seed layer 30a and the plating resist. For example, the intermediate substrate is arranged in a device (pressurizing device) for applying pressure to the intermediate substrate. The intermediate substrate is a substrate having a seed layer 30a and a resin layer on the seed layer 30a. Thereafter, gas is introduced into the pressurizing device. Gas is introduced into the pressurizing device to apply pressure to the resin layer. The pressurizing device may include a heater. The heater heats the gas within the pressurizing device. Heat is applied to the resin layer via the gas. The intermediate substrate may also include a protective film on the resin layer. If the protective film is present on the resin layer, pressure is applied to the resin layer via the protective film and the gas. Pressure and heat are applied to the resin layer via the protective film and the gas.

[0077] Using DI exposure, the resin layer is irradiated with exposure light. DI exposure, also known as direct exposure, is a method for forming a desired pattern of resist. DI exposure does not use a mask, but directly irradiates the resin layer with light. Therefore, DI exposure offers high productivity. Examples of DI exposure according to embodiments are disclosed in Japanese Patent Application Publication Nos. 2006-301591 and 2010-122526.

[0078] The DI exposure of the embodiment includes the following steps. Figure 7 As shown, the position of the boundary between the resin layer 300 and the seed layer 30a is measured by the sensor 400. The sensor 400 emits measurement light 500. The sensor 400 then measures the position by detecting the measurement light 500 reflected by the detection object. The sensor 400 can measure the position of the upper surface of the resin layer 300 rather than the position of the boundary between the resin layer 300 and the seed layer 30a. If a protective film is present on the resin layer 300, the sensor 400 can measure the position of the boundary between the resin layer 300 and the protective film or the position of the upper surface of the protective film.

[0079] For example, the position of the boundary between the resin layer 300 and the seed layer 30a is measured at position L1. The focus of the light used for exposure is corrected based on the measurement result. Based on the correction result, the resin layer 300 formed at a specified distance (between position L1 and position L2) is irradiated with the light for exposure. The depth of focus is, for example, ±5 μm. Next, the position of the boundary between the resin layer 300 and the seed layer 30a is measured at position L2. The focus of the light is corrected based on the measurement result. Based on the correction result, the resin layer 300 formed at a specified distance (between position L2 and position L3) is irradiated with the light for exposure. By repeating this process, the resin layer 300 is irradiated with light for forming a desired pattern.

[0080] In the prior art, the first surface 22 of the resin insulating layer 20 is roughened. The prior art forms unevenness on the first surface 22 of the resin insulating layer 20. In the prior art, the seed layer 30a on the first surface 22 of the resin insulating layer 20 should follow the unevenness of the first surface 22 of the resin insulating layer 20. The upper surface of the seed layer 30a of the prior art should have unevenness. Therefore, it is considered that in the prior art, when the resin layer 300 is formed on the seed layer 30a, a gap 600 is formed between the seed layer 30a and the resin layer 300 due to the unevenness of the upper surface of the seed layer 30a. Figure 7 In the example shown in FIG. 5 , a gap 600 is formed between the seed layer 30 a located at the position L2 and the resin layer 300 .

[0081] Position L2 has a gap 600 between the seed layer 30a and the resin layer 300. The resin layer 300 and the gap 600 are made of different materials. Therefore, when the measuring light 500 emitted from the sensor 400 is irradiated to position L2, the measuring light 500 should be refracted at the boundary surface between the resin layer 300 and the gap 600. Due to the influence of the gap 600, the sensor 400 cannot accurately measure the position of the boundary between the seed layer 30a and the resin layer 300. Therefore, the focus of the light used for exposure cannot be accurately corrected. Based on inaccurate information, the resin layer 300 formed at a specified distance (between position L2 and position L3) is irradiated with exposure light. For example, when the exposure light is irradiated, the focus of the light is misaligned. It is difficult to match the design value with the actual value. The pattern of the actually formed plating resist is likely to differ from the design value. The design value is the width of the plating resist and the spacing between adjacent plating resists. The prior art is prone to having gaps 600. The prior art makes it difficult to form fine wiring.

[0082] On the other hand, the first surface 22 of the resin insulating layer 20 of the embodiment has almost no recesses. The seed layer 30a formed on the first surface 22 follows the first surface 22. The upper surface of the seed layer 30a has almost no recesses. When the resin layer is formed on the seed layer 30a, no gap is formed between the seed layer 30a and the resin layer, or the gap is small or minimal.

[0083] Position L1 does not have a gap 600 between the seed layer 30a and the resin layer 300. Alternatively, even if there is a gap 600, the size of the gap 600 is such that it does not affect the measurement of the position. Therefore, when the measurement light 500 emitted from the sensor 400 is irradiated to position L1, the sensor 400 can accurately measure the position of the boundary between the seed layer 30a and the resin layer 300. The focus of the light used for exposure is accurately corrected based on the measurement result. Based on accurate information, the resin layer 300 formed at a specified distance (between position L1 and position L2) is irradiated with light for exposure. For example, the focus is aligned when irradiating the light for exposure. The pattern of the resist actually formed is roughly consistent with the design value. It is difficult for the embodiment to have a gap 600 that affects the measurement of the position. The embodiment can form fine wiring.

[0084] In order to form a plating resist, the embodiment can use DI exposure with high productivity. The plating resist has an opening for forming the first signal wiring 32, the second signal wiring 34 and the pad 36. If the first surface 22 has a recess, the air caused by the recess is easily enclosed between the plating resist and the seed layer 30a. However, in the embodiment, the first surface 22 has almost no recess. Therefore, the seed layer 30a on the first surface 22 is formed to be roughly flat. The seed layer 30a has almost no recess. It is difficult for air (gap) to remain between the plating resist and the seed layer 30a. The contact area between the plating resist and the seed layer 30a is large. Even if the width of the plating resist for forming the space between the first signal wiring 32 and the second signal wiring 34 is less than 10 μm, the plating resist is difficult to peel off from the upper surface of the seed layer 30a. Even if the width of the plating resist is more than 3 μm and less than 8 μm, the embodiment can also form the plating resist on the seed layer 30a. Even if the width of the plating resist is 6 μm or less, the plating resist is unlikely to be peeled off from the seed layer 30 a .

[0085] An electroplating layer 30b is formed on the seed layer 30a exposed from the plating resist. The electroplating layer 30b is formed of copper. The electroplating layer 30b fills the opening 26. The first signal wiring 32, the second signal wiring 34, and the pad 36 are formed by the seed layer 30a and the electroplating layer 30b on the first surface 22. The second conductor layer 30 is formed. The via conductor (first via conductor) 40 is formed using the seed layer 30a and the electroplating layer 30b in the opening 26. The via conductor 40 connects the pad 14 to the pad 36. The first signal wiring 32 and the second signal wiring 34 form a paired wiring. The first via conductor 40 connects the conductor layer (first conductor layer) 10 and the conductor layer (second conductor layer) 30.

[0086] The plating resist is removed. The seed layer 30a exposed from the electroplating layer 30b is removed. The seed layer 30a is removed by wet etching. The etching solution used in the wet etching is an aqueous solution containing hydrogen peroxide solution and sulfuric acid. Through wet etching, the first layer 31a and the second layer 31b are removed simultaneously. The second conductor layer 30 and the via conductor 40 are formed simultaneously. The width D2 of the first layer 31a is greater than the width D3 of the second layer 31b, and the width D1 of the electroplating layer 30b is greater than the width D2 of the first layer 31a. The etching rate of the seed layer 30a is greater than the etching rate of the electroplating layer 30b. The etching rate of the seed layer is 1.1 to 1.5 times that of the electroplating layer. The seed layer 30a formed by sputtering has a higher ratio of amorphous structure to metal crystal part than the electroplating layer 30b. Generally, the amorphous structure has many crystal defects. The greater the number of crystal defects, the greater the etching rate. The etching rate of the seed layer 30a is greater than the etching rate of the electroplating layer 30b. Therefore, when the seed layer 30a is removed, the etching amount of the electroplating layer 30b is small. The conductor circuit is difficult to be excessively removed. In an embodiment, the width of the conductor circuit is roughly consistent with the design value. When the seed layer 30a is removed by etching, the width of the seed layer 30a forming the conductor circuit (first signal wiring 32, second signal wiring 34, pad 36) of the second conductor layer 30 is less than the width of the electroplating layer 30b. When the first layer 31a is formed of a copper alloy and the second layer 31b is formed of copper, only the first layer 31a is an alloy. Therefore, the embodiment can increase the etching rate difference between the two. As an etching solution for removing the seed layer 30a, an etching solution that dissolves the second layer 31b more than the first layer 31a is preferably used. The width of the wiring (the distance between the side walls of the wiring) is minimum at the boundary portion B between the second layer 31b and the electroplating layer 30b. Since the stress is greatest at the boundary portion B, the adhesion between the first layer 31 a and the first resin insulating layer 20 is improved.

[0087] Because the first surface 22 has almost no recesses, embodiments can reduce the thickness of the first layer 31a. The thickness of the first layer 31a is substantially thinner than the thickness of the electroplated layer 30b. Therefore, the orientation of the particles forming the first layer 31a is likely to be smaller than the orientation of the particles forming the electroplated layer 30b. Alternatively, the density of the first layer 31a is likely to be smaller than the density of the electroplated layer 30b. Alternatively, the crystallinity of the first layer 31a is likely to be smaller than the crystallinity of the electroplated layer 30b. Because the first surface 22 has almost no recesses, embodiments can reduce the thickness of the second layer 31b. The thickness of the second layer 31b is substantially thinner than the thickness of the electroplated layer 30b. Therefore, the orientation of the particles forming the second layer 31b is likely to be smaller than the orientation of the particles forming the electroplated layer 30b. Alternatively, the density of the second layer 31b is likely to be smaller than the density of the electroplated layer 30b. Alternatively, the crystallinity of the second layer 31b is likely to be smaller than the crystallinity of the electroplated layer 30b. Therefore, the etching rate of the first layer 31a and the second layer 31b is greater than the etching rate of the electroplating layer 30b. When the seed layer 30a exposed from the electroplating layer 30b is removed, the width D1 of the electroplating layer 30b is greater than the width D2 of the first layer 31a. The width D1 of the electroplating layer 30b is greater than the width D3 of the second layer 31b. The etching rate of the electroplating layer 30b is less than the etching rate of the seed layer 30a. Therefore, the amount of dissolved components in the etching solution consumed to dissolve the electroplating layer 30b is small. According to the embodiment, the dissolved components fully reach the seed layer 30a. The seed layer 30a is effectively dissolved. The embodiment can form a signal wiring with a target width. The first layer 31a is covered by the second layer 31b. The dissolved components are consumed to dissolve the second layer 31b. Therefore, the embodiment can make the amount of dissolved first layer 31a less than the amount of dissolved second layer 31b. When the seed layer 30 a exposed from the plating layer 30 b is removed, the width D2 of the first layer 31 a is greater than the width D3 of the second layer 31 b .

[0088] A resin insulating layer (second resin insulating layer) 120 is formed on the first surface 22 of the first resin insulating layer 20 and the second conductor layer 30 using the same method as the first resin insulating layer 20. The second resin insulating layer 120 has a first surface 122, a second surface 124 opposite to the first surface 122, and an opening (an opening for a via conductor) 126. The second surface 124 of the second resin insulating layer 120 faces the second conductor layer 30. The second conductor layer 30 is exposed through the opening 126. A conductor layer (third conductor layer) 130 is formed on the first surface 122 of the second resin insulating layer 120 using the same method as the second conductor layer 30. A via conductor (second via conductor) 140 connecting the second conductor layer 30 and the third conductor layer 130 is formed within the opening (second opening) 126 using the same method as the first via conductor 40. This results in the printed wiring board 2 of the embodiment.

[0089] Each resin insulating layer is formed from resin 80 and inorganic particles 90. The resin forming each resin insulating layer is the same as resin 80 forming first resin insulating layer 20. The inorganic particles forming each resin insulating layer are the same as inorganic particles 90 forming first resin insulating layer 20. Each resin insulating layer contains first, second, and third inorganic particles. The first, second, and third inorganic particles in each resin insulating layer are the same as the first, second, and third inorganic particles in first resin insulating layer 20. Each resin insulating layer has a first surface, which is the same as first surface 22 of first resin insulating layer 20. Each resin insulating layer has an opening (opening for a via conductor). The opening penetrating each resin insulating layer is the same as opening 26 penetrating the first resin insulating layer. The inner wall surface of the opening penetrating each resin insulating layer is the same as inner wall surface 27 of opening 26 penetrating the first resin insulating layer 20.

[0090] Each conductor layer is formed from a seed layer and an electroplated layer on the seed layer. The seed layer forming each conductor layer is the same as the seed layer 30a forming the second conductor layer 30. The first layer forming each conductor layer is the same as the first layer 31a forming the second conductor layer 30. The second layer forming each conductor layer is the same as the second layer 31b forming the second conductor layer 30. The electroplated layer forming each conductor layer is the same as the electroplated layer 30b forming the second conductor layer 30.

[0091] Each via conductor is formed from a seed layer and a plating layer on the seed layer. The seed layer forming each via conductor is the same as seed layer 30a forming first via conductor 40. The first layer forming each via conductor is the same as first layer 31a forming first via conductor 40. The second layer forming each via conductor is the same as second layer 31b forming first via conductor 40. The plating layer forming each via conductor is the same as plating layer 30b forming first via conductor 40.

[0092] In the printed wiring board 2 of the embodiment, almost no recesses are formed on the first surface 22 of the resin insulating layer 20. The first surface 22 of the resin insulating layer 20 has almost no recesses. The upper surface of the seed layer 30a formed by sputtering on the first surface 22 of the resin insulating layer 20 also has almost no recesses. This embodiment can reduce transmission loss when electrical signals propagate through the signal wiring. Because the seed layer 30a is formed by sputtering, the bonding strength between the resin insulating layer 20 and the seed layer 30a is high. The conductive circuit is difficult to peel off from the resin insulating layer 20. Even with a thin sputtering film, the embodiment can form a continuous seed layer 30a. When removing the seed layer 30a, the embodiment can reduce the amount of etching. Furthermore, because the upper surface of the seed layer 30a is substantially flat, the embodiment can form a fine plating resist having dimensions close to the target value using DI exposure. This embodiment can form fine signal wiring. This embodiment can produce a high-quality printed wiring board 2.

[0093] Even if the sputtering film is thin, the embodiment can form a continuous seed layer 30a. The inner wall surface 27 of the opening 26 is formed by the flat portion 93a of the third inorganic particle 93 and the resin 80. The flat portion 93a and the surface 80a of the resin 80 that forms the inner wall surface 27 form a common surface. The inner wall surface 27 is smoothly formed. Therefore, a seed layer 30a having a uniform thickness is formed on the inner wall surface 27 of the opening 26. The thickness of the seed layer 30a is thin. The first surface 22 is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The first surface 22 does not have a recessed portion. Therefore, a seed layer 30a having a uniform thickness is formed on the first surface 22. The thickness of the seed layer 30a is thin. When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electroplated layer 30b is small. The second conductive layer 30 including the first signal wiring 32 and the second signal wiring 34 has a width as designed, thereby forming fine wiring and providing a high-quality printed wiring board 2.

[0094] If the first layer 31a of the seed layer 30a contains aluminum and the third inorganic particles 93 contain oxygen, the embodiment can improve the adhesion between the first layer 31a and the inner wall surface 27. Even if the diameter of the opening 26 is small, the via conductor 40 is unlikely to be peeled off from the inner wall surface 27. Therefore, the connection resistance through the via conductor 40 is unlikely to increase. Figure 6G As shown, the diameter D of the via conductor 40 (the diameter of the opening 26) is measured on the pad 14. Diameter D is 20 μm or more and 50 μm or less. Even if the length of each side of the printed wiring board 2 exceeds 50 mm, the connection resistance through the via conductor 40 is unlikely to increase. Even if the length of each side of the printed wiring board 2 is 100 mm or more, the connection resistance is unlikely to increase over a long period of time. A printed wiring board 2 with high connection reliability is provided.

[0095] The embodiment can reduce the thickness of the first layer 31a forming the via conductor 40. The embodiment can reduce the thickness of the second layer 31b forming the via conductor 40. The first layer 31a and the second layer 31b form the seed layer 30a. The embodiment can increase the volume of the opening for the via conductor after the seed layer is formed. The opening for the via conductor after the seed layer is formed can also be referred to as the opening after the seed layer is formed. By forming an electroplating layer in the opening after the seed layer is formed, a via conductor composed of a seed layer and an electroplating layer is formed. Even if the diameter of the opening for the via conductor is small, the electroplating solution can easily enter the opening for the via conductor after the seed layer is formed. The electroplating layer forming the via conductor is unlikely to contain voids. A low-resistance via conductor is formed. An example of the opening 260 after the seed layer is formed is as follows Figure 6G As shown in FIG. 1 , the opening 260 after the seed layer is formed is surrounded by the seed layer, and the bottom and side surfaces of the opening 260 are in contact with the seed layer.

[0096] The embodiment can reduce the thickness of the first layer 31a formed of an alloy containing aluminum. The aluminum content in the signal wiring is low, while the copper content is high. The embodiment can provide low-resistance signal wiring. The embodiment can provide low-resistance signal wiring with high adhesion to the resin insulation layer.

[0097] In the printed wiring board 2 of the embodiment, the first surface 22 of the resin insulation layer 20 has almost no recesses. This suppresses the standard deviation of the relative dielectric constant near the first surface 22 of the resin insulation layer 20. The relative dielectric constant of the first surface 22 of the resin insulation layer 20 does not vary significantly depending on the location. Even if multiple signal wires contact the first surface 22 of the resin insulation layer 20, the embodiment can reduce the difference in propagation speed of electrical signals between the signal wires. Therefore, noise is suppressed in the printed wiring board 2 of the embodiment. Even if a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted by each signal wire reaches the logic IC almost simultaneously. The embodiment can suppress malfunctions of the logic IC. Even if the length of each signal wire is 5 mm or longer, the embodiment can reduce the difference in propagation speed. Even if the length of each signal wire is 10 mm to 20 mm, the embodiment can suppress malfunctions of the logic IC. The first surface 122 of the second resin insulation layer 120 is the same as the first surface 22 of the resin insulation layer 20. Therefore, the signal wires within the third conductor layer 130 have the same effects as the signal wires within the second conductor layer 30. A printed wiring board 2 having high quality is provided.

[0098] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the third inorganic particles 93 on the inner wall surface contain silicon. The first layer and the first inorganic particles 91 on the first surface contain silicon. It is believed that the two are firmly bonded via the silicon. The seed layer composed of an alloy containing copper, aluminum, and silicon is difficult to peel off from the inner wall surface. The seed layer is difficult to peel off from the first surface. The seed layer is difficult to peel off from the resin insulation layer.

[0099] It is believed that if the first layer contains aluminum and the inorganic particles (first inorganic particles 91, second inorganic particles 92, and third inorganic particles 93) 90 contain oxygen, the first layer and the inorganic particles (inorganic particles containing oxygen, such as glass particles) 90 will be firmly bonded. If the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer can be formed of copper, aluminum, and impurities.

[0100] [Another Example 1 of Implementation]

[0101] In another embodiment 1, the specific metal is selected from titanium, nickel, chromium, tin, and calcium.

[0102] [Another Example 2 of Implementation]

[0103] In another embodiment example 2, first layer 11a, 31a of seed layer 10a, 30a is formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, and calcium. First layer 11a, 31a is formed of an alloy containing copper. Second layer 11b, 31b is formed of copper. The amount of copper forming second layer 11b, 31b is 99.9 at % or greater. Preferably, the amount of copper is 99.95 at % or greater.

[0104] Each cross-sectional view is obtained by cutting the printed wiring board 2 along a plane perpendicular to the first surface 22. When the cross-sectional view includes a conductor circuit, the side surface of the conductor circuit is perpendicular to the cross-sectional view.

[0105] In this specification, the term "plane" is used to refer to the shape of the inner wall surface 27, the shape of the flat portion 93a, and the shape of the third inorganic particle 93. Figure 1 and Figure 3 That is, in Figure 1 and Figure 3 In FIG, the inner wall surface 27 is drawn substantially straight. Figure 1 and Figure 3 The shape of the inner wall surface 27 in the embodiment is substantially a straight line. The plane in this specification includes the actual straight line shown in the cross section. Figure 1 and Figure 3 As shown in the cross section of the third inorganic particle 93, in the cross section, cutting with a plane includes cutting with a straight line. The plane in this specification does not mean a completely flat plane, but includes a substantially flat plane. A substantially flat plane may also include small bumps and depressions.

Claims

1. A method for manufacturing a printed wiring board, comprising the following steps: forming a resin insulating layer having a first surface and a second surface opposite to the first surface on the first conductor layer; forming a protective film on the first surface of the resin insulation layer; forming an opening for a via conductor that simultaneously penetrates the protective film and the resin insulating layer and reaches the first conductor layer; removing the protective film from the resin insulation layer after forming the opening; cleaning the first surface of the resin insulation layer; forming a second conductor layer on the first surface of the resin insulation layer; as well as forming a via conductor in the opening to connect the first conductor layer and the second conductor layer; in, The resin insulating layer includes a resin and inorganic particles, the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles are approximately spherical in shape, and the second inorganic particles are approximately spherical in shape. The cleaning includes the steps of selectively removing the resin so that a portion of the second inorganic particles protrudes from the first surface of the resin insulating layer. By selectively removing the resin, the first inorganic particles are formed from the second inorganic particles, The first inorganic particle is formed by a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface. The step of forming the second conductor layer comprises the following steps: forming a seed layer on the first surface of the resin insulation layer by sputtering; forming a plating resist on the seed layer using DI exposure; forming an electroplating layer on the seed layer exposed from the plating resist; removing the plating resist; and The seed layer exposed from the electroplating layer is removed.

2. The method for manufacturing a printed wiring board according to claim 1, wherein Before forming the seed layer, the first surface of the resin insulation layer is not roughened.

3. The method for manufacturing a printed wiring board according to claim 1, wherein The second conductor layer has a conductor circuit, The seed layer has a first layer formed on the first surface and a second layer formed on the first layer, The conductor circuit is formed by the seed layer and the electroplating layer on the seed layer, In a cross section of the conductor circuit, the width of the first layer is greater than the width of the second layer, and the width of the electroplating layer is greater than the width of the first layer.

4. The method for manufacturing a printed wiring board according to claim 1, wherein The seed layer has a first layer formed on the first surface and a second layer formed on the first layer, The first layer is composed of an alloy containing copper and aluminum, The second layer is formed of copper.

5. The method for manufacturing a printed wiring board according to claim 1, wherein The inorganic particles further include third inorganic particles forming the inner wall surface of the opening, The third inorganic particles are formed from the second inorganic particles by treating the inner wall surface. The third inorganic particles have a flat portion, The shape of the third inorganic particle is roughly spherical, The flat portion forms the inner wall surface.

6. The method for manufacturing a printed wiring board according to claim 5, wherein The step of forming the opening includes the steps of: forming the inorganic particles to have a protruding portion protruding from the resin forming the inner wall surface of the opening, The third inorganic particles are formed by removing the protruding portions of the inorganic particles.

7. The method for manufacturing a printed wiring board according to claim 1, wherein A cross section of the seed layer on an inner wall surface of the opening has a substantially stepped shape.

8. The method for manufacturing a printed wiring board according to claim 1, wherein The step of forming the plating resist comprises the following steps: forming a resin layer for forming the plating resist on the seed layer; and Pressure is applied to the resin layer by means of gas.

9. The method for manufacturing a printed wiring board according to claim 8, wherein The step of applying the pressure is performed after forming the resin layer.

10. The method for manufacturing a printed wiring board according to claim 9, wherein The step of forming the plating resist further includes applying heat to the resin layer, and the step of applying pressure and the step of applying heat are performed simultaneously.

11. The method for manufacturing a printed wiring board according to claim 10, wherein The step of applying the pressure and the step of forming the resin layer are performed separately.

12. The method for manufacturing a printed wiring board according to claim 11, wherein The step of applying heat is performed with the aid of the gas.

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