A high-precision current mirror

Abstract

This application relates to a high-precision current mirror, comprising: a main transistor group configured to receive a reference current; and a slave transistor configured to generate a mirror current proportional to the reference current; wherein the main transistor group includes a first transistor and a second transistor, the control electrodes of which are electrically connected to each other; the second electrodes of both the first transistor and the second transistor are grounded; wherein the equivalent size ratio of the slave transistor to the main transistor group is a ratio K; the size of the first transistor is 1 to x times the ratio of the transistor size to the ratio K, and the size of the second transistor is x times the ratio of the transistor size to the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K as a percentage of its expected value; and a first adjustment circuit electrically connected to the second transistor, configured to decrease the ratio K; and / or a second adjustment circuit electrically connected to the second transistor, configured to increase the ratio K.

Description

Technical Field

[0001] This invention relates to the field of electrical control, and in particular to a high-precision current mirror. Background Technology

[0002] A current mirror is one of the fundamental units of analog integrated circuits. Besides serving as a bias module for various circuits within analog integrated circuits, it is also widely used to amplify reference currents to drive current-driven devices, such as LEDs. The accuracy and stability of the entire analog integrated circuit are directly affected by whether the current mirror can accurately replicate or scale the reference current.

[0003] Figure 1 The diagram shows a basic cascode current mirror structure, comprising a master transistor M0 and a slave transistor M1. The gates and sources of the two transistors are electrically connected. The mirror current Iout flowing through the slave transistor M1 can be understood as a scaled-down version of the reference current Iin flowing through the master transistor M0. Ideally, Iout = K * Iin, where K is the ratio of the dimensions of the slave transistor M1 to the master transistor M0. .

[0004] Figure 2 and Figure 3 The diagram shows a traditional current mirror structure with adjustment capabilities. A traditional common-gate common-source current mirror typically includes common-gate transistors MC0 and MC1 connected in series with the drains of the master transistor M0 and slave transistor M1, respectively, to make the drain voltages of the master and slave transistors approximately equal, thereby improving the accuracy of the current mirror. However, due to manufacturing errors, the ratio K of the slave transistor M1 to the master transistor M0 cannot reach the ideal value. To obtain a more accurate mirrored current Iout, the current mirror needs to use adjustment circuits or methods to correct the ratio K.

[0005] Figure 2 The solution can only adjust the value of the ratio K in one direction. The more switches are closed, the smaller the value of the ratio K becomes, and the smaller the output current becomes. Figure 3 The proposed solution enables bidirectional (increasing or decreasing) adjustment of the ratio K, exhibiting good trimming characteristics when K=1. However, when the ratio K is large (e.g., 100), the dimensions of transistors MT1 to MT3 need to be increased by a factor of K. This significantly increases chip area and costs. Therefore, the greater expectation is to utilize a bidirectional trimming circuit that does not substantially increase layout or cost to effectively improve the current mirror trimming accuracy, thereby obtaining a precise mirrored current. Summary of the Invention

[0006] To address the technical problems existing in the prior art, this application proposes a high-precision current mirror, comprising: a main transistor group configured to receive a reference current; and a slave transistor configured to generate a mirror current proportional to the reference current; wherein the main transistor group includes a first transistor and a second transistor, the control electrodes of which are electrically connected to each other; the second electrodes of both the first transistor and the second transistor are grounded; wherein the equivalent size ratio of the slave transistor to the main transistor group is a ratio K; the size of the first transistor is 1-x times the ratio of the slave transistor size to the ratio K, and the size of the second transistor is x times the ratio of the slave transistor size to the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K to its expected value; and a first adjustment circuit electrically connected to the second transistor, configured to decrease the ratio K; and / or a second adjustment circuit electrically connected to the second transistor, configured to increase the ratio K.

[0007] In particular, the high-precision current mirror is characterized in that the value of x is no greater than 20% of the total value.

[0008] Specifically, the high-precision current mirror is characterized in that the first adjustment circuit includes a first group of transistors, comprising one or more transistors connected in parallel with each other; the control electrode of each transistor in the first group of transistors is electrically connected to the control electrode of the first transistor and the control electrode of the second transistor; and the second electrode of each transistor in the first group of transistors is electrically connected to the second electrode of the second transistor; and a first group of switches, comprising one or more switches, respectively electrically connected between the first electrode of the corresponding transistor in the first group of transistors and the first electrode of the second transistor.

[0009] Specifically, the high-precision current mirror is characterized in that the length of each transistor in the first group of transistors is equal to the equivalent length of the main transistor group.

[0010] Specifically, the high-precision current mirror is characterized in that the first electrode of the second transistor is electrically connected to the first electrode of the first transistor via a first switch; wherein the first terminal of the first switch is electrically connected to the first electrode of the first transistor.

[0011] Specifically, the high-precision current mirror is characterized in that the second adjustment circuit includes a second group of transistors, comprising one or more transistors connected in parallel with each other; the control electrode of each transistor in the second group of transistors is electrically connected to the control electrode of the first transistor and the second transistor; and the second electrode of each transistor in the second group of transistors is electrically connected to the first electrode of the second transistor; and a second group of switches, comprising one or more switches; each switch in the second group of switches is electrically connected between the first electrode of each transistor in the second group of transistors and the first electrode of the first transistor.

[0012] Specifically, the high-precision current mirror is characterized in that the width of each transistor in the second group of transistors is equal to the width of the second transistor.

[0013] Specifically, the high-precision current mirror is characterized in that the second adjustment circuit includes a third group of transistors, comprising one or more transistors connected in series between the first electrode of the first transistor and the first electrode of the second transistor; the control electrode of each transistor in the third group of transistors is electrically connected to the control electrode of the first transistor and the second transistor; and a third group of switches, comprising one or more switches; each switch in the third group of switches is electrically connected between the first electrode and the second electrode of each transistor in the third group of transistors.

[0014] Specifically, the high-precision current mirror is characterized in that the width of each transistor in the third group of transistors is equal to the width of the second transistor.

[0015] This application also relates to an electronic device characterized by including a high-precision current mirror as described in any of the preceding applications.

[0016] This application also relates to a high-precision current mirror, characterized by comprising: a master transistor configured to receive a reference current; a slave transistor group configured to generate a mirror current proportional to the reference current; wherein the slave transistor group includes a third transistor and a fourth transistor, the control electrodes of which are electrically connected to each other; the second electrodes of the third transistor and the fourth transistor are both grounded; wherein the ratio of the equivalent size of the slave transistor group to the size of the master transistor is a ratio K; the size of the third transistor is 1-x times the product of the size of the master transistor and the ratio K, and the size of the fourth transistor is x times the product of the size of the master transistor and the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K relative to its expected value; and a fifth adjustment circuit electrically connected to the fourth transistor, configured to increase the ratio K; and / or a sixth adjustment circuit electrically connected to the fourth transistor, configured to decrease the ratio K.

[0017] In particular, the high-precision current mirror is characterized in that the value of x is no greater than 20% of the total value.

[0018] Specifically, the high-precision current mirror is characterized in that the fifth adjustment circuit includes a fifth group of transistors, comprising one or more transistors connected in parallel with each other, wherein the control electrode of each transistor in the fifth group of transistors is electrically connected to the control electrode of the third transistor and the fourth transistor; and the second electrode of each transistor in the fifth group of transistors is electrically connected to the second electrode of the fourth transistor; and a fifth group of switches, comprising one or more switches, respectively electrically connected between the first electrode of the corresponding transistor in the fifth group of transistors and the first electrode of the fourth transistor.

[0019] Specifically, the high-precision current mirror is characterized in that the length of each transistor in the fifth group of transistors is equal to the equivalent length of the transistor group.

[0020] Specifically, the high-precision current mirror is characterized in that the first terminal of the fourth transistor is electrically connected to the first terminal of the third transistor via a second switch; wherein the first terminal of the second switch is electrically connected to the first terminal of the third transistor.

[0021] Specifically, the high-precision current mirror is characterized in that the sixth adjustment circuit includes a sixth group of transistors, comprising one or more transistors connected in parallel with each other; the control electrode of each transistor in the sixth group of transistors is electrically connected to the control electrodes of the third transistor and the fourth transistor; and the second electrode of each transistor in the sixth group of transistors is electrically connected to the first electrode of the fourth transistor; and a sixth group of switches, comprising one or more switches, wherein each switch in the sixth group of switches is electrically connected between the first electrode of each transistor in the sixth group of transistors and the first electrode of the third transistor.

[0022] Specifically, the high-precision current mirror is characterized in that the width of each transistor in the sixth group of transistors is equal to the width of the fourth transistor.

[0023] Specifically, the high-precision current mirror is characterized in that the sixth adjustment circuit includes a seventh group of transistors, comprising one or more transistors connected in series between the first terminals of the third transistor and the second transistor; the control terminals of each transistor in the seventh group of transistors are electrically connected to the control terminals of the third transistor and the fourth transistor; and a seventh group of switches, comprising one or more switches; each switch in the seventh group of switches is electrically connected between the first and second terminals of the respective transistors in the seventh group of transistors.

[0024] Specifically, the high-precision current mirror is characterized in that the width of each transistor in the seventh group of transistors is equal to the width of the fourth transistor.

[0025] This application also relates to an electronic device characterized by including a high-precision current mirror as described in any of the preceding applications.

[0026] The high-precision current mirror proposed in this application can achieve high-precision bidirectional adjustment of the ratio of the reference current to the mirror current, thereby obtaining a higher precision mirror current and having higher reliability and stability. Attached Figure Description

[0027] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0028] Figure 1 The diagram shows a cascode current mirror structure based on a common source and cascode grid.

[0029] Figure 2 The diagram shown is a schematic of a traditional current mirror structure with adjustment function.

[0030] Figure 3 The diagram shown is a schematic of another traditional current mirror structure with adjustment function;

[0031] Figure 4 The diagram shown is a schematic diagram of a current mirror structure according to an embodiment of this application;

[0032] Figure 5 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application;

[0033] Figure 6 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application;

[0034] Figure 7 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0037] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0038] The high-precision current mirror proposed in this application adjusts the ratio of the reference current to the mirrored current by increasing or decreasing it through local adjustment. This significantly reduces the complexity of the adjustment circuit in the current mirror, thereby providing a more accurate mirrored current and improving the working efficiency of the current mirror. Compared with traditional current mirror solutions with adjustment capabilities, the circuit is simpler, the adjustment accuracy is higher, and the layout area is saved.

[0039] The high-precision current mirror proposed in this application equates the master or slave transistor in traditional schemes to two or more transistors based on an error ratio. The error ratio x is the percentage difference between the actual and expected values ​​of the ratio K, relative to its expected value. Determining the error ratio x determines the adjustment range of the ratio K. Based on the error ratio x, an adjustment starting point for the ratio K is selected, and the master or slave transistor is split according to x. The master or slave transistor is split into two transistors: a larger one and a smaller one. The larger transistor can be understood as occupying most of the original master or slave transistor's size, and the current mirror's mirroring function is primarily achieved by this part of the transistor. The smaller transistor can be understood as a portion of the original master or slave transistor. The adjustment circuit is electrically connected to the smaller transistor in series or parallel, adjusting the equivalent size of the smaller transistor to change the equivalent size of the master or slave transistor, thereby changing the value of the ratio K and improving the mirrored current accuracy of the current mirror output. By using this equivalent splitting method, the size of smaller transistors is adjusted. The comparison value K is then adjusted through local approximation or modification, significantly reducing the size of the transistors in the modification circuit and thus greatly reducing the current mirror layout. For example, when the length of the main transistor is L and the desired error ratio x is 20%, the main transistor is equivalently split into two transistors according to 20%L and 80%L. The size of the transistor with a length of 20%L is adjusted using the modification circuit, ultimately correcting the comparison value K. As another example, when the width of the transistor is W and the desired error ratio x is 10%, the transistor is equivalently split into two transistors according to 10%W and 90%W. The size of the transistor with a width of 10%W is adjusted using the modification circuit, thus correcting the comparison value k.

[0040] In one embodiment, the widths of the master and slave transistors are equal, and the lengths of either the master or slave transistors are divided according to an error ratio x. Alternatively, the lengths of the master and slave transistors are equal, and the widths of either the master or slave transistors are divided according to an error ratio x. This typically allows the current mirror to achieve better ratio K-value adjustment.

[0041] The working principle of the high-precision current mirror proposed in this application will be explained below using an example where all transistors in the current mirror are N-type transistors. However, it should not be assumed that the type of transistors in the current mirror of this application is limited to this embodiment; for example, P-type transistors may also be used. Depending on the type of transistor, the connection relationship between the transistors in the current mirror can also be adaptively adjusted or changed.

[0042] In the following text, transistor width refers to the width of the transistor channel, transistor length refers to the length of the transistor channel, and transistor size is the ratio of transistor channel width to channel length.

[0043] Figure 4 The diagram shown is a schematic diagram of a current mirror structure according to an embodiment of this application.

[0044] According to one embodiment, the current mirror includes a current source 41, a common-gate transistor T42, and a transistor T43. A common-gate transistor refers to two or more transistors whose gates or control electrodes are electrically connected to each other. The current source 41 is configured to receive a supply voltage VDD and provide a reference current Iin. The first electrode of transistor T42 is electrically connected to the output of current source 41. The first electrode of transistor T43 provides a mirrored current Iout.

[0045] According to one embodiment, the current mirror includes a master transistor group 44 electrically connected to the second terminal of transistor T42 and a slave transistor T45 electrically connected to the second terminal of transistor T43. The master transistor group 44 is configured to receive a reference current Iin delivered by transistor T42, and the slave transistor T45 is configured to generate a mirror current Iout proportional to the reference current Iin. Here, the proportionality refers to the ratio K.

[0046] According to one embodiment, the main transistor group 44 includes two common-gate, common-source transistors, a first transistor T441 and a second transistor T442. Common-gate, common-source means that the gates or control terminals of the transistors are electrically connected to each other, and their sources or second terminals are electrically connected to each other.

[0047] According to one embodiment, the first terminal of the first transistor T441 is electrically connected to the second terminal of the transistor T42.

[0048] According to one embodiment, the current mirror may further include a first switch S443. The first terminal of the second transistor T442 is electrically connected between the first terminal of the first transistor T441 and the second terminal of the transistor T42 via the first switch S443. The first terminal of the first switch S443 is electrically connected between the first terminal of the first transistor T441 and the second terminal of the transistor T42, and its second terminal is electrically connected to the first terminal of the second transistor T442.

[0049] According to one embodiment, the second terminals of the first transistor T441 and the second transistor T442 are respectively electrically connected to the second terminal of the transistor T45.

[0050] According to one embodiment, the control electrode of transistor T45 is electrically connected to the control electrodes of the first transistor T441 and the second transistor T442, and is also electrically connected to the first electrode of transistor T42, while the first electrode of transistor T45 is electrically connected to the second electrode of transistor T43.

[0051] According to one embodiment, the second terminal of transistor T45 is grounded.

[0052] According to one embodiment, the ratio of the size of transistor T45 to the equivalent size of the main transistor group 44 is K, and the error ratio of the ratio K is x. The size of the first transistor T441 can be 1 to x times the ratio of the size of transistor T45 to the ratio K, and the size of the second transistor T442 can be x times the ratio of the size of transistor T45 to the ratio K.

[0053] In one embodiment of this application, the lengths of the first transistor T441, the second transistor T442, and the transistor T45 may be substantially equal, while their widths may be unequal.

[0054] According to one embodiment, the width of the second transistor T442 can be x times the equivalent width of the main transistor group 44, and the width of the first transistor T441 can be (1-x) times the equivalent width of the main transistor group 44. Here, x is a percentage not greater than 50%. In one embodiment of this application, x is a percentage not greater than 20%. For example, the equivalent length of the main transistor group is L0 and the equivalent width is W0, and the ideal ratio is K, with an error ratio set to x. In this case, the width of the first transistor T441... and the width of the second transistor T442 The length of both the first transistor T441 and the second transistor T442 is L0.

[0055] In another embodiment of this application, the widths of the first transistor T441, the second transistor T442, and the transistor T45 may be substantially equal, while their lengths may be unequal.

[0056] According to one embodiment, transistors T42, T43, T45, T441, and T442 can be of the same type, such as N-type transistors.

[0057] According to one embodiment, the current mirror may include a first trimming circuit 46 and / or a second trimming circuit 47 electrically connected to the second transistor T442 to achieve bidirectional adjustment of the contrast value K.

[0058] In one embodiment, the first adjustment circuit 46 is configured to decrease the value of the ratio K. The second adjustment circuit 47 is configured to increase the value of the ratio K.

[0059] In one embodiment, the first tuning circuit 46 includes a first group of transistors sharing a common gate with the first transistor T441 and the second transistor T442, and a first group of switches. The first group of transistors includes transistors T460 to T46n, and the first group of switches includes switches S460 to S46n electrically connected between the first terminal of each of transistors T460 to T46n and the first terminal of the first switch S443. The first group of switches is configured such that, when the first switch S443 is closed, the first terminal of the corresponding transistor among transistors T460 to T46n is electrically connected to the first terminal of the second transistor T442, such that the corresponding transistor is connected in parallel with the second transistor T442 to increase the equivalent size of the second transistor T442. Here, n is an integer greater than or equal to 1.

[0060] In one embodiment, transistors T460 to T46n may be of the same type as transistors T42, T43, T45, T441, and T442.

[0061] According to one embodiment, in the first trimming circuit 46, transistors T460 to T46n in the first group of transistors are connected in parallel with each other.

[0062] According to one embodiment, the control electrodes of transistors T460 to T46n in the first group of transistors are electrically connected to each other and to the control electrodes of the first transistor T441 and the second transistor T442, and their respective second electrodes are electrically connected to the second electrode of the second transistor T442.

[0063] According to one embodiment, when the first switch S443 is closed, the first adjustment circuit 46 operates. The first adjustment circuit 46 is electrically connected to the second transistor T442 via the first switch S443. Closing a switch in the first group of switches causes the corresponding transistor in the first group of transistors to be connected to a current mirror, increasing the equivalent size of the second transistor T442, thereby increasing the equivalent size of the main transistor group 44 and decreasing the value of the ratio K. The number of switches closed in the first group of switches can be freely combined according to actual needs to obtain the required adjustment accuracy.

[0064] According to one embodiment, when the lengths of transistors T460 to T46n in the first group of transistors in the first adjustment circuit 46 are approximately the same or equivalent to the lengths of the main transistor group 44, the adjustment accuracy of the ratio K can be improved more effectively.

[0065] In one embodiment of this application, the main transistor group 44 has an equivalent width of W0 and an equivalent length of L0; the slave transistor T45 has a width of W1 and a length of L1; the ratio In the first trimming circuit 46, the widths of transistors T460 to T46n are Ws1, Ws2...Wsn, respectively, and their lengths are the same as the equivalent length of the main transistor group 44. The trimmed ratio is... This is equivalent to reducing the ratio K by increasing the width of the main transistor group 44.

[0066] In one embodiment, the dimensions of transistors T460 to T46n in the first group of transistors can be, for example, 1%, 2%, 5% of the equivalent size of the main transistor group 44, with the specific percentage value related to the actual adjustment accuracy.

[0067] According to one embodiment, the second trimming circuit 47 includes a second set of transistors sharing a common gate with the first transistor T441 and the second transistor T442, and a second set of switches. The second set of transistors includes transistors T470 to T47n, ​​and the second set of switches includes switches S470 to S47n, each electrically connected between the first terminal of each of transistors T470 to T47n and the first terminal of the first transistor T441. The second set of switches is configured to electrically connect the first terminal of the respective transistors T470 to T47n to the first terminal of the first transistor T441 to reduce the equivalent size of the second transistor T442.

[0068] According to one embodiment, the control electrodes of transistors T470 to T47n are electrically connected to each other and to the control electrodes of the first transistor T441 and the second transistor T442, respectively, and their second electrodes are electrically connected to the first electrode of the second transistor T442.

[0069] In one embodiment, transistors T470 to T47n may be of the same type as transistors T42, T43, T45, T441, and T442.

[0070] In one embodiment, transistors T470 to T47n in the second trimming circuit 47 are connected in parallel with each other.

[0071] According to one embodiment, when the first switch S443 is open, switches S460 to S46n in the first adjustment circuit 46 are open, and the second adjustment circuit 47 operates. By closing the switches in the second set of switches, the corresponding transistors are connected to the current mirror, reducing the equivalent size of the second transistor T442, thereby reducing the equivalent size of the main transistor group 44 and increasing the value of the ratio K. The number of closed switches in the second set of switches is selected according to actual needs.

[0072] In one embodiment, the size of transistors T470 to T47n can be, for example, 2%, 3%, 5% of the equivalent size of the main transistor group 44, with the specific percentage value related to the actual adjustment accuracy.

[0073] According to one embodiment, when the widths of transistors T470 to T47n in the second trimming circuit 47 are all approximately or the same as the width of the second transistor T442, the trimming accuracy of the ratio K can be improved more effectively.

[0074] According to one embodiment, the first trimming circuit 46 and the second trimming circuit 47 do not operate simultaneously.

[0075] According to one embodiment, in the first adjustment circuit 46, transistors T460 to T46n increase in size proportionally to each other, with a size ratio of a first fixed value. That is, the size ratio of one transistor to the size of the next transistor is a first fixed value, which can achieve a better ratio K adjustment effect. For example, the size ratio of transistor T461 to transistor T460 is 2, the size ratio of transistor T462 to transistor T461 is 2, and so on.

[0076] According to one embodiment, in the second adjustment circuit 47, transistors T470 to T47n increase in size proportionally to each other, with a size ratio of a second fixed value. That is, the size ratio of each transistor to the size of the preceding transistor is a second fixed value. In this case, a better ratio K adjustment effect can be obtained. For example, the size ratio of transistor T471 to transistor T470 is 3, the size ratio of transistor T472 to transistor T471 is 3, and so on.

[0077] In some embodiments, the first fixed value and the second fixed value can be equal, which makes it easier to control the trimming circuit and obtain good trimming accuracy.

[0078] In some embodiments, the transistors T460 to T46n in the first trimming circuit 46 may not have a fixed size ratio.

[0079] In some other embodiments of this application, the transistors T470 to T47n in the second trimming circuit 47 may not have a fixed size ratio.

[0080] For example, the equivalent width of the main transistor group 44 is W0, and the equivalent length is L0. The width of both the first transistor T441 and the second transistor T442 is 50%W0, meaning the value of x is 50%, and both have a length of L0. Ideally, the mirror current... Let transistor T45 have a channel width of KW0 and a channel length of L0. In this case, in the first adjustment circuit 46, the channel lengths of transistors T460 to T46n in the first group of transistors are all L0, with a first fixed value of 2, and the channel widths can be 2%W0, 4%W0, and 8%W0 respectively. In the second adjustment circuit 47, the channel widths of transistors T470 to T47n in the second group of transistors can all be 50%W0, with a second fixed value of 2, and the channel lengths can be 2%L0, 4%L0, and 8%L0 respectively.

[0081] When the ratio K is reduced, the first switch S443 closes and switches S470 to S47n in the second adjustment circuit 47 open, and the first adjustment circuit 46 operates. In this case, switch S460 closes, other switches open, transistor T460 is connected in the current mirror, and the adjusted ratio... When switches S460 and S461 are closed and other switches are closed, the adjusted ratio is... .

[0082] When the ratio K is increased, the first switch S443 and switches S460 to S46n in the first adjustment circuit 46 are opened, and the second adjustment circuit 47 is activated. In this case, switch S470 is closed, other switches are open, transistor T470 is connected in the current mirror, and the adjusted ratio... When switch S471 is closed and other switches are closed, the adjusted ratio When switch S472 is closed and other switches are closed, the adjusted ratio .

[0083] Figure 5 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application.

[0084] According to one embodiment, the current mirror includes a current source 51, a common-gate transistor T52, and a transistor T53. The current source 51 is configured to receive a supply voltage VDD and provide a reference current Iin. The first terminal of transistor T52 is electrically connected to the output of current source 51. The first terminal of transistor T53 provides a mirrored current Iout.

[0085] According to one embodiment, the current mirror also includes a master transistor group 54 electrically connected to the second terminal of transistor T52 and a slave transistor T55 electrically connected to the second terminal of transistor T53.

[0086] According to one embodiment, the main transistor group 54 includes two common-gate, common-source transistors, a first transistor T541 and a second transistor T542.

[0087] According to one embodiment, the first terminal of the first transistor T541 is electrically connected to the second terminal of the transistor T52.

[0088] According to one embodiment, the second terminals of the first transistor T541 and the second transistor T542 are respectively electrically connected to the second terminal of the transistor T55.

[0089] According to one embodiment, the control terminal of transistor T55 is electrically connected to the control terminals of the first transistor T541 and the second transistor T542, and is also electrically connected to the first terminal of transistor T52. The first terminal of transistor T55 is electrically connected to the second terminal of transistor T53.

[0090] According to one embodiment, the second terminal of transistor T55 is grounded.

[0091] According to one embodiment, the current mirror may include a first adjustment circuit 56 electrically connected between the first and second terminals of the first transistor T541, and / or a third adjustment circuit 57 electrically connected between the first terminal of the first transistor T541 and the first terminal of the second transistor T542, to achieve bidirectional adjustment of the contrast value K.

[0092] According to one embodiment, the first adjustment circuit 56 is configured to decrease the value of the ratio K when it operates. The third adjustment circuit 57 is configured to increase the value of the ratio K when it operates.

[0093] According to one embodiment, the first adjustment circuit 56 can be connected to... Figure 4 The first adjustment circuit 46 has a similar structure.

[0094] In one embodiment, the first trimming circuit 56 includes a first group of transistors sharing a common gate with the first transistor T541 and the second transistor T542, and a first group of switches. The first group of transistors includes transistors T560 to T56n, and the first group of switches includes switches S560 to S56n electrically connected between the first terminals of transistors T560 to T56n and the first terminal of the first transistor T541, respectively. The first group of switches is configured to electrically connect the first terminal of a corresponding transistor among transistors T560 to T56n to the first terminal of the first transistor T541 to increase the equivalent size of the second transistor T542.

[0095] According to one embodiment, the control electrodes of transistors T560 to T56n in the first group of transistors are electrically connected to each other and to the control electrodes of the first transistor T541 and the second transistor T542, respectively, and their second electrodes are electrically connected to the second electrode of the second transistor T542.

[0096] According to one embodiment, the third trimming circuit 57 includes a third set of transistors sharing a common gate with the first transistor T541 and the second transistor T542, and a third set of switches. The third set of transistors includes transistors T570 to T57n, and the third set of switches includes switches S570 to S57n electrically connected between the first and second terminals of each of the transistors T570 to T57n. The third set of switches is configured to disconnect the electrical connection between the first and second terminals of the respective transistors T570 to T57n to reduce the size of the second transistor T542.

[0097] According to one embodiment, in the third group of transistors, the control electrodes of transistors T570 to T57n are electrically connected to each other and also electrically connected to the control electrodes of the first transistor T541 and the second transistor T542. Transistors T570 to T57n are connected in series between the first electrode of the first transistor T541 and the first electrode of the second transistor T542. That is, the second electrode of transistor T570 in the third group of transistors is electrically connected to the first electrode of the second transistor T542, the second electrode of transistor T571 is electrically connected to the first electrode of transistor T570, and so on.

[0098] In one embodiment, transistors T570 to T57n may also be of the same type as transistors T52, T53, T55, T541, and T542.

[0099] According to one embodiment, as the number of disconnected switches in the third adjustment circuit 57 increases, the number of transistors electrically connected between the first terminal of the first transistor T541 and the first terminal of the second transistor T542 increases, and the number of transistors connected to the current mirror increases.

[0100] According to one embodiment, when the widths of transistors T570 to T57n in the third trimming circuit 57 are approximately the same as or the same as the width of the second transistor T542, the trimming accuracy of the ratio K can be improved more effectively.

[0101] In one embodiment of this application, the main transistor group 54 has an equivalent width of W0 and an equivalent length of L0. The first transistor T541 has a width of W01, and the second transistor T542 has a width of W02. The sum of their widths is the equivalent width W0 of the main transistor group 54, and both have a length of L0. The secondary transistor T55 has a width of W1 and a length of L1. The ratio In the third adjustment circuit 57, the lengths of transistors T570 to T57n are Ls1, Ls2...Lsn, respectively, and their widths are the same as the width of the second transistor T542. The ratio obtained after adjustment is... This is equivalent to reducing the ratio K by increasing the length of the main transistor group 54.

[0102] In one embodiment, the size of transistors T570 to T57n can be, for example, 1%, 2%, 5% of the equivalent size of the main transistor group 54, with the specific percentage value related to the actual adjustment accuracy.

[0103] According to one embodiment, the first trimming circuit 56 and the third trimming circuit 57 do not operate simultaneously.

[0104] According to one embodiment, when the first adjustment circuit 56 is operating, all switches S570 to S57n in the third adjustment circuit 57 are closed, and the first adjustment circuit 56 is electrically connected to the second transistor T542 through the third adjustment circuit 57. When all the first set of switches are open, the value of the ratio K is reduced by closing switches S560 to S56n.

[0105] According to one embodiment, when the third adjustment circuit 57 is operating, all switches S560 to S56n in the first adjustment circuit 56 are disconnected. By disconnecting one or more switches in the third group of switches, the equivalent size of the second transistor T542 is reduced, thereby reducing the equivalent size of the main transistor group 54 and increasing the value of the ratio K.

[0106] According to one embodiment, in the third adjustment circuit 57, transistors T570 to T57n increase in size proportionally to each other, with a size ratio of a third fixed value. That is, the size ratio of one transistor to the size of the next transistor is a third fixed value, which can achieve a better ratio K adjustment effect. For example, the size ratio of transistor T571 to transistor T570 is 5, the size ratio of transistor T572 to transistor T571 is 5, and so on.

[0107] In some embodiments, the third fixed value may be equal to the first fixed value of the size ratio between transistors T560 to T56n in the first group of transistors.

[0108] In some other embodiments of this application, in the third adjustment circuit 57, transistors T570 to T57n in the third group of transistors may not have a fixed size ratio.

[0109] In one embodiment of this application, the current mirror can also be equivalently divided from the transistors according to the error ratio. Figure 6 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application.

[0110] According to one embodiment, the current mirror includes a current source 81, a common-gate transistor T82, and a transistor T83. The current source 81 is configured to receive a supply voltage VDD and provide a reference current Iin. The first terminal of transistor T82 is electrically connected to the output of current source 81. The first terminal of transistor T83 provides a mirrored current Iout.

[0111] According to one embodiment, the current mirror further includes a master transistor T84 and a slave transistor group 85. The master transistor T84 is configured to receive a reference current Iin delivered by the transistor T82. The first terminal of the master transistor T84 is electrically connected to the second terminal of the transistor T82, which is grounded, and its control terminal is electrically connected to the first terminal of the transistor T82.

[0112] According to one embodiment, the transistor group 85 is electrically connected to the second terminal of transistor T83 and configured to generate a mirror current Iout that is proportional to the reference current Iin.

[0113] According to one embodiment, the transistor group 85 includes two common-gate transistors, a third transistor T851 and a fourth transistor T852.

[0114] According to one embodiment, the first terminal of the third transistor T851 is electrically connected to the second terminal of the transistor T83.

[0115] According to one embodiment, the current mirror may further include a second switch S853. The first terminal of the fourth transistor T852 is electrically connected between the first terminal of the third transistor T851 and the second terminal of the transistor T83 via the second switch S853. The first terminal of the second switch S853 is electrically connected to the first terminal of the third transistor T851, and its second terminal is electrically connected to the first terminal of the fourth transistor T852.

[0116] According to one embodiment, the second terminals of the third transistor T851 and the fourth transistor T852 are both electrically connected to the second terminal of the main transistor T84. The control terminals of the third transistor T851 and the fourth transistor T852 are electrically connected to the control terminal of the main transistor T84, and are also electrically connected to the first terminal of transistor T82.

[0117] According to one embodiment, the ratio of the equivalent size of transistor group 85 to the size of main transistor T84 is K, and the error ratio of ratio K is x. The size of the third transistor T851 can be 1 to x times the product of the size of main transistor T84 and ratio K, and the size of the fourth transistor T852 can be x times the product of the size of main transistor T84 and ratio K.

[0118] In one embodiment of this application, the lengths of the third transistor T851, the fourth transistor T852, and the main transistor T84 may be substantially equal or the same, while their widths may be unequal.

[0119] According to one embodiment, the width of the fourth transistor T852 can be x times the equivalent width of the transistor group 85, and the width of the third transistor T851 can be (1-x) times the equivalent width of the transistor group 85. For example, given that the equivalent length of the transistor group 85 is L1 and the equivalent width is W1, and the ideal ratio is K, the error ratio is set to x. In this case, the width of the third transistor T851... and the width of the fourth transistor T852 The lengths of the third transistor T851 and the fourth transistor T852 are both L1.

[0120] In another embodiment of this application, the widths of the third transistor T851, the fourth transistor T852, and the main transistor T84 may be substantially equal or the same, and their lengths may be unequal.

[0121] According to one embodiment, transistors T82, T83, main transistor T84, third transistor T851, and fourth transistor T852 can be of the same type, such as N-type transistors.

[0122] According to one embodiment, the current mirror may further include a fifth trimming circuit 86 and / or a sixth trimming circuit 87 electrically connected to the fourth transistor T852 to achieve bidirectional adjustment of the contrast value K.

[0123] In one embodiment, the fifth adjustment circuit 86 is configured to increase the ratio K. In one embodiment, the sixth adjustment circuit 87 is configured to decrease the ratio K.

[0124] According to one embodiment, the fifth adjustment circuit 86 can be connected to... Figure 4 The first adjustment circuit 46 has a similar structure.

[0125] According to one embodiment, the sixth adjustment circuit 87 can be connected to... Figure 4 The second adjustment circuit 47 has a similar structure.

[0126] In one embodiment, the fifth trimming circuit 86 includes a fifth group of transistors sharing a common gate with the third transistor T851 and the fourth transistor T852, and a fifth group of switches. The fifth group of transistors includes transistors T860 to T86n, and the fifth group of switches includes switches S860 to S86n electrically connected between the first terminals of transistors T860 to T86n and the first terminal of the second switch S853, respectively. The fifth group of switches is configured such that, when the second switch S853 is closed, a corresponding transistor among transistors T860 to T86n is connected in parallel with the fourth transistor T852 to increase the equivalent size of the fourth transistor T852.

[0127] In one embodiment, the control terminals of transistors T860 to T86n are electrically connected to each other and to the control terminals of the third transistor T851 and the fourth transistor T852, respectively, and their respective second terminals are electrically connected to the second terminal of the fourth transistor T852.

[0128] According to one embodiment, transistors T860 to T86n in the fifth trimming circuit 86 are connected in parallel with each other.

[0129] According to one embodiment, when the lengths of transistors T860 to T86n in the fifth adjustment circuit 86 are all approximately or the same as the equivalent lengths from transistor group 85, the adjustment accuracy of the ratio K can be improved more effectively.

[0130] According to one embodiment, the sixth trimming circuit 87 includes a sixth group of transistors sharing a common gate with the third transistor T851 and the fourth transistor T852, and a sixth group of switches. The sixth group of transistors includes transistors T870 to T87n, and the sixth group of switches includes switches S870 to S87n, respectively electrically connected between the first terminals of transistors T870 to T87n and the first terminal of the second switch S853. The sixth group of switches is configured to electrically connect the first terminals of the respective transistors T870 to T87n to the first terminal of the third transistor T851, thereby reducing the equivalent size of the fourth transistor T852.

[0131] According to one embodiment, the control electrodes of transistors T870 to T87n are electrically connected to each other and to the control electrodes of the third transistor T851 and the fourth transistor T852, respectively, with their second electrodes electrically connected to the first electrode of the fourth transistor T852.

[0132] According to one embodiment, when the widths of transistors T870 to T87n in the sixth adjustment circuit 87 are approximately the same as or the same as the width of the fourth transistor T852, the adjustment accuracy of the ratio K can be improved more effectively.

[0133] According to one embodiment, the fifth trimming circuit 86 and the sixth trimming circuit 87 do not operate simultaneously.

[0134] According to one embodiment, when the second switch S853 is open, all switches in the fifth adjustment circuit 86 are open. The sixth adjustment circuit 87 operates, closing the switches in the sixth group of switches, thereby reducing the equivalent size of the fourth transistor T852, and consequently reducing the equivalent size of the transistor group 75, and thus reducing the value of the ratio K.

[0135] According to one embodiment, when the second switch S853 is closed, the fifth adjustment circuit 86 operates, and all switches in the sixth adjustment circuit 87 are open. By closing the switches in the fifth group, the equivalent size of the transistor group 85 increases, and the value of the ratio K increases.

[0136] According to one embodiment, in the fifth trimming circuit 86, transistors T860 to T86n increase in size proportionally to each other, with a size ratio of a fifth fixed value. That is, the size ratio of each transistor to the size of its predecessor is a fifth fixed value.

[0137] According to one embodiment, in the sixth adjustment circuit 87, transistors T870 to T87n increase in size proportionally to each other, and the size ratio is a sixth fixed value.

[0138] In some embodiments, the fifth fixed value and the sixth fixed value may be equal.

[0139] In some other embodiments of this application, transistors T860 to T86n in the fifth trimming circuit 86, or transistors T870 to T87n in the sixth trimming circuit 87, do not have a fixed size ratio to each other.

[0140] Figure 7 The diagram shown is a schematic diagram of a current mirror structure according to another embodiment of this application.

[0141] According to one embodiment, the current mirror includes a current source 91, a common-gate transistor T92, and a transistor T93. The first terminal of transistor T92 is electrically connected to the output terminal of the current source 91.

[0142] According to one embodiment, the current mirror may further include a master transistor T94 and a slave transistor group 95. The first terminal of the master transistor T94 is electrically connected to the second terminal of transistor T92, which is grounded, and its control terminal is electrically connected to the first terminal of transistor T92. The master transistor T94 is configured to receive a reference current Iin from transistor T92, and the slave transistor group 95 is configured to generate a mirror current Iout proportional to the reference current Iin.

[0143] According to one embodiment, transistor group 95 includes two common-gate, common-source transistors, a third transistor T951 and a fourth transistor T952. The first terminal of the third transistor T951 is electrically connected to the second terminal of transistor T93. The second terminals of the third transistor T951 and the fourth transistor T952 are respectively electrically connected to the second terminal of the main transistor T94. The control terminals of the third transistor T951 and the fourth transistor T952 are also electrically connected to the control terminal of the main transistor T94, and are also electrically connected to the first terminal of the first transistor T92.

[0144] According to one embodiment, the current mirror further includes a fifth trimming circuit 96 and / or a seventh trimming circuit 97 electrically connected to the fourth transistor T952 to achieve bidirectional adjustment of the contrast value K.

[0145] According to one embodiment, the fifth trimming circuit 96 and the seventh trimming circuit 97 do not operate simultaneously. The fifth trimming circuit 96 is configured to increase the equivalent size of the transistor group 95, thereby increasing the value of the ratio K. The seventh trimming circuit 97 is configured to decrease the equivalent size of the transistor group 95, thereby decreasing the value of the ratio K.

[0146] According to one embodiment, the fifth adjustment circuit 96 can be connected with... Figure 6 The fifth trimming circuit 86 has a similar structure. The seventh trimming circuit 97 can be... Figure 5 The third adjustment circuit 57 has a similar structure.

[0147] In one embodiment, the fifth trimming circuit 96 includes a fifth group of transistors sharing a common gate with the third transistor T951 and the fourth transistor T952, and a fifth group of switches. The fifth group of transistors includes transistors T960 to T96n, and the fifth group of switches includes switches S960 to S96n electrically connected between the first terminals of transistors T960 to T96n and the first terminal of the third transistor T951, respectively. The fifth group of switches is configured to electrically connect the first terminals of corresponding transistors T960 to T96n to the first terminal of the third transistor T951 to increase the size of the fourth transistor T952.

[0148] According to one embodiment, the control electrodes of transistors T960 to T96n are electrically connected to each other and are also electrically connected to the control electrodes of the third transistor T951 and the fourth transistor T952, and their respective second electrodes are electrically connected to the second electrode of the fourth transistor T952.

[0149] According to one embodiment, the seventh trimming circuit 97 includes a seventh group of transistors sharing a common gate with the third transistor T951 and the fourth transistor T952, and a seventh group of switches. The seventh group of transistors includes transistors T970 to T97n, and the seventh group of switches includes switches S970 to S97n electrically connected between the first and second terminals of each of the transistors T970 to T97n. The seventh group of switches is configured to disconnect the electrical connection between the first and second terminals of the respective transistors T970 to T97n, thereby reducing the size of the fourth transistor T952.

[0150] According to one embodiment, the control electrodes of transistors T970 to T97n are electrically connected to each other, and their respective control electrodes are also electrically connected to the control electrodes of the third transistor T951 and the fourth transistor T952. Transistors T970 to T97n are connected in series between the first electrode of the third transistor T951 and the first electrode of the fourth transistor T952. That is, the second electrode of transistor T970 is electrically connected to the first electrode of the fourth transistor T952, the second electrode of transistor T971 is electrically connected to the first electrode of transistor T970, and so on.

[0151] According to one embodiment, when the widths of transistors T970 to T97n in the seventh trimming circuit 97 are approximately the same as or equal to the width of the fourth transistor T952, the trimming accuracy of the ratio K can be improved more effectively.

[0152] According to one embodiment, when the seventh adjustment circuit 97 is operating, all switches in the fifth adjustment circuit are open. By opening one or more switches from switch S970 to switch S97n, the equivalent size of the transistor group 95 is reduced, and the value of the ratio K is reduced.

[0153] According to one embodiment, when the fifth adjustment circuit 96 is operating, all switches S970 to S97n in the seventh adjustment circuit 97 are closed, and the fifth adjustment circuit 96 is electrically connected between the first and second terminals of the fourth transistor T952. By closing the switches in the fifth group of switches, the equivalent size of the transistor group 95 is increased, thereby increasing the value of the ratio K.

[0154] According to one embodiment, in the seventh adjustment circuit 97, transistors T970 to T97n increase in size proportionally to each other, and the size ratio is a seventh fixed value.

[0155] In some embodiments, the seventh fixed value may be equal to or unequal to the fifth fixed value of the fifth adjustment circuit 96.

[0156] This application also includes an electronic device comprising a current mirror as described in any of the preceding descriptions. The current mirror includes a master transistor group and / or a slave transistor group, and, as described in any of the preceding descriptions, a tuning circuit.

[0157] The high-precision current mirror proposed in this application can accurately adjust the ratio of the mirror current to the reference current, greatly improving the accuracy of the mirror current output by the current mirror. At the same time, it saves circuit layout and cost, and has high reliability and stability.

[0158] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A high-precision current mirror, characterized in that, include: The main transistor group is configured to receive a reference current. The transistor is configured to generate a mirror current that is proportional to the reference current; The main transistor group includes a first transistor and a second transistor, whose control electrodes are electrically connected to each other; the second electrodes of both the first and second transistors are grounded; the equivalent size ratio of the slave transistor to the main transistor group is a ratio K; the size of the first transistor is 1-x times the ratio of the slave transistor size to the ratio K, and the size of the second transistor is x times the ratio of the slave transistor size to the ratio K; where x is the percentage of the difference between the actual and expected values ​​of the ratio K; and... A first adjustment circuit, electrically connected to the second transistor, is configured to decrease the ratio K; and, A second adjustment circuit, electrically connected to the second transistor, is configured to increase the ratio K. Wherein, the first terminal of the second transistor is electrically connected to the first terminal of the first transistor via a first switch; wherein, the first terminal of the first switch is electrically connected to the first terminal of the first transistor.

2. The high-precision current mirror according to claim 1, characterized in that, in, The value of x is a percentage no greater than 20%.

3. The high-precision current mirror according to claim 1, characterized in that, The first adjustment circuit includes... The first group of transistors includes one or more transistors connected in parallel with each other; the control electrode of each transistor in the first group of transistors is electrically connected to the control electrode of the first transistor and the control electrode of the second transistor; and the second electrode of each transistor in the first group of transistors is electrically connected to the second electrode of the second transistor. as well as, The first set of switches includes one or more switches, which are electrically connected between the first terminal of a corresponding transistor in the first set of transistors and the first terminal of the second transistor.

4. The high-precision current mirror according to claim 3, characterized in that, The length of each transistor in the first group of transistors is equal to the equivalent length of the main transistor group.

5. The high-precision current mirror according to claim 1, characterized in that, The second adjustment circuit includes, The second group of transistors includes one or more transistors connected in parallel with each other; The control electrode of each transistor in the second group of transistors is electrically connected to the control electrodes of the first transistor and the second transistor; and the second electrode of each transistor in the second group of transistors is electrically connected to the first electrode of the second transistor; and, The second group of switches includes one or more switches; each switch in the second group of switches is electrically connected between the first terminal of each transistor in the second group of transistors and the first terminal of the first transistor.

6. The high-precision current mirror according to claim 5, characterized in that, The width of each transistor in the second group is equal to the width of the second transistor.

7. The high-precision current mirror according to claim 1, characterized in that, The second adjustment circuit includes, The third group of transistors includes one or more transistors connected in series between the first terminal of the first transistor and the first terminal of the second transistor; The control electrode of each transistor in the third group of transistors is electrically connected to the control electrode of the first transistor and the second transistor; and, The third group of switches includes one or more switches; each switch in the third group of switches is electrically connected between the first and second terminals of the respective transistors in the third group of transistors.

8. The high-precision current mirror according to claim 7, characterized in that, The width of each transistor in the third group of transistors is equal to the width of the second transistor.

9. An electronic device, characterized in that, Includes the high-precision current mirror as described in any one of claims 1-8.

10. A high-precision current mirror, characterized in that, include: The main transistor is configured to receive a reference current; The transistor array is configured to generate a mirror current that is proportional to the reference current; The slave transistor group includes a third transistor and a fourth transistor, whose control electrodes are electrically connected to each other; the second electrodes of both the third and fourth transistors are grounded; the ratio of the equivalent size of the slave transistor group to the size of the master transistor is a ratio K; the size of the third transistor is 1-x times the product of the master transistor size and the ratio K; and the size of the fourth transistor is x times the product of the master transistor size and the ratio K; where x is the percentage of the difference between the actual and expected values ​​of the ratio K; and... A fifth adjustment circuit, electrically connected to the fourth transistor, is configured to increase the ratio K; and, A sixth adjustment circuit, electrically connected to the fourth transistor, is configured to reduce the ratio K. The first terminal of the fourth transistor is electrically connected to the first terminal of the third transistor via a second switch; wherein the first terminal of the second switch is electrically connected to the first terminal of the third transistor.

11. The high-precision current mirror according to claim 10, characterized in that, in, The value of x is a percentage no greater than 20%.

12. The high-precision current mirror according to claim 10, characterized in that, in, The fifth adjustment circuit includes: The fifth group of transistors includes one or more transistors connected in parallel with each other, wherein the control electrode of each transistor in the fifth group of transistors is electrically connected to the control electrode of the third transistor and the fourth transistor; and the second electrode of each transistor in the fifth group of transistors is electrically connected to the second electrode of the fourth transistor. as well as, The fifth group of switches includes one or more switches, which are electrically connected between the first terminal of the corresponding transistor in the fifth group of transistors and the first terminal of the fourth transistor, respectively.

13. The high-precision current mirror according to claim 12, characterized in that, The length of each transistor in the fifth group is equal to the equivalent length of the slave transistor group.

14. The high-precision current mirror according to claim 10, characterized in that, The sixth adjustment circuit includes: A sixth group of transistors includes one or more transistors connected in parallel with each other; the control electrode of each transistor in the sixth group is electrically connected to the control electrodes of the third and fourth transistors; and the second electrode of each transistor in the sixth group is electrically connected to the first electrode of the fourth transistor; and, The sixth group of switches includes one or more switches, each of which is electrically connected between the first terminal of each transistor in the sixth group of transistors and the first terminal of the third transistor.

15. The high-precision current mirror according to claim 14, characterized in that, The width of each transistor in the sixth group is equal to the width of the fourth transistor.

16. The high-precision current mirror according to claim 10, characterized in that, in, The sixth adjustment circuit includes: The seventh group of transistors includes one or more transistors connected in series between the first terminal of the third transistor and the first terminal of the second transistor; The control electrode of each transistor in the seventh group of transistors is electrically connected to the control electrode of the third and fourth transistors; and, The seventh group of switches includes one or more switches; each switch in the seventh group of switches is electrically connected between the first and second terminals of the corresponding transistors in the seventh group of transistors.

17. The high-precision current mirror according to claim 16, characterized in that, The width of each transistor in the seventh group is equal to the width of the fourth transistor.

18. An electronic device, characterized in that, Includes the high-precision current mirror as described in any one of claims 11-17.

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