Super through hole interconnection structure and manufacturing method thereof

Abstract

The invention provides a super through hole interconnection structure and a manufacturing method thereof, and particularly relates to the field of semiconductors. The manufacturing method comprises the following steps: forming a first metal interconnection structure in a first dielectric layer; sequentially forming a second dielectric layer and a dielectric barrier layer on the first dielectric layer, wherein the etching rate of the dielectric barrier layer is smaller than that of the second dielectric layer; forming a second metal interconnection structure in the dielectric barrier layer and the second dielectric layer, wherein the top of the second metal interconnection structure is lower than the top of the dielectric barrier layer; forming a third dielectric layer on the dielectric barrier layer; a third metal interconnection structure is formed in the third dielectric layer, meanwhile, a super through hole penetrating through the dielectric barrier layer and the second dielectric layer is formed, and the third metal interconnection structure is electrically connected with the first metal interconnection structure through the super through hole. According to the manufacturing method, the problems of offset and dislocation in the etching process of the super through hole can be solved, and therefore the problems of bridging and TDDB failure are effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a super through-hole interconnection structure and a manufacturing method thereof. Background Art

[0002] As chip manufacturing processes continue to shrink, the performance of interconnect structures has gradually become a key factor restricting the overall performance of the chip, and super via (SV) technology has emerged. Super vias are a type of through-hole technology that penetrates multiple dielectric layers to connect one or more metal interconnect structures in a dielectric layer to the metal interconnect structure below the dielectric layer. Compared with traditional single-layer vias, super vias can effectively reduce wiring impedance and parasitic capacitance. However, edge placement error (EPE) during super via etching causes misalignment between the super via and the adjacent intermediate metal layer, which may cause process defects such as super via-intermediate layer metal interconnect structure bridging or TDDB (Time-Dependent Dielectric Breakdown) failure, thereby affecting device yield and reliability.

[0003] Therefore, it is necessary to provide a super via interconnect structure and a manufacturing method thereof to improve the above problems. Summary of the Invention

[0004] In view of the above problems existing in the prior art, the present invention provides a super via interconnect structure and a manufacturing method thereof, so as to improve the problem of edge position error in the super via etching process.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides, in a first aspect, a method for manufacturing a super via interconnect structure, comprising the following steps: forming a first metal interconnect structure in the first dielectric layer; forming a second dielectric layer and a dielectric barrier layer in sequence on the first dielectric layer, wherein the etching rate of the dielectric barrier layer is lower than the etching rate of the second dielectric layer; forming a second metal interconnect structure in the dielectric barrier layer and the second dielectric layer, wherein a top of the second metal interconnect structure is lower than a top of the dielectric barrier layer; forming a third dielectric layer on the dielectric barrier layer; A third metal interconnect structure is formed in the third dielectric layer, and a super via is formed simultaneously penetrating the dielectric barrier layer and the second dielectric layer, wherein the super via electrically connects the third metal interconnect structure with the first metal interconnect structure.

[0006] In one embodiment of the present invention, forming a second metal interconnect structure in the dielectric barrier layer and the second dielectric layer includes: forming a second metal interconnection trench on the dielectric barrier layer and the second dielectric layer; filling the second metal interconnect trench with a conductive material; A portion of the conductive material in the second metal interconnection trench is removed by etching, so that a top of the conductive material is lower than a top of the dielectric barrier layer, thereby forming a second metal interconnection structure.

[0007] In one embodiment of the present invention, in the step of etching away a portion of the conductive material in the second metal interconnect trench, the thickness of the removed conductive material is such that the height difference between the top of the second metal interconnect structure and the top of the dielectric barrier layer is less than or equal to half the thickness of the dielectric barrier layer.

[0008] In one embodiment of the present invention, before forming the second metal interconnect trench on the dielectric barrier layer and the second dielectric layer, the method includes: forming a first patterned mask layer on the dielectric barrier layer, wherein the first patterned mask layer has a plurality of first openings exposing the dielectric barrier layer, the first openings corresponding to positions of the second metal interconnect trenches and super vias to be formed subsequently; Using the first patterned mask layer as a mask, etching and removing the dielectric barrier layer exposed in the first opening to form a plurality of trenches; removing the first patterned mask layer, and forming a low dielectric constant material layer in the plurality of trenches and on the dielectric barrier layer on both sides of the trenches; planarizing the low-k material layer, removing the low-k material layer on the dielectric barrier layer, and forming a filling layer with the low-k material remaining in the trench; forming a second patterned mask layer on the dielectric barrier layer, wherein the second patterned mask layer has a plurality of second openings exposing the filling layer, and the filling layer corresponding to the position of the super via is covered by the second patterned mask layer; The second patterned mask layer is used as a mask to etch and remove the filling layer and a portion of the second dielectric layer exposed in the second opening to form a second metal interconnection trench.

[0009] In one embodiment of the present invention, the material of the dielectric barrier layer includes one or more of TEOS, SiON, and SiCN; and / or the thickness of the formed dielectric barrier layer is 5-20 nm.

[0010] In one embodiment of the present invention, before filling the second metal interconnect trench with a conductive material, the method further includes: forming a diffusion barrier layer on an inner wall of the second metal interconnect trench; and / or, After forming the second metal interconnect structure, the method further includes: forming a second etch stop layer on top of the dielectric barrier layer and the second metal interconnect structure.

[0011] In one embodiment of the present invention, forming a third metal interconnect structure in the third dielectric layer and simultaneously forming a super via penetrating the dielectric barrier layer and the second dielectric layer includes: forming a third patterned mask layer on the third dielectric layer, wherein the third patterned mask layer has a third opening exposing the third dielectric layer, and an area of ​​the third opening at least includes the filling layer covered by the second patterned mask layer; Using the third patterned mask layer as a mask, etching the third dielectric layer, the filling layer, and the second dielectric layer until the first metal interconnect structure is exposed to form a through-hole trench, and etching the periphery of the through-hole trench in the third dielectric layer to form a third metal interconnect trench connected to the through-hole trench; forming a diffusion barrier layer on inner walls of the third metal interconnect trench and the through-hole trench; A conductive material is filled on the diffusion barrier layer, and a third metal interconnection structure and a super via are formed at the same time.

[0012] A second aspect of the present invention provides a super via interconnect structure, comprising: a first dielectric layer, a second dielectric layer, a dielectric barrier layer, a third dielectric layer and a super via, wherein a first metal interconnect structure is provided inside the first dielectric layer, the second dielectric layer is arranged on the first dielectric layer, and a second metal interconnect structure is provided inside the second dielectric layer, the dielectric barrier layer is arranged on the second dielectric layer, and the top of the second metal interconnect structure is lower than the top of the dielectric barrier layer, and the etching rate of the dielectric barrier layer is lower than the etching rate of the second dielectric layer; the third dielectric layer is arranged on the dielectric barrier layer, and a third metal interconnect structure is provided inside the third dielectric layer; the super via passes through the dielectric barrier layer and the second dielectric layer, and electrically connects the first metal interconnect structure with the third metal interconnect structure.

[0013] In one embodiment of the present invention, a height difference between a top of the second metal interconnect structure and a top of the dielectric barrier layer is less than or equal to half the thickness of the dielectric barrier layer.

[0014] In one embodiment of the present invention, the material of the dielectric barrier layer includes one or more of TEOS, SiON, and SiCN; and / or the thickness of the dielectric barrier layer is 5-20 nm.

[0015] The present invention's method for fabricating a supervia interconnect structure forms a dielectric barrier layer between the second and third dielectric layers, and the dielectric barrier layer has a lower etching rate than the second dielectric layer. During the supervia etching process, the dielectric barrier layer prevents etching offset, facilitating self-alignment of the supervia. It also effectively mitigates bridging issues and / or TDDB failures between the metal layer and the supervia within the dielectric layer where the dielectric barrier layer resides, thereby improving product yield and reliability. Furthermore, during the fabrication of the second metal interconnect structure, the conductive material filling its trench is partially etched, lowering the top of the second metal interconnect structure below the top of the dielectric barrier layer. This increases the distance between the second metal interconnect structure and the supervia, further mitigating bridging and / or TDDB failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A flow chart of a method for manufacturing a super via interconnect structure according to an embodiment of the present invention; Figure 2 A schematic structural diagram of forming a first metal interconnection structure in a first dielectric layer in an embodiment of a method for manufacturing a super via interconnection structure according to the present invention; Figure 3 A schematic structural diagram of forming a first etch stop layer on a first dielectric layer in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention; Figure 4 A schematic structural diagram of forming a second dielectric layer and a dielectric barrier layer on a first dielectric layer in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 5 A schematic structural diagram of forming a first patterned mask layer on a dielectric barrier layer in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 6 A schematic diagram of a method for manufacturing a super via interconnect structure of the present invention, in one embodiment, wherein a portion of the dielectric barrier layer is etched away to form a plurality of grooves; Figure 7 A schematic structural diagram of removing the first patterned mask layer in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 8A schematic structural diagram of forming a low-k material layer in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention; Figure 9 A schematic structural diagram of forming a filling layer in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 10 Schematic diagram of the structure of forming a second patterned mask layer in one embodiment of the method for manufacturing a super via interconnect structure of the present invention; Figure 11 A schematic structural diagram of forming a second metal interconnection trench in an embodiment of a method for manufacturing a super via interconnection structure according to the present invention; Figure 12 A schematic structural diagram of filling a conductive material in a second metal interconnect trench in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 13 A schematic structural diagram of etching a portion of the conductive material to form a second metal interconnect structure in an embodiment of a method for manufacturing a super via interconnect structure of the present invention; Figure 14 A schematic structural diagram of forming an etch stop layer on a second dielectric layer in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention; Figure 15 A schematic structural diagram of forming a third dielectric layer in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention; Figure 16 A schematic structural diagram of forming a third patterned mask layer in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention; Figure 17 A schematic structural diagram of etching the third dielectric layer, the dielectric barrier layer, and the second dielectric layer to form a through-hole trench in an embodiment of a method for manufacturing a super through-hole interconnect structure of the present invention; Figure 18 A schematic structural diagram of forming a third metal interconnection trench in an embodiment of a method for manufacturing a super via interconnection structure according to the present invention; Figure 19 FIG. 1 is a schematic structural diagram of forming a third metal interconnect structure and a super via in an embodiment of a method for manufacturing a super via interconnect structure according to the present invention.

[0018] Component number description: 100, first dielectric layer; 110, first metal interconnect structure; 111, first metal interconnect trench; 112, first diffusion barrier layer; 113, first etch stop layer; 200, second dielectric layer; 210, dielectric barrier layer; 211, trench; 212, low-k material layer; 213, filling layer; 220, first patterned mask layer; 221, first opening; 230, second patterned mask layer; 231, second opening; 240, second metal interconnect structure; 24 1. Second metal interconnect trench; 242. Second diffusion barrier layer; 250. Second etch stop layer; 300. Third dielectric layer; 310. Third patterned mask layer; 311. Third opening; 312. Fourth opening; 320. Third metal interconnect structure; 321. Third metal interconnect trench; 322. Third diffusion barrier layer; 330. Third etch stop layer; 400. Super via; 410. Second via trench; 500. First via; 510. First via trench. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0020] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0021] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0022] In the present invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate and simplify the description of the present application and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0023] Super vias need to penetrate multiple dielectric layers. Improper process control during etching (such as uneven etching rate and mask alignment deviation) will lead to deviations between the actual etched pattern edge and the designed position (edge ​​position error, EPE). Edge position error will cause misalignment between the super via and the adjacent intermediate layer metal interconnect structure, causing process defects such as bridging or TDDB failure, thereby affecting device yield and reliability.

[0024] Based on this, the present invention provides a super via interconnect structure and a manufacturing method thereof, which utilizes a dielectric barrier layer to prevent super via etching offset, thereby preventing the super via from bridging with the metal interconnect structure of the intermediate layer.

[0025] See also Figures 1 to 19 The present invention provides a method for manufacturing a super through-hole interconnection structure, comprising the following steps: S1, forming a first metal interconnect structure 110 in the first dielectric layer 100; S2, sequentially forming a second dielectric layer 200 and a dielectric barrier layer 210 on the first dielectric layer 100, wherein the etching rate of the dielectric barrier layer 210 is lower than the etching rate of the second dielectric layer 200; S3, forming a second metal interconnect structure 240 in the dielectric barrier layer 210 and the second dielectric layer 200, wherein the top of the second metal interconnect structure 240 is lower than the top of the dielectric barrier layer 210; S4, forming a third dielectric layer 300 on the dielectric barrier layer 210; S5 . Form a third metal interconnect structure 320 in the third dielectric layer 300 , and simultaneously form a super via 400 penetrating the dielectric barrier layer 210 and the second dielectric layer 200 . The super via 400 electrically connects the third metal interconnect structure 320 with the first metal interconnect structure 110 .

[0026] The super via interconnect structure of the present invention is formed on a semiconductor substrate. This semiconductor substrate can be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, a silicon-on-insulator substrate, or any other semiconductor substrate known in the art. Semiconductor devices such as transistors can be formed within the semiconductor substrate, and those skilled in the art can configure the structure based on actual needs. For the sake of simplicity, the semiconductor substrate and the semiconductor devices formed thereon are not depicted in this invention.

[0027] In the present invention, the first metal interconnect structure 110 can be understood as a metal wiring structure located at a lower layer, the second metal interconnect structure 240 can be understood as a metal wiring structure located at an intermediate layer, and the third metal interconnect structure 320 can be understood as a metal wiring structure located at a higher layer. The first metal interconnect structure 110 and the third metal interconnect structure 320 need to be connected across layers using super vias 400. The second metal interconnect structure 240 and the third metal interconnect structure 320, or the second metal interconnect structure 240 and the first metal interconnect structure 110, can be connected to adjacent layers using conventional vias as needed.

[0028] The following combination Figures 2 to 19 The steps of the method for manufacturing the super through-hole interconnection structure of the present invention are introduced in detail.

[0029] See also Figure 2 In step S1, a first dielectric layer 100 is formed on a semiconductor substrate (not shown). First dielectric layer 100 is made of a dielectric material with a low dielectric constant (low-k), preferably a dielectric material with k < 3. Exemplary materials for first dielectric layer 100 include, but are not limited to, SiCOH, porous SiCOH, and SiOC. In this embodiment, first dielectric layer 100 is made of SiCOH. First dielectric layer 100 can be formed using conventional deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0030] The first metal interconnect structure 110 can be formed in the first dielectric layer 100 according to conventional processes in the art. For example, a patterned mask layer (not shown) is first formed on the first dielectric layer 100. The patterned mask layer is used to define the position of the first metal interconnect structure 110. The patterned mask layer can be a photoresist layer. Then, using the patterned mask layer as a mask, a portion of the first dielectric layer 100 is etched away to form the first metal interconnect trench 111. The etching process can be, for example, dry etching, wet etching, or a combination of both. After removing the patterned mask layer, the first metal interconnect trench 111 is filled with a conductive material to form the first metal interconnect structure 110. The conductive material filling method can be, for example, electrochemical plating (ECP). During the ECP process, a certain thickness of conductive material layer will also form on the surface of the first dielectric layer 100. Therefore, the conductive material layer needs to be planarized, such as by chemical mechanical polishing (CMP), to remove the conductive material layer on the surface of the first dielectric layer 100. The remaining filler material in the first metal interconnect trench 111 forms the first metal interconnect structure 110. The above-mentioned conductive material can be copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), and other conventional conductive materials in the art.

[0031] In some embodiments, before filling the conductive material, a first diffusion barrier layer 112 is formed on the inner wall of the first metal interconnect trench 111 to prevent the conductive material of the first metal interconnect structure 110 from diffusing into the surrounding first dielectric layer 100. The material of the first diffusion barrier layer 112 may be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or any combination thereof. In this embodiment, the material of the first diffusion barrier layer 112 is TaN. The first diffusion barrier layer 112 may be formed by a deposition process such as PVD, CVD, or ALD. Furthermore, a seed layer (not shown) may be formed on the first diffusion barrier layer 112. The seed layer facilitates the subsequent electrochemical deposition (ECP) of the metal interconnect structure and ensures good adhesion between the interconnect metal structure and the underlying structure. The seed layer may be made of the same conductive material as the first metal interconnect structure 110, such as copper, or a different conductive material, such as ruthenium (Ru), although this application is not limited thereto.

[0032] See also Figure 3In one embodiment, after performing step S1, the process further includes forming a first etch stop layer 113 on the surfaces of the first dielectric layer 100 and the first metal interconnect structure 110. The first etch stop layer 113 can serve as a stop layer in the subsequent etching process to protect the first metal interconnect structure 110 thereunder from etching damage. The material of the first etch stop layer 113 includes, but is not limited to, aluminum nitride (AlN), silicon nitride (SiN), or silicon carbonitride (SiCN). The first etch stop layer 113 can be formed using conventional techniques in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0033] See also Figure 4 , step S2 is performed to sequentially form a second dielectric layer 200 and a dielectric barrier layer 210 on the first dielectric layer 100. When the first etch stop layer 113 is formed on the first dielectric layer 100, the second dielectric layer 200 and the dielectric barrier layer 210 are sequentially formed on the first etch stop layer 113.

[0034] The second dielectric layer 200 is used to provide support for the subsequent formation of the second metal interconnect structure 240 and to insulate and isolate the first metal interconnect structure 110 from the second metal interconnect structure 240. The second dielectric layer 200 is made of the same or different low-k dielectric material as the first dielectric layer 100. In this embodiment, the second dielectric layer 200 is made of the same low-k dielectric material as the first dielectric layer 100, SiCOH. The formation process is similar to that of the first dielectric layer 100. A dielectric barrier layer 210 is formed on the second dielectric layer 200. Dielectric barrier layer 210 is used to prevent offset during subsequent etching. Therefore, dielectric barrier layer 210 is made of a different dielectric material than the second dielectric layer 200, and the etching rate of dielectric barrier layer 210 is much lower than that of the second dielectric layer 200. In other words, there is a high etching selectivity between the second dielectric layer 200 and dielectric barrier layer 210. In some embodiments, the material of dielectric barrier layer 210 includes one or more of TEOS, SiON, and SiCN. That is, dielectric barrier layer 210 can be made of a single material, such as TEOS, or a combination of two or more materials, such as a combination layer of SiON and SiCN. The thickness of dielectric barrier layer 210 should not be too large or too small. If it is too large, it will increase the parasitic capacitance of the device and affect signal transmission. If it is too small, it may be completely etched and fail to serve as a barrier. Therefore, in the present application, the thickness of dielectric barrier layer 210 is 5 to 20 nm. For example, it can be 5 nm, 10 nm, 15 nm, or 20 nm. Dielectric barrier layer 210 can be formed using deposition processes such as CVD and PVD.

[0035] Step S3 is performed to form a second metal interconnect structure 240 in the dielectric barrier layer 210 and the second dielectric layer 200, including the following steps: See also Figure 5 , forming second metal interconnect trenches 241 on the dielectric barrier layer 210 and the second dielectric layer 200. The specific process is as follows: First, a first patterned mask layer 220 is formed on the dielectric barrier layer 210. The first patterned mask layer 220 has a plurality of first openings 221 that expose the dielectric barrier layer 210. The first openings 221 correspond to the positions of the second metal interconnect structures 240 and super vias 400 to be formed subsequently. In this embodiment, the first openings 221 correspond one-to-one to the positions of the underlying first metal interconnect structures 110. The first patterned mask layer 220 can be a patterned photoresist layer, which is formed by spin-coating photoresist on the dielectric barrier layer 210, exposing and developing to remove the photoresist in the areas where the first openings 221 are to be formed.

[0036] See also Figure 6 and Figure 7 Then, using the first patterned mask layer 220 as a mask, the exposed dielectric barrier layer 210 within the first opening 221 is etched away to form a plurality of trenches 211. The etching method can be dry etching, wet etching, or a combination of dry and wet etching. The remaining dielectric barrier layer 210 acts as a barrier during the subsequent etching of the super via 400, thereby improving EPE deviation.

[0037] See also Figure 7 and Figure 8 Then, the first patterned mask layer 220 is removed, and a low-k material layer 212 is formed on the dielectric barrier layer 210 in the plurality of trenches 211 and on both sides of the trenches 211. The first patterned mask layer 220 can be removed by an ashing process or a stripping process. The low-k material layer 212 can be formed by a deposition process such as CVD or PVD. The low-k material layer 212 is made of a material with a dielectric constant k less than 3, such as SiCOH, porous SiCOH, or SiOC, which can be the same as the material of the second dielectric layer 200 or different from the material of the second dielectric layer 200. In this embodiment, the low-k material layer 212 uses the same dielectric material SiCOH as the second dielectric layer 200.

[0038] See also Figure 9 Next, the low-k material layer 212 is planarized to remove the low-k material layer 212 on the dielectric barrier layer 210. The low-k material layer 212 remaining in the trench 211 forms a filling layer 213. The planarization step may be, for example, chemical mechanical polishing (CMP), with the dielectric barrier layer 210 serving as a stop layer.

[0039] See also Figure 10Next, a second patterned mask layer 230 is formed on the dielectric barrier layer 210. The second patterned mask layer 230 has a plurality of second openings 231 that expose the fill layer 213. Since the second patterned mask layer 230 is used to define the second metal interconnect structure 240, the second openings 231 correspond to the locations of the second metal interconnect structure 240 to be formed later. In this embodiment, the fill layer 213 corresponding to the super via 400 (the middle position) is covered by the second patterned mask layer 230, while the fill layer 213 at the remaining positions is exposed by the second openings 231. The second patterned mask layer 230 can be a patterned photoresist layer formed through processes such as spin coating, exposure, and development. Furthermore, since the etching rate of the dielectric barrier layer 210 is much lower than that of the fill layer 213 and the second dielectric layer 200, which are composed of low-k materials, the area of ​​the second openings 231 can be larger than the width of the fill layer 213, providing a certain amount of redundancy. This reduces the exposure requirements during the formation of the second patterned mask layer 230, thereby reducing the process difficulty.

[0040] See also Figure 11 Then, using the second patterned mask layer 230 as a mask, the exposed filler layer 213 and a portion of the second dielectric layer 200 within the second opening 231 are etched away to form a second metal interconnect trench 241. The etching process can be dry etching, wet etching, or a combination of both. The second patterned mask layer 230 is then removed using conventional processes such as ashing or stripping.

[0041] See also Figure 12 , a conductive material is filled in the second metal interconnect trench 241 .

[0042] The conductive material in this step can be a material with good conductivity, such as copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co). The filling method can be ECP. During the ECP process, a certain thickness of conductive material will also form on the surface of the dielectric barrier layer 210. Therefore, the conductive material must be planarized, such as by chemical mechanical polishing (CMP), to remove the conductive material from the surface of the dielectric barrier layer 210. The conductive material remaining within the second metal interconnect trench 241 forms the second metal interconnect structure 240. In some embodiments of the present invention, before filling with the conductive material, a diffusion barrier layer, referred to as the second diffusion barrier layer 242, can be formed on the inner wall of the second metal interconnect trench 241 to prevent the conductive material of the second metal interconnect structure 240 from diffusing into the surrounding second dielectric layer 200. Furthermore, a sublayer (not shown) can be formed on the second diffusion barrier layer 242 to facilitate the subsequent ECP process of the metal interconnect structure and ensure good adhesion between the conductive material and the underlying structure.

[0043] See also Figure 13, a portion of the conductive material in the second metal interconnect trench 241 is etched away so that the top of the conductive material is lower than the top of the dielectric barrier layer 210 , thereby forming a second metal interconnect structure 240 .

[0044] The top of the second metal interconnect structure 240 is lower than the dielectric barrier layer 210 , which can increase the distance between the second metal interconnect structure 240 and the subsequently formed super via 400 , further improving the bridging problem between the metal and the super via 400 .

[0045] In one embodiment, a portion of the conductive material is removed by wet etching. Exemplarily, the conductive material is etched using a combination of SC1 (Standard Clean 1) and dHF (diluted hydrofluoric acid). SC1 consists of ammonia (NH₄OH), hydrogen peroxide (H₂O₂), and deionized water (DIW). SC1 is first used to remove organic contaminants (such as photoresist residue) and particles from the wafer surface (through oxidation and micro-etching). Then, dHF is used to etch the conductive material. The amount of etched material removed is such that the height difference between the top of the ultimately formed second metal interconnect structure 240 and the top of the dielectric barrier layer 210 is less than or equal to half the thickness of the dielectric barrier layer 210. Specifically, the amount of etched material removed is related to the thickness of the dielectric barrier layer 210. For example, if the dielectric barrier layer 210 is 10 nm thick, the amount of etched material removed is such that the height difference between the top of the second metal interconnect structure 240 and the top of the dielectric barrier layer 210 is less than or equal to 5 nm.

[0046] In some embodiments, before filling the conductive material, a second diffusion barrier layer 242 is formed on the inner wall of the second metal interconnect trench 241 . Therefore, after removing part of the conductive material, part of the second diffusion barrier layer 242 needs to be etched away. The second diffusion barrier layer 242 is etched, for example, by wet etching using an etchant that is selective for the second diffusion barrier layer 242. For example, if the second diffusion barrier layer 242 is TaN, the etchant includes deionized water, hydrogen peroxide (H2O2), benzotriazole (BTA), 1,2-cyclohexanediaminetetraacetic acid (CDTA), and potassium hydroxide (KOH). Deionized water is used as the solvent, and the remaining components are 15% H2O2 by mass, 10 g / L BTA, and 0.5 g / L CDTA. The amount of KOH added is such that the pH of the etchant is between 4 and 12. For example, the pH of the etchant can be 4, 8, 10, or 12. In other embodiments, KOH can be replaced with other alkaline substances, such as NaOH. The etched removal size of the second diffusion barrier layer 242 is consistent with the etched removal size of the conductive material.

[0047] See also Figure 14 In some embodiments, after the second metal interconnect structure 240 is formed, a second etch stop layer 250 is further formed on top of the dielectric barrier layer 210 and the second metal interconnect structure 240. The second etch stop layer 250 can act as a stop layer in the subsequent etching process to protect the second metal interconnect structure 240 below it from etching damage. The material of the second etch stop layer 250 includes but is not limited to aluminum nitride (AlN), silicon nitride (SiN), or silicon carbonitride (SiCN). The second etch stop layer 250 can be formed using conventional techniques in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0048] See also Figure 15 , step S4 is performed to form a third dielectric layer 300 on the dielectric barrier layer 210 . If the second etch stop layer 250 is formed on the dielectric barrier layer 210 , the third dielectric layer 300 is formed on the second etch stop layer 250 .

[0049] The third dielectric layer 300 is made of a low-k dielectric material, such as a dielectric material with k < 3. Exemplarily, the material of the third dielectric layer 300 includes, but is not limited to, SiCOH, porous SiCOH, SiOC, and the like. In this embodiment, the material of the third dielectric layer 300 is SiCOH. The third dielectric layer 300 can be formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0050] See also Figures 16 to 19 , executing step S5, forming a third metal interconnect structure 320 in the third dielectric layer 300, and forming a super via 400 at the same time, the super via 400 passes through the dielectric barrier layer 210 and the second dielectric layer 200, and connects the third metal interconnect structure 320 and the first metal interconnect structure 110.

[0051] See also Figure 16 In one embodiment, the specific process of step S5 is as follows: a third patterned mask layer 310 is formed on the third dielectric layer 300, wherein the third patterned mask layer 310 has a third opening 311 that exposes the third dielectric layer 300. The third patterned mask layer 310 in this step can be a patterned photoresist layer, which is formed by processes such as spin coating of photoresist, exposure, and development. The third opening 311 is used to define the position of the subsequently formed super via 400. Therefore, the third opening 311 is aligned with the filling layer 213 (the filling layer at the middle position) covered by the second patterned mask layer 230.

[0052] The second metal interconnect structure 240 and the third metal interconnect structure 320 are electrically connected using a conventional via process. In the present application, during the formation of the super via 400, a conventional via can be simultaneously formed, referred to herein as the first via 500. At this point, the third patterned mask layer 310 also has a fourth opening 312 that exposes the third dielectric layer 300. The fourth opening 312 is used to define the location of the first via 500.

[0053] See also Figure 17 Using the third patterned mask layer 310 as a mask, the third dielectric layer 300 and the second etch stop layer 250 are sequentially etched to form a first via trench 510 at a location corresponding to the fourth opening 312. A conductive material is then filled into the first via trench 510 to form the first via 500, thereby forming the second metal interconnect structure 240 and the third metal interconnect structure 320. The filling layer 213, the second dielectric layer 200, and the first etch stop layer 113 are further etched downward at a location corresponding to the third opening 311 until the top of the first metal interconnect structure 110 is exposed, forming a via trench, referred to as a second via trench 410. The second via trench 410 can be understood as the initial morphology for the subsequent formation of the super via 400. During this etching process, the dielectric barrier layer 210 is more difficult to etch than the filling layer 213 (low-k dielectric material) and the second dielectric layer 200. Even if the etching process deviates, if the dielectric barrier layer 210 blocks the etching process, the etching direction will be deflected to etch the easier-to-etch filling layer 213, thereby correcting the aforementioned etching deviation. This step can be performed using wet etching, dry etching, or a combination of the two methods.

[0054] See also Figure 18 The third dielectric layer 300 between the first via trench 510 and the second via trench 410 is then removed to form a third metal interconnect trench 321 communicating with the first via trench 510 and the second via trench 410. This process can be performed according to conventional techniques in the art. For example, after the first via trench 510 and the second via trench 410 are formed, the third patterned mask layer 310 is removed. This removal can be performed by ashing or stripping. A fourth patterned mask layer (not shown) is then formed on the third dielectric layer 300. The openings in the fourth patterned mask layer correspond to the locations of the third metal interconnect structures 320. The fourth patterned mask layer can be a patterned photoresist layer. The formation process is similar to that described above for the third patterned mask layer 310. Using the fourth patterned mask layer as a mask, the third dielectric layer 300 is then etched away to form the third metal interconnect trench 321 communicating with the first via trench 510 and the second via trench 410. The fourth patterned mask layer is then removed by ashing or stripping.

[0055] See also Figure 19A third diffusion barrier layer 322 is formed on the inner walls of the third metal interconnect trench 321, the first via trench 510, and the second via trench 410. The third diffusion barrier layer 322 is used to prevent the conductive material within the trench from diffusing into the surrounding dielectric layer. The material of the third diffusion barrier layer 322 may be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or any combination thereof. In this embodiment, the material of the third diffusion barrier layer 322 is TaN. The third diffusion barrier layer 322 may be formed by a deposition process such as PVD, CVD, or ALD. In one embodiment, after the third diffusion barrier layer 322 is formed, a seed layer (not shown) is also formed thereon. The seed layer facilitates the subsequent ECP process and ensures good adhesion between the interconnect metal structure and the underlying structure.

[0056] Conductive material is filled into the third diffusion barrier layer 322. The conductive material in the third metal interconnect trench 321 forms the third metal interconnect structure 320. The conductive material in the first via trench 510 forms the first via 500 for connecting the third metal interconnect structure 320 and the second metal interconnect structure 240. The conductive material in the second via trench 410 forms the super via 400 for cross-layer connection between the third metal interconnect structure 320 and the first metal interconnect structure 110. It should be noted that during the etching process, due to the obstruction of the dielectric barrier layer 210, the second via trench 410 forms a step on the dielectric barrier layer 210. When the conductive material is filled, this step is also filled. Therefore, the super via 400 forms a step structure on the upper surface of one side of the dielectric barrier layer 210. The position of this step structure is determined by the offset direction during the etching process. The conductive material in this step can be a material with good conductivity, such as copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co). In this step, the conductive material is filled using an ECP process. During this process, a certain thickness of conductive material will also be formed on the surface of the third dielectric layer 300. Therefore, the conductive material needs to be planarized, such as by chemical mechanical polishing (CMP), to remove the conductive material on the surface of the third dielectric layer 300.

[0057] In some embodiments, after step S5, a third etch stop layer 330 is formed on top of the third dielectric layer 300 and the third metal interconnect structure 320 to facilitate subsequent steps. The formation process of the third etch stop layer 330 is similar to that of the first etch stop layer 113 and the second etch stop layer 250.

[0058] It should be noted that the first metal interconnect structure 110 and the second metal interconnect structure 240 can be connected or not according to actual production needs. The connection method adopts a conventional single-layer through hole. The formation method refers to the method of the first through hole 500 and will not be repeated here.

[0059] See also Figure 19 The present invention also provides a super through-hole interconnect structure, which is formed on a semiconductor substrate. The semiconductor substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, a silicon-on-insulator substrate, or other semiconductor substrates well known in the art, and semiconductor devices such as transistors can be formed in the semiconductor substrate.

[0060] The super via interconnect structure of the present invention includes a first dielectric layer 100, a second dielectric layer 200, a dielectric barrier layer 210, a third dielectric layer 300, and a super via 400. The first dielectric layer 100, the second dielectric layer 200, the dielectric barrier layer 210, and the third dielectric layer 300 are sequentially formed on a semiconductor substrate (not shown). A first metal interconnect structure 110 is provided within the first dielectric layer 100. A second metal interconnect structure 240 is provided within the second dielectric layer 200 and the dielectric barrier layer 210. The top of the second metal interconnect structure 240 is lower than the top of the dielectric barrier layer 210, and the etching rate of the dielectric barrier layer 210 is lower than that of the second dielectric layer 200. A third metal interconnect structure 320 is provided within the third dielectric layer 300. Super via 400 penetrates the dielectric barrier layer 210 and the second dielectric layer 200, electrically connecting the first metal interconnect structure 110 with the third metal interconnect structure 320.

[0061] The first dielectric layer 100, the second dielectric layer 200, and the third dielectric layer 300 are made of low-k materials, and further, can be dielectric materials with k < 3. Specifically, the low-k material can be SiCOH, porous SiCOH, or SiOC. In one embodiment, the first dielectric layer 100, the second dielectric layer 200, and the third dielectric layer 300 are all made of SiCOH. The dielectric barrier layer 210 is made of a material with a lower etch rate than the second dielectric layer 200. During subsequent etching processes, the dielectric barrier layer 210 can prevent etching offset. In some embodiments, the dielectric barrier layer 210 can be made of one or more of TEOS, SiON, and SiCN. That is, the dielectric barrier layer 210 can be made of a single material or a combination of two or more materials. Furthermore, the thickness of the dielectric barrier layer 210 is between 5 and 20 nm, and can be 5 nm, 10 nm, 15 nm, or 20 nm, for example. A thickness that is too thick can increase parasitic capacitance and affect signal transmission, while a thin thickness can cause complete etching, failing to provide a barrier effect.

[0062] In some embodiments, a first etch-stop layer 113 is further disposed between the first dielectric layer 100 and the second dielectric layer 200, a second etch-stop layer 250 is further disposed between the dielectric barrier layer 210 and the third dielectric layer 300, and a third etch-stop layer 330 is further disposed on the surface of the third dielectric layer 300. The materials of the first etch-stop layer 113, the second etch-stop layer 250, and the third etch-stop layer 330 may be one or more of aluminum nitride (AlN), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0063] In one embodiment, the first metal interconnect structure 110 is located within the first dielectric layer 100, and the top of the first metal interconnect structure 110 is flush with the top of the first dielectric layer 100, that is, the top of the first metal interconnect structure 110 is not covered by the first dielectric layer 100, so that the subsequently formed via can be electrically connected to the first metal interconnect structure 110. In addition, the first metal interconnect structure 110 may also be electrically connected to other components (such as transistors) below, but for the sake of simplicity, these other components are not depicted here. The second metal interconnect structure 240 is located within the second dielectric layer 200 and the dielectric barrier layer 210, and the top of the second metal interconnect structure 240 is lower than the top of the dielectric barrier layer 210. This can increase the distance between the second metal interconnect structure 240 and the subsequently formed super via 400, reducing the risk of bridging. In one embodiment, the height difference between the second metal interconnect structure 240 and the dielectric barrier layer 210 is less than or equal to half the thickness of the dielectric barrier layer 210. Furthermore, the first metal interconnect structure 110 and the second metal interconnect structure 240 can be electrically connected via a conventional via structure (not shown) based on actual production needs. A third metal interconnect structure 320 is located within the third dielectric layer 300, with the top of the third metal interconnect structure 320 flush with the top of the third dielectric layer 300. The third metal interconnect structure 320 is electrically connected to the first metal interconnect structure 110 via a super via 400. Super via 400 is fabricated using the aforementioned manufacturing method of the present invention. Due to the obstruction of dielectric barrier layer 210, super via 400 forms a step structure on one side of dielectric barrier layer 210. The specific location of the step structure is not limited and is determined by the offset direction during the etching of super via 400. Furthermore, the third metal interconnect structure 320 is electrically connected to the second metal interconnect structure 240 via a first via 500, which is a conventional single-layer via.

[0064] In some embodiments, the conductive materials used in the first metal interconnect structure 110, the second metal interconnect structure 240, the third metal interconnect structure 320, the super via 400, and the first via 500 can each be independently selected from materials with good conductivity, such as copper (Cu), aluminum (Al), tungsten (W), and cobalt (Co), without limitation. In the present invention, the first metal interconnect structure 110 can be understood as a metal wiring structure located at a lower layer, the second metal interconnect structure 240 can be understood as a metal wiring structure located at an intermediate layer, and the third metal interconnect structure 320 can be understood as a metal wiring structure located at a higher layer.

[0065] The method for manufacturing a super via interconnect structure provided by the present invention forms a dielectric barrier layer between the second dielectric layer and the third dielectric layer, and the etching rate of the dielectric barrier layer is lower than that of the second dielectric layer. During the etching process of the super via, the dielectric barrier layer can prevent etching offset, facilitating self-alignment of the super via, while effectively improving bridging issues and / or TDDB failure between the metal interconnect structure within the dielectric layer where the dielectric barrier layer is located and the super via. In addition, when manufacturing the second metal interconnect structure, its conductive material is partially etched so that the top of the second metal interconnect structure is lower than the top of the dielectric barrier layer, thereby increasing the distance between the second metal interconnect structure and the super via, further improving bridging and / or TDDB failure issues. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and practical significance.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a super through-hole interconnect structure, characterized in that: The following steps are involved: forming a first metal interconnect structure in the first dielectric layer; forming a second dielectric layer and a dielectric barrier layer in sequence on the first dielectric layer, wherein the etching rate of the dielectric barrier layer is lower than the etching rate of the second dielectric layer; forming a second metal interconnect structure in the dielectric barrier layer and the second dielectric layer, wherein a top of the second metal interconnect structure is lower than a top of the dielectric barrier layer; forming a third dielectric layer on the dielectric barrier layer; A third metal interconnect structure is formed in the third dielectric layer, and a super via is formed simultaneously penetrating the dielectric barrier layer and the second dielectric layer, wherein the super via electrically connects the third metal interconnect structure with the first metal interconnect structure.

2. The method for manufacturing a super via interconnect structure according to claim 1, wherein: forming a second metal interconnect structure in the dielectric barrier layer and the second dielectric layer, comprising: forming a second metal interconnection trench on the dielectric barrier layer and the second dielectric layer; filling the second metal interconnect trench with a conductive material; A portion of the conductive material in the second metal interconnection trench is removed by etching, so that a top of the conductive material is lower than a top of the dielectric barrier layer, thereby forming a second metal interconnection structure.

3. The method for manufacturing a super via interconnect structure according to claim 2, wherein: In the step of etching away part of the conductive material in the second metal interconnect trench, the conductive material is removed to a thickness such that the height difference between the top of the second metal interconnect structure and the top of the dielectric barrier layer is less than or equal to half the thickness of the dielectric barrier layer.

4. The method for manufacturing a super via interconnect structure according to claim 2, wherein: Before forming a second metal interconnection trench on the dielectric barrier layer and the second dielectric layer, the method includes: forming a first patterned mask layer on the dielectric barrier layer, wherein the first patterned mask layer has a plurality of first openings exposing the dielectric barrier layer, the first openings corresponding to positions of the second metal interconnect trenches and super vias to be formed subsequently; Using the first patterned mask layer as a mask, etching and removing the dielectric barrier layer exposed in the first opening to form a plurality of trenches; removing the first patterned mask layer, and forming a low dielectric constant material layer in the plurality of trenches and on the dielectric barrier layer on both sides of the trenches; planarizing the low-k material layer, removing the low-k material layer on the dielectric barrier layer, and forming a filling layer with the low-k material remaining in the trench; forming a second patterned mask layer on the dielectric barrier layer, wherein the second patterned mask layer has a plurality of second openings exposing the filling layer, and the filling layer corresponding to the position of the super via is covered by the second patterned mask layer; The second patterned mask layer is used as a mask to etch and remove the filling layer and a portion of the second dielectric layer exposed in the second opening to form a second metal interconnection trench.

5. The method for manufacturing a super via interconnect structure according to claim 1, wherein: The material of the dielectric barrier layer includes one or more of TEOS, SiON, and SiCN; and / or the thickness of the formed dielectric barrier layer is 5-20 nm.

6. The method for manufacturing a super via interconnect structure according to claim 2, wherein: Before filling the second metal interconnect trench with a conductive material, the method further includes: forming a diffusion barrier layer on an inner wall of the second metal interconnect trench; and / or, After forming the second metal interconnect structure, the method further includes: forming a second etch stop layer on top of the dielectric barrier layer and the second metal interconnect structure.

7. The method for manufacturing a super via interconnect structure according to claim 4, wherein: Forming a third metal interconnect structure in the third dielectric layer and simultaneously forming a super via penetrating the dielectric barrier layer and the second dielectric layer, comprising: forming a third patterned mask layer on the third dielectric layer, wherein the third patterned mask layer has a third opening exposing the third dielectric layer, and an area of ​​the third opening at least includes the filling layer covered by the second patterned mask layer; Using the third patterned mask layer as a mask, etching the third dielectric layer, the filling layer, and the second dielectric layer until the first metal interconnect structure is exposed to form a through-hole trench, and etching the periphery of the through-hole trench in the third dielectric layer to form a third metal interconnect trench connected to the through-hole trench; forming a diffusion barrier layer on inner walls of the third metal interconnect trench and the through-hole trench; A conductive material is filled on the diffusion barrier layer, and a third metal interconnection structure and a super via are formed at the same time.

8. A super through-hole interconnect structure, characterized in that: include: a first dielectric layer having a first metal interconnection structure disposed therein; a second dielectric layer, disposed on the first dielectric layer, wherein a second metal interconnection structure is disposed in the second dielectric layer; a dielectric barrier layer disposed on the second dielectric layer, wherein a top of the second metal interconnect structure is lower than a top of the dielectric barrier layer, and an etching rate of the dielectric barrier layer is lower than an etching rate of the second dielectric layer; a third dielectric layer, disposed on the dielectric barrier layer, and a third metal interconnection structure is disposed in the third dielectric layer; A super via penetrates the dielectric barrier layer and the second dielectric layer and electrically connects the first metal interconnection structure with the third metal interconnection structure.

9. The super via interconnect structure according to claim 8, wherein: A height difference between a top of the second metal interconnect structure and a top of the dielectric barrier layer is less than or equal to half a thickness of the dielectric barrier layer.

10. The super via interconnect structure according to claim 8, wherein: The material of the dielectric barrier layer includes one or more of TEOS, SiON, and SiCN; and / or the thickness of the dielectric barrier layer is 5-20 nm.

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