Common mode circuit and its biasing method

Abstract

The present application belongs to the technical field of common mode circuit, and particularly relates to a common mode circuit and a biasing method thereof. When a signal link is not formally working, a common mode establishing stage is started, and a resistance selection signal is set to low level. After the resistance selection signal is set to low level, the adjustable resistance RT is switched to a small resistance through inverter control. After being switched to the small resistance, the PGA input common mode voltage is waited to be established to a predetermined value. After the common mode voltage is established, a signal transmission stage is started, and the resistance selection signal is set to high level. After the resistance selection signal is set to high level, the adjustable resistance RT is switched to a large resistance through inverter control. After being switched to the large resistance, signal transmission is performed. The value of the adjustable resistance RT is dynamically adjusted in different stages of the signal link. A small resistance value is used in the common mode establishing stage to accelerate the voltage establishing process, and the adjustable resistance RT is switched to a large resistance value in the signal transmission stage to improve SNR.

Description

Technical Field

[0001] This invention belongs to the field of common-mode circuit technology, specifically relating to a common-mode circuit and its biasing method. Background Technology

[0002] The signal link is structured as follows: Figure 1 As shown, the signal travels from outside the chip through a DC blocking capacitor to the chip. Once inside the chip, the signal passes through a filter to remove interference and noise. Next, the signal is amplified by a PGA, typically to the full swing input of the ADC to achieve the maximum signal-to-noise ratio (SNR). Finally, after being sampled by the ADC, the signal enters the DSP module for corresponding calculations and processing.

[0003] To ensure signal integrity, PGA input signals typically require a fixed common-mode voltage. Since the DC component is filtered out by an off-chip DC blocking capacitor, an additional bias circuit is needed at the PGA input to provide the required input common-mode voltage.

[0004] like Figure 2 As shown, the input common-mode voltage of the PGA is currently connected to point A of the PGA input via the output of the buffer. The impedance at point A is the parallel value of the output impedance of the buffer and the input impedance of the PGA. Although the input impedance of the PGA is large, considering that the output impedance of the buffer is only 20~30 ohms, the impedance at point A is approximately equal to the output impedance of the buffer, and the value is small. The low impedance at point A will lead to a reduction in the signal amplitude transmitted to the PGA input. In addition, since the PGA has a fixed equivalent input noise, this will further reduce the SNR.

[0005] Based on the above analysis, the bias circuit typically adds a bias resistor RT between the buffer output and the PGA input. This resistor increases the impedance looking from point A into the buffer, thereby improving the SNR. Simultaneously, the presence of this resistor reduces the current drawn from the buffer output by voltage fluctuations at point A, decreasing the size of the push-pull output of the buffer and saving chip area.

[0006] However, in some applications that have high requirements for the common-mode settling time of the PGA input, the value of the bias resistor RT cannot be too large, because RT is proportional to the settling time. The higher the value of RT, the longer the system waits for the common-mode to set, which limits the range of resistor values.

[0007] Existing common-mode bias circuits typically select the RT value based on a trade-off between application requirements. If the application demands a high SNR, a larger RT resistor is chosen; if the application prioritizes high-speed signal transmission and requires a shorter settling time, a smaller RT resistor is selected. However, in applications that simultaneously require both high SNR and fast settling time, a fixed resistor value is insufficient to meet these needs. Summary of the Invention

[0008] The purpose of this invention is to provide a common-mode circuit and its biasing method that shortens the common-mode voltage settling time while maintaining a high SNR, thereby solving the problems mentioned in the background art.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: a common-mode circuit biasing method, comprising the following steps:

[0010] Step 1: Before the signal link is officially working, start the common-mode setup phase by setting the resistor selection signal to low level;

[0011] Step 2: After setting the resistor selection signal to low level, the adjustable resistor RT is switched to a smaller resistance by controlling the inverter.

[0012] Step 3: After switching to a small resistor, wait for the PGA input common-mode voltage to build up to the predetermined value;

[0013] Step 4: After the common-mode voltage is established, start the signal transmission phase and set the resistor selection signal to high level;

[0014] Step 5: After setting the resistor selection signal to a high level, the inverter controls the adjustable resistor RT to switch to a larger resistance. After switching to a larger resistance, signal transmission is performed.

[0015] Preferably, the adjustable resistor RT includes MOS transistors MR1, MR2, MR3, MR4, MR5, and MR6, as well as a small resistor Rr1 and a large resistor Rr2.

[0016] Preferably, in step two, when the resistor selection signal is low, inverter one outputs a high level ENR1 and inverter two outputs a low level ENR2. ENR1 turns on MR1, MR2, and MR6, and ENR2 turns off MR3, MR4, and MR5, thereby switching RT to the small resistor Rr1.

[0017] Preferably, in step five, when the resistor selection signal is high, inverter one outputs low level ENR1 and inverter two outputs high level ENR2. ENR1 turns off MR1, MR2, and MR6, and ENR2 turns on MR3, MR4, and MR5, thereby switching RT to the large resistor Rr2.

[0018] Preferably, the predetermined value is 99%Vref, where Vref is the reference voltage.

[0019] Preferably, the waiting time for the PGA input common-mode voltage to establish is calculated based on the following formula:

[0020] ;in, Let A be the voltage at point A. The reference voltage is t, and the time is t. This is the resistance value. Let A be the total capacitance to ground.

[0021] Preferably, during the signal transmission phase, the current extraction at point A is calculated based on the following formula:

[0022] Where I is the current, Let A be the voltage at point A. For reference voltage, This represents the resistance value.

[0023] On the other hand, the present invention proposes a common-mode circuit, including: an external DC blocking capacitor C1, an on-chip filter, a PGA, an ADC, a DSP module, a buffer, and an adjustable resistor RT;

[0024] The filter's output is connected to the PGA's input and the MINUS terminal of the adjustable resistor RT at point A. The PLUS terminal of the adjustable resistor RT is connected to the buffer's output. The PGA's output is connected to the ADC's input, and the ADC's output is connected to the DSP module.

[0025] Preferably, the adjustable resistor RT includes:

[0026] The resistor selection signal port is connected to the input terminal of inverter one, the output terminal of inverter one is connected to the input terminal of inverter two and the gates of MR1, MR2, and MR6, and the output terminal of inverter two is connected to the gates of MR3, MR4, and MR5.

[0027] The PLUS port is connected to the drain ports of MR1, MR2, MR4, and MR5.

[0028] The source terminal of MR1 is connected to the MINUS port through a small resistor Rr1, and the source terminal of MR4 is connected to the MINUS port through a large resistor Rr2.

[0029] The b-end of MR2, MR3, MR5, and MR6 is connected to GND;

[0030] The b end of MR1 is connected to the source end of MR2 and the drain end of MR3;

[0031] The b end of MR4 is connected to the source end of MR5 and the drain end of MR6.

[0032] The source ends of MR3 and MR6 are connected to GND.

[0033] Preferably, the resistor selection signal controls the conduction state of the inverter and the MOSFET.

[0034] Technical effects and advantages of the present invention: The common-mode circuit and its biasing method proposed in this invention have the following advantages compared with the prior art:

[0035] This invention dynamically adjusts the value of an adjustable resistor RT at different stages of the signal link—using a small resistance value to accelerate voltage buildup during the common-mode establishment phase, and switching to a large resistance value during the signal transmission phase to improve signal-to-noise ratio (SNR). This not only effectively resolves the contradiction between high SNR and fast setup time in traditional solutions, but also reduces the current drawn from the buffer, lowers the requirements for the buffer push-pull output, and thus saves chip area and cost. Furthermore, because the common-mode voltage can be established more quickly, the overall system latency is shortened, and power consumption is reduced accordingly. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the signal link;

[0037] Figure 2 This is a schematic diagram of a signal link that includes common-mode bias.

[0038] Figure 3 The circuit diagram is for an adjustable resistor;

[0039] Figure 4 This is the timing diagram for the adjustable resistor switching. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The specific embodiments described herein are merely used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] In this embodiment, a common-mode circuit with an adjustable resistor design is proposed. This circuit switches the resistor at different stages of the measurement, abandoning the traditional single bias resistor method. This design satisfies the requirement for rapid common-mode setup at the PGA input while ensuring a high signal-to-noise ratio (SNR) during signal transmission. Furthermore, this circuit effectively reduces the overall measurement system's operating time, decreases power consumption, and significantly improves measurement accuracy and precision.

[0042] Specifically, the input common-mode voltage of the PGA can be divided into two stages during operation: one is the common-mode establishment stage, and the other is the stage after the common-mode is established, when the signal is officially transmitted.

[0043] The formula for calculating the input noise of a PGA is as follows: ;in It's noise from the input signal itself. It is the equivalent input noise of the PGA itself, and the sum of the two is the noise at the PGA input.

[0044] The formula for calculating the input signal-to-noise ratio of a PGA is as follows: ;in It is the input signal noise of the PGA.

[0045] If the impedance seen from point A towards the buffer decreases, it will cause the impedance at point A to decrease, thus making... , Decrease proportionally. Under fixed conditions, , A proportional reduction will lead to a decrease in SNR.

[0046] In this embodiment, the method to improve SNR is to switch RT to a large resistance during the signal transmission phase, thereby increasing the impedance to ground at point A and thus improving SNR.

[0047] During signal transmission, voltage fluctuations at point A will draw current from the output of the buffer, and the current satisfies the following formula: According to the formula, when RT increases, the current I drawn from the buffer will decrease, thereby reducing the drive requirements for the push-pull output of the buffer, thus reducing the area and saving costs.

[0048] The equation for establishing the common-mode signal Vp of the PGA can be obtained from the following formula: ;

[0049] The time required for the common-mode voltage to build up to 99% Vref is 5RT*C, where the build-up time is proportional to RT, and C is the total capacitance to ground at point A. An excessively long build-up time will increase the system's latency.

[0050] In this embodiment, by switching the adjustable resistor RT to a smaller resistor during the common-mode voltage setup phase, the system's waiting time is shortened and the overall chip's power consumption is reduced.

[0051] The bias circuit architecture in this embodiment is as follows: Figure 2 As shown, the external DC blocking capacitor C1 is connected to the input terminal of the on-chip filter. The output terminal of the filter is connected to the input terminal of the PGA and the MINUS terminal of the adjustable resistor RT at point A. The PLUS terminal of the adjustable resistor RT is connected to the push-pull output terminal of the buffer. The output terminal of the PGA is connected to the input terminal of the ADC, and the output terminal of the ADC is connected to the DSP module.

[0052] The circuit architecture of the adjustable resistor RT is as follows: Figure 3 As shown, the resistor selection signal port is internally connected to inverter one. The output of inverter one is connected to the input of inverter two and the gates of MR1, MR2, and MR6. The output of inverter two is connected to the gates of MR3, MR4, and MR5. The PLUS port is internally connected to the drain terminals of MR1, MR2, MR4, and MR5. The source terminal of MR1 is connected to the MINUS port through a small resistor Rr1, and the source terminal of MR4 is connected to the MINUS port through a large resistor Rr2. The base terminals (b) of MR2, MR3, MR5, and MR6 are connected to GND. The base terminal (b) of MR1 is connected to the source terminal of MR2 and the drain terminal of MR3. The base terminal (b) of MR4 is connected to the source terminal of MR5 and the drain terminal of MR6. The source terminals of MR3 and MR6 are connected to GND.

[0053] The working process of the bias circuit is as follows: Figure 4 As shown. Before the signal arrives, the input common-mode voltage of the PGA needs to be established in advance; this is the common-mode establishment phase. This process is executed by the RT, as... Figure 3 As shown, when RSE_SEL is low, inverter one inverts it to a high level ENR1, and inverter two inverts ENR1 to a low level ENR2. When ENR1 is high, NMOS transistors MR1, MR2, and MR6 are turned on. MR1's turn-on switches RT to a small resistance Rr1. MR2's turn-on connects the base (b) of MR1 to the PLUS terminal, increasing the base potential, weakening the substrate bias effect, and reducing MR1's on-resistance. MR6's turn-on connects MR4's potential to GND, enhancing MR4's substrate bias effect and increasing its turn-off resistance. When ENR2 is low, MR3, MR4, and MR5 are turned off, rendering the large resistance Rr2 ineffective.

[0054] After the PGA input common-mode voltage is established, the bias circuit switches to the signal transmission stage. RSE_SEL switches to a high level, inverter one inverts it to a low level ENR1, and inverter two inverts ENR1 to a high level ENR2. When ENR1 is low, MR1, MR2, and MR6 are turned off, so the small resistance of Rr1 is ineffective. When ENR2 is high, MR3, MR4, and MR5 are turned on. The turn on of MR4 causes RT to switch to the large resistance Rr2. The turn on of MR5 connects the b terminal of MR4 to the PLUS terminal, increasing the b terminal potential, weakening the substrate bias effect, and reducing the on-resistance of MR4. The turn on of MR3 connects the b terminal potential of MR1 to GND, enhancing the substrate bias effect of MR1 and increasing the turn-off resistance of MR4.

[0055] For example, the above-described common-mode circuit biasing method includes the following steps:

[0056] Step 1: Before the signal link is officially working, start the common-mode setup phase by setting the resistor selection signal to low level;

[0057] Step 2: After setting the resistor selection signal to low level, the inverter controls the adjustable resistor RT to switch to a small resistance. The adjustable resistor RT includes MOSFETs MR1, MR2, MR3, MR4, MR5, and MR6, as well as a small resistor Rr1 and a large resistor Rr2. The resistor selection signal controls the conduction state of the inverter and the MOSFETs.

[0058] Furthermore, when the resistor selection signal is low, inverter one outputs a high level ENR1, and inverter two outputs a low level ENR2. ENR1 turns on MR1, MR2, and MR6, while ENR2 turns off MR3, MR4, and MR5, thus switching RT to the small resistor Rr1.

[0059] Step 3: After switching to a small resistor, wait for the PGA input common-mode voltage to build up to a predetermined value; the predetermined value is 99%Vref, where Vref is the reference voltage.

[0060] The time to wait for the PGA input common-mode voltage to establish is calculated based on the following formula: ;in, Let A be the voltage at point A. The reference voltage is t, and the time is t. This is the resistance value. Let A be the total capacitance to ground.

[0061] Step 4: After the common-mode voltage is established, start the signal transmission phase and set the resistor selection signal to high level;

[0062] Step 5: After setting the resistor selection signal to a high level, the inverter controls the adjustable resistor RT to switch to a larger resistance. After switching to a larger resistance, signal transmission is performed.

[0063] Furthermore, when the resistor selection signal is high, inverter one outputs a low level ENR1, and inverter two outputs a high level ENR2. ENR1 turns off MR1, MR2, and MR6, while ENR2 turns on MR3, MR4, and MR5, thus switching RT to the large resistor Rr2.

[0064] During the signal transmission phase, the current extraction at point A is calculated based on the following formula: Where I is the current, Let A be the voltage at point A. For reference voltage, This represents the resistance value.

[0065] In summary, this invention dynamically adjusts the value of the adjustable resistor RT at different stages of the signal link—using a small resistance value to accelerate voltage establishment during the common-mode establishment stage, and switching to a large resistance value during the signal transmission stage to improve SNR. This not only effectively resolves the contradiction between high SNR and fast establishment time in traditional solutions, but also reduces the current drawn from the buffer, lowers the requirements for buffer push-pull output, and thus saves chip area and cost. Furthermore, because the common-mode voltage can establish faster, the overall system latency is shortened, and power consumption is reduced accordingly.

[0066] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A biasing method for a common-mode circuit, characterized in that, Includes the following steps: Step 1: Before the signal link is officially working, start the common-mode setup phase by setting the resistor selection signal to low level; Step 2: After setting the resistor selection signal to low level, the adjustable resistor RT is switched to a smaller resistance by controlling the inverter. Step 3: After switching to a small resistor, wait for the PGA input common-mode voltage to build up to the predetermined value; Step 4: After the common-mode voltage is established, start the signal transmission phase and set the resistor selection signal to high level; Step 5: After setting the resistor selection signal to a high level, the inverter controls the adjustable resistor RT to switch to a larger resistance. After switching to a larger resistance, signal transmission is performed.

2. The biasing method for a common-mode circuit according to claim 1, characterized in that, The adjustable resistor RT includes MOSFETs MR1, MR2, MR3, MR4, MR5, and MR6, as well as a small resistor Rr1 and a large resistor Rr2.

3. The biasing method for a common-mode circuit according to claim 2, characterized in that, In step two, when the resistor selection signal is low, inverter one outputs a high level ENR1 and inverter two outputs a low level ENR2. ENR1 turns on MR1, MR2, and MR6, and ENR2 turns off MR3, MR4, and MR5, thus switching RT to the small resistor Rr1.

4. The biasing method for a common-mode circuit according to claim 2, characterized in that, In step five, when the resistor selection signal is high, inverter one outputs low level ENR1 and inverter two outputs high level ENR2. ENR1 turns off MR1, MR2, and MR6, and ENR2 turns on MR3, MR4, and MR5, thereby switching RT to the large resistor Rr2.

5. The biasing method for a common-mode circuit according to claim 1, characterized in that, The predetermined value is 99%Vref, where Vref is the reference voltage.

6. The biasing method for a common-mode circuit according to claim 5, characterized in that, The waiting time for the PGA input common-mode voltage to establish is calculated based on the following formula: ;in, Let A be the voltage at point A. The reference voltage is t, and the time is t. This is the resistance value. Let A be the total capacitance to ground.

7. The biasing method for a common-mode circuit according to claim 1, characterized in that, During the signal transmission phase, the current extraction at point A is calculated based on the following formula: Where I is the current, Let A be the voltage at point A. For reference voltage, This represents the resistance value.

8. A common-mode circuit for implementing the biasing method according to any one of claims 1-7, characterized in that, include: External DC blocking capacitor C1, on-chip filter, PGA, ADC, DSP module, buffer, and adjustable resistor RT; The filter's output is connected to the PGA's input and the MINUS terminal of the adjustable resistor RT at point A. The PLUS terminal of the adjustable resistor RT is connected to the buffer's output. The PGA's output is connected to the ADC's input, and the ADC's output is connected to the DSP module.

9. The common-mode circuit according to claim 8, characterized in that, The adjustable resistor RT includes: The resistor selection signal port is connected to the input terminal of inverter one, the output terminal of inverter one is connected to the input terminal of inverter two and the gates of MR1, MR2, and MR6, and the output terminal of inverter two is connected to the gates of MR3, MR4, and MR5. The PLUS port is connected to the drain ports of MR1, MR2, MR4, and MR5. The source terminal of MR1 is connected to the MINUS port through a small resistor Rr1, and the source terminal of MR4 is connected to the MINUS port through a large resistor Rr2. The b-end of MR2, MR3, MR5, and MR6 is connected to GND; The b end of MR1 is connected to the source end of MR2 and the drain end of MR3; The b end of MR4 is connected to the source end of MR5 and the drain end of MR6. The source ends of MR3 and MR6 are connected to GND.

10. The common-mode circuit according to claim 9, characterized in that, The resistor selection signal controls the conduction state of the inverter and the MOSFET.

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