Signal amplification circuit, chip, and electronic device

Abstract

The invention discloses a signal amplification circuit, a chip and electronic equipment, and relates to the technical field of display driving. The signal amplification circuit comprises a slew rate enhancement circuit and an operational amplifier, and the slew rate enhancement circuit is connected with the operational amplifier; and the slew rate enhancing circuit is used for detecting a voltage difference between an input signal and an output signal of the operational amplifier and inputting a reference current to the operational amplifier under the condition that the voltage difference is greater than a reference threshold value, the reference current is used for increasing the slew rate of the operational amplifier, and the reference threshold value is determined based on a current value of the reference current. Thus, by inputting the reference current to the operational amplifier, the slew rate of the operational amplifier can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display driving technology, and in particular to a signal amplification circuit, a chip, and an electronic device. Background Art

[0002] For displays connected to display drivers, the visual performance of the display is affected by the operational amplifiers (OPA) within the display driver. The slew rate of an OPA refers to the rate of change of the voltage of the OPA's output signal. The greater the slew rate of an OPA, the faster the voltage of the OPA's output signal changes—in other words, the faster the output signal's voltage changes to match the input signal's voltage.

[0003] Therefore, how to increase the slew rate of the operational amplifier to improve the visual performance of the display is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a signal amplification circuit, chip, and electronic device for improving the slew rate of an operational amplifier. The technical solution includes the following contents.

[0005] On the one hand, a signal amplification circuit is provided, which includes a slew rate enhancement circuit and an operational amplifier, wherein the slew rate enhancement circuit is connected to the operational amplifier; the slew rate enhancement circuit is used to detect the voltage difference between the input signal and the output signal of the operational amplifier; the slew rate enhancement circuit is also used to input a reference current into the operational amplifier when the voltage difference is greater than a reference threshold, the reference current is used to increase the slew rate of the operational amplifier, and the reference threshold is determined based on the current value of the reference current.

[0006] In one possible implementation, the slew rate enhancement circuit includes: a voltage signal generating circuit and an analog switch, the voltage signal generating circuit being connected to the operational amplifier through the analog switch; the voltage signal generating circuit being used to obtain a control current and detect a voltage difference between an input signal and an output signal of the operational amplifier; the voltage signal generating circuit being further used to generate an analog voltage signal based on the control current and the voltage difference, wherein, when the voltage difference is greater than a reference threshold, the analog voltage signal is used to control the analog switch to conduct, so as to input a reference current into the operational amplifier.

[0007] In one possible implementation, the control current includes a first current, a second current, and a third current; the voltage signal generating circuit includes: a reference current mirror circuit and a voltage control element, the voltage control element being connected to the reference current mirror circuit and the analog switch, respectively; the reference current mirror circuit is used to obtain the first current and the second current, and detect the voltage difference between the input signal and the output signal of the operational amplifier; the reference current mirror circuit is also used to control the input voltage of the voltage control element based on the voltage difference, the first current, and the second current; the voltage control element is used to generate an analog voltage signal based on the input voltage of the voltage control element and the third current.

[0008] In one possible implementation, the slew rate enhancement circuit also includes at least one of a reference current source or a reference voltage source, at least one of the reference current source or the reference voltage source is connected to the voltage signal generating circuit, and at least one of the reference current source or the reference voltage source is used to provide a control current to the voltage signal generating circuit.

[0009] In one possible implementation, the direction of the control current is the direction of flowing into the voltage signal generating circuit, and the voltage signal generating circuit is used to perform an operation of generating an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is less than the voltage of the output signal.

[0010] In one possible implementation, the direction of the control current is the direction of flowing out of the voltage signal generating circuit, and the voltage signal generating circuit is used to perform an operation of generating an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is greater than the voltage of the output signal.

[0011] In a possible implementation, the signal amplifying circuit further includes a startup control circuit, and the slew rate enhancement circuit is connected to the startup control circuit; the startup control circuit is used to control turning on or off the slew rate enhancement circuit.

[0012] In a possible implementation, the operational amplifier is connected to the display panel via an output switch; and the startup control circuit is configured to activate the slew rate enhancement circuit after the output switch is turned on.

[0013] On the other hand, a chip is provided, which includes any one of the above-mentioned signal amplification circuits.

[0014] On the other hand, an electronic device is provided, which includes the above chip.

[0015] The technical solution provided by this application brings at least the following beneficial effects:

[0016] In the signal amplification circuit provided in an embodiment of the present application, a slew rate enhancement circuit can detect the voltage difference between the input signal and the output signal of the operational amplifier. When the detected voltage difference is greater than a reference threshold, a reference current is input into the operational amplifier to increase the slew rate of the operational amplifier. The reference threshold is determined based on the current value of the reference current. Thus, by inputting the reference current into the operational amplifier, the slew rate of the operational amplifier can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a schematic structural diagram of a signal amplification circuit provided in an embodiment of the present application;

[0019] Figure 2 1 is a schematic structural diagram of a slew rate enhancement circuit provided in an embodiment of the present application;

[0020] Figure 3 is a structural diagram of another slew rate enhancement circuit provided in an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a signal change provided by an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a voltage change provided in an embodiment of the present application;

[0023] Figure 6 This is a schematic diagram of a connection between a signal amplification circuit and a display panel provided by an embodiment of the present application;

[0024] Figure 7 is a schematic diagram of another signal change provided in an embodiment of the present application;

[0025] Figure 8 This is a flow chart of a signal amplification method provided in an embodiment of the present application;

[0026] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0027] Figure 10 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0029] It should be noted that the terms "first," "second," and the like in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] For high-quality displays, the display driver connected to the display plays a crucial role. The display driver includes an output buffer circuit, which in turn includes an operational amplifier. The greater the slew rate of the operational amplifier, the faster the voltage of the output signal of the operational amplifier changes to match the voltage of the input signal. Therefore, when the display needs to update its image, the greater the slew rate of the operational amplifier, the faster the display updates the image.

[0031] The speed at which a display displays a new image can represent the display's visual performance. Thus, the faster a display updates an image, the better the visual performance. With the increasing use of displays with high image refresh rates, an operational amplifier with a higher slew rate is needed.

[0032] An embodiment of the present application provides a signal amplification circuit. The signal amplification circuit can be applied to an output buffer circuit of a display driver. The display driver can be a source driver or a gate driver. Figure 1 is a structural diagram of a signal amplification circuit provided in an embodiment of the present application, such as Figure 1 As shown, the signal amplifying circuit includes: a slew rate enhancement circuit 10 and an operational amplifier 20 , and the slew rate enhancement circuit 10 is connected to the operational amplifier 20 .

[0033] like Figure 1 As shown, the operational amplifier 20 includes an input stage, an output stage, and a capacitor Cc. The input end of the input stage is used to receive the input signal Vin and the output signal Vout of the operational amplifier 20. The output end of the input stage is connected to the input end of the output stage. The capacitor Cc is connected to the input end and the output end of the output stage respectively. The output end of the output stage is used to output the output signal of the operational amplifier 20. The output end of the output stage is also connected to the input end of the input stage.

[0034] The input stage also receives a tail current Itail. In this case, the slew rate of the operational amplifier 20 can be obtained by dividing the tail current Itail by the capacitance of the capacitor Cc. Since the magnitude of the tail current Itail is limited by power and the gain-bandwidth product (GBP), and the capacitance of the capacitor Cc is limited by the phase margin, simply increasing the tail current Itail to adjust the slew rate results in high power consumption. Alternatively, simply adjusting the capacitance of the capacitor Cc to adjust the slew rate results in poor circuit stability. Therefore, a signal amplification circuit including a slew rate enhancement circuit 10 and an operational amplifier 20 is needed to achieve the purpose of increasing the slew rate by optimizing the circuit structure.

[0035] In the embodiment of the present application, the slew rate enhancement circuit 10 is used to detect the voltage difference between the input signal and the output signal of the operational amplifier 20; the slew rate enhancement circuit 10 is also used to input a reference current to the operational amplifier 20 when the voltage difference is greater than a reference threshold. The reference current is used to increase the slew rate of the operational amplifier. The reference threshold is determined based on the current value of the reference current. Figure 1 The current I_SR is shown in FIG.

[0036] In other words, the core principle of increasing the slew rate of operational amplifier 20 in the embodiments of the present application is to input a reference current into operational amplifier 20 during the transient response of operational amplifier 20, thereby increasing the slew rate by increasing the transient bias current. The transient response process of operational amplifier 20 is the process in which the voltage of the output signal of operational amplifier 20 changes to the voltage of the input signal. Since the input signal is determined by the image to be displayed on the display, the process of changing the voltage of the output signal to the voltage of the input signal can also be called a data conversion process.

[0037] Furthermore, in the embodiment of the present application, when the voltage difference between the input signal and the output signal is less than or equal to the reference threshold, the slew rate enhancement circuit 10 may stop inputting the reference current to the operational amplifier 20 .

[0038] Exemplarily, the reference threshold is determined based on the current value of the reference current and the component parameters of the slew rate enhancement circuit. For example, the reference threshold α is expressed as follows:

[0039]

[0040] Among them, I SR represents the current value of the reference current, and β represents the component parameters of the slew rate enhancement circuit 10.

[0041] In some embodiments, the slew rate enhancement circuit 10 includes a voltage signal generating circuit and an analog switch. The voltage signal generating circuit is connected to the operational amplifier 20 via the analog switch. The voltage signal generating circuit is used to obtain a control current and detect the voltage difference between the input signal and the output signal of the operational amplifier 20. The voltage signal generating circuit is further used to generate an analog voltage signal based on the voltage difference and the control current. When the voltage difference is greater than a reference threshold, the analog voltage signal is used to control the analog switch to conduct, thereby inputting a reference current into the operational amplifier 20.

[0042] By using a voltage signal generation circuit to generate an analog voltage signal based on the control current and the voltage difference between the input signal and the output signal, the on and off of the analog switch can be controlled. Thus, when the analog switch is on, the reference current can be input into the operational amplifier 20 to increase the slew rate of the operational amplifier 20. For example, when the voltage difference between the input signal and the output signal is less than or equal to a reference threshold, the analog voltage signal generated by the voltage signal generation circuit is used to control the analog switch to be off, thereby stopping the input of the reference current to the operational amplifier 20.

[0043] Because the on / off state of the analog switch is controlled by an analog voltage signal generated by a voltage signal generation circuit, and the analog voltage signal is generated based on the control current and the voltage difference between the input signal and the output signal, the analog voltage signal is an analog signal rather than a digital signal. Therefore, compared to methods that control the on / off state of the analog switch using digital signals, the stability of the on / off control of the analog switch in the embodiments of the present application is higher, thereby enhancing the reliability and stability of the slew rate of the operational amplifier 20.

[0044] Furthermore, since the slew rate of the operational amplifier 20 can be increased by inputting a reference current into the operational amplifier 20, the slew rate of the operational amplifier 20 can be controlled by controlling the magnitude of the input reference current.

[0045] In one possible implementation, the control current includes a first current, a second current, and a third current; the voltage signal generating circuit includes: a reference current mirror circuit and a voltage control element, the voltage control element being connected to the reference current mirror circuit and the analog switch, respectively; the reference current mirror circuit is used to obtain the first current and the second current, and detect the voltage difference between the input signal and the output signal of the operational amplifier 20; the reference current mirror circuit is also used to control the input voltage of the voltage control element based on this voltage difference, the first current, and the second current; the voltage control element is used to generate an analog voltage signal based on the input voltage of the voltage control element and the third current.

[0046] Exemplarily, the voltage-controlled element is a transistor, which can be referred to as a first transistor. In this case, the input voltage of the voltage-controlled element can be the gate voltage of the first transistor. Thus, the reference current mirror circuit can be used to control the gate voltage of the first transistor based on the voltage difference, the first current, and the second current. The first transistor is used to generate an analog voltage signal based on the gate voltage of the first transistor and the third current.

[0047] Exemplarily, the reference current mirror circuit includes: a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The connection relationship between the second transistor, the third transistor, the fourth transistor, and the fifth transistor is as follows:

[0048] The gate voltage of the second transistor is the voltage of the input signal of the operational amplifier 20. The source of the second transistor is used to obtain the first current. The drain of the second transistor is connected to the gates of the fourth and fifth transistors, respectively. The gate voltage of the third transistor is the voltage of the output signal of the operational amplifier 20. The source of the third transistor is used to obtain the first current. The drain of the third transistor is connected to the drain of the fifth transistor and the gate of the first transistor, respectively. The gate of the first transistor is also used to obtain the second current. The source of the fourth transistor is connected to a reference voltage. The drain of the fourth transistor is connected to the drain of the second transistor. The reference voltage is also connected to the source of the fifth transistor and the source of the first transistor. Furthermore, the drain of the first transistor is used to obtain the third current. An analog voltage signal is generated based on the gate voltage of the first transistor and the third current.

[0049] In some embodiments, the first transistor, the fourth transistor, the fifth transistor, and the analog switch are all N-type metal-oxide-semiconductor (negative channel metal oxide semiconductor, NMOS) transistors; the second transistor and the third transistor are both P-type metal-oxide-semiconductor (positive channel metal oxide semiconductor, PMOS) transistors. In other embodiments, the first transistor, the fourth transistor, the fifth transistor, and the analog switch are all PMOS transistors; and the second transistor and the third transistor are both NMOS transistors.

[0050] The first current, the second current, and the third current can be implemented based on a voltage source or a current source. For example, the transmission of the first current, the second current, and the third current is implemented by using one or more current sources. For another example, three bias voltages are set by using one or more voltage sources. Among the three bias voltages, the first bias voltage is used to implement the first current transmitted between the voltage source and the source of the second transistor, the second bias voltage is used to implement the second current transmitted between the voltage source and the gate of the first transistor, and the third bias voltage is used to implement the third current transmitted between the voltage source and the drain of the first transistor.

[0051] That is, the slew rate enhancement circuit 10 may further include at least one of a reference current source or a reference voltage source, wherein at least one of the reference current source or the reference voltage source is connected to the voltage signal generation circuit and configured to provide a control current to the voltage signal generation circuit. For example, the reference current source may be one or more current sources that transmit the first current, the second current, and the third current. For another example, the reference voltage source may be one or more voltage sources that set the three bias voltages.

[0052] The reference benchmark can be set to ground (GND) or a voltage source according to actual needs. The voltage value of the voltage source can be determined according to needs, and the embodiments of the present application are not limited to this.

[0053] Different situations of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the analog switch are described below respectively.

[0054] Case 1: the first transistor, the fourth transistor, the fifth transistor and the analog switch are all NMOS transistors; the second transistor and the third transistor are all PMOS transistors.

[0055] In this case, the structure of the slew rate enhancement circuit 10 can be as follows: Figure 2 As shown. Figure 2 In the figure, the first transistor is represented by ME, the second transistor is represented by MA, the third transistor is represented by MB, the fourth transistor is represented by MC, the fifth transistor is represented by MD, and the analog switch is represented by SWN. MC, MD, and ME are all NMOS transistors, while MA and MB are both PMOS transistors. The first current is represented by I1, the second current is represented by I2, and the third current is represented by I3. The input signal voltage is represented by Vin, and the output signal voltage is represented by Vout.

[0056] The source of the MA tube and the source of the MB tube both receive I1, the gate voltage of the MA tube is Vin, and the drain of the MA tube is connected to the drain and gate of the MC tube and the gate of the MD tube respectively. The source of the MC tube and the MD tube are connected to the reference reference respectively. Figure 2 In the circuit, the reference is GND. The gate voltage of the MB tube is Vout. The drain of the MB tube and the drain of the MD tube are both connected to the gate of the ME tube. The gate of the ME tube is also used to receive I2. The source of the ME tube is connected to the reference, and the drain of the ME tube is used to receive I3. The drain of the ME tube is also connected to the gate of the SWN tube. That is, the signal between the drain of the ME tube and the gate of the SWN tube is the generated analog voltage signal. Figure 2 In the example, the analog voltage signal is represented as the contn signal. The drain of the SWN tube is connected to the operational amplifier 20, which is not in operation. Figure 2 Shown in.

[0057] In the embodiment of the present application, the reference current can be implemented based on a current source or a metal-oxide-semiconductor (channel metal oxide semiconductor, MOS) transistor. Figure 2 Take the reference current based on NMOS transistor as an example for explanation. The NMOS transistor is called BSN tube, and the reference current is expressed as I_SRN. Figure 2 As shown, the source of the SWN transistor is connected to the drain of the BSN transistor. The gate of the BSN transistor is controlled by a voltage VBSN, and the value of VBSN can be set according to requirements. The source of the BSN transistor is connected to the reference. Figure 2 For the relevant content of SREN, please refer to the relevant instructions below, which will not be explained here.

[0058] Since the input signal is determined by the image that needs to be displayed on the monitor, the input signal has a rising edge and a falling edge. Figure 2 The illustrated structure is configured to operate on the falling edge of the input signal. At this falling edge, the voltage of the input signal is lower than the voltage of the output signal. That is, when the control current flows into the voltage signal generating circuit, the voltage signal generating circuit can be configured to generate an analog voltage signal based on the control current and the voltage difference between the input and output signals, even when the voltage of the input signal is lower than the voltage of the output signal.

[0059] For example, in Figure 2 In the structure shown, I1 is equal to twice I2, that is, I1 = 2*I2, and I3 is designed to be a very small current. When the falling edge of the input signal arrives, Vin is less than Vout, and the current flowing through the MB tube is I MB is 0, the current flowing through the MD tube I MD 、The current I flowing through the MC tube MC and the current I flowing through the MA tube MA Satisfy Formula I MD =I MC =I MA=I1. Since I1 is twice I2, I MB with I MD Satisfy the formula (I2+I MB ) MD =I1, the MD tube is pressed into the linear region, so that the gate voltage VE of the ME tube is approximately 0, and the ME tube enters the cut-off state.

[0060] In this case, I3 is greater than the current I flowing through the ME tube. ME , the contn signal is pulled high, thereby controlling the SWN transistor to turn on, and I_SRN flows into the operational amplifier 20 through the SWN transistor. Therefore, the current flowing into the operational amplifier 20 is equal to the sum of Itail and I_SRN, and the slew rate of the operational amplifier 20 is increased.

[0061] As Vout decreases, when Vout equals Vin, I MA and I MB Theoretically, they should be equal to 1 / 2 of I1. In this case, we can get the formula I MD =I MB =0.5*I1=I2. However, due to the existence of I2, MB tube will not be allocated 1 / 2 of I1, MB tube will be pressed into the linear region, and the gate voltage VE of ME tube will be pulled high. Therefore, the current I flowing through ME tube ME The contn signal is pulled low, turning off the SWN transistor. I_SRN does not flow into op amp 20 via the SWN transistor. Consequently, the current flowing into op amp 20 equals Itail, and the slew rate of op amp 20 is not increased, but op amp 20 still operates normally.

[0062] Since the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the analog switch can all be implemented by MOS transistors, the components of the slew rate enhancement circuit 10 and the internal component connection relationship are relatively simple, easy to implement and low cost.

[0063] Case 2: the first transistor, the fourth transistor, the fifth transistor and the analog switch are all PMOS transistors; the second transistor and the third transistor are all NMOS transistors.

[0064] In this case, the structure of the slew rate enhancement circuit 10 can be as follows: Figure 3 As shown. Figure 3 ​In the figure, the first transistor is MK, the second transistor is MF, the third transistor is MG, the fourth transistor is MH, the fifth transistor is MJ, and the analog switch is SWP. MH, MJ, and MK are all PMOS transistors, while MF and MG are both PMOS transistors. The first current is I4, the second current is I5, and the third current is I6. The input signal voltage is Vin, and the output signal voltage is Vout.

[0065] The source of the MF tube and the source of the MG tube are both connected to I4, the gate voltage of the MF tube is Vin, and the drain of the MF tube is respectively connected to the drain and gate of the MH tube and the gate of the MJ tube. The sources of the MH tube and the MJ tube are respectively connected to the reference standard, the gate voltage of the MG tube is Vout, the drain of the MG tube and the drain of the MJ tube are both connected to the gate of the MK tube, and the gate of the MK tube is also connected to I5. The source of the MK tube is connected to the reference standard, the drain of the MK tube is connected to I6, and the drain of the MK tube is also connected to the gate of the SWP tube, that is, the signal between the drain of the MK tube and the gate of the SWP tube is the generated analog voltage signal. Figure 3 In the example, the analog voltage signal is represented as the contp signal. The drain of the SWP tube is connected to the operational amplifier 20, which is not in the Figure 3 Shown in.

[0066] exist Figure 3 In the example, the reference standard can be a voltage source, and the voltage value of the voltage source can be determined according to the requirements, which can achieve Figure 3 The transmission directions of I4, I5 and I6 are sufficient, and the embodiments of the present application are not limited to this. Figure 3 The multiple voltage sources shown may be the same or different voltage sources, and the embodiments of the present application are not limited thereto.

[0067] based on Figure 3 In the structure shown, the reference current is realized based on a PMOS transistor, which is called a BSP transistor, and the reference current is expressed as I_SRP. Figure 3 As shown, the source of the SWP transistor is connected to the drain of the BSP transistor. The gate of the BSP transistor is controlled by a voltage VBSP, and the value of VBSP can be set according to requirements. The source of the BSP transistor is connected to the reference. Figure 3 For the relevant content of SREN, please refer to the relevant instructions below, which will not be expanded here.

[0068] Figure 3The illustrated structure is configured to operate on the rising edge of the input signal. On this rising edge, the voltage of the input signal is greater than the voltage of the output signal. That is, when the control current is directed out of the voltage signal generating circuit, the voltage signal generating circuit can be configured to generate an analog voltage signal based on the control current and the voltage difference between the input and output signals, even when the voltage of the input signal is greater than the voltage of the output signal.

[0069] For example, in Figure 3 In the structure shown, I4 is equal to twice of I5, that is, I4=2*I5, and I6 is designed to be a very small current. When the rising edge of the input signal arrives, Vin is greater than Vout, and the current flowing through the MG tube is I MG is 0, the current I flowing through the MJ tube MJ , the current I flowing through the MH tube MH and the current I flowing through the MF tube MF Satisfy Formula I MJ =I MH =I MF =I4. Since I4 is twice as much as I5, I MG with I MJ Satisfy the formula (I5+I MG ) MJ =I4, the MJ tube is turned on, so that the gate voltage VE of the MK tube is approximately 0, and the MK tube is turned on.

[0070] In this case, I6 is less than the current I flowing through the MK tube. MK , the contp signal is pulled to a low level, thereby controlling the SWP tube to be turned on, and I_SRP flows into the operational amplifier 20 through the SWP tube. Therefore, the current flowing into the operational amplifier 20 is equal to the sum of Itail and I_SRP, and the slew rate of the operational amplifier 20 is increased.

[0071] As Vout increases, when Vout equals Vin, I MF and I MG Theoretically, they should be equal to 1 / 2 of I4. In this case, we can get the formula I MJ =I MG =0.5*I4=I5. However, due to the existence of I5, the MG tube will not be allocated 1 / 2 of I4, the MG tube will be pressed into the linear region, and the gate voltage VK of the MK tube will be pulled high. Therefore, the current I flowing through the MK tube MK The contp signal is pulled high, turning off the SWP transistor. I_SRP does not flow into the op amp through the SWP transistor. Consequently, the current flowing into op amp 20 equals Itail, and the slew rate of op amp 20 is not increased, but op amp 20 still operates normally.​

[0072] Since the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the analog switch can all be implemented by MOS transistors, the components of the slew rate enhancement circuit 10 and the internal component connection relationship are relatively simple, easy to implement and low cost.

[0073] Figure 4 This is a schematic diagram of a signal change provided in an embodiment of the present application. Figure 4 Shows Vin, Vout, I MA , I MB , I2, VE, contp and contn signal changes. Figure 4 As shown, Vin has rising and falling edges. In phase 1, Vout rises until it is consistent with Vin, and in phase 2, Vout falls until it is consistent with Vin. At the beginning of phase 1, contp changes from high level to low level; at the end of phase 1, contp changes from low level to high level. At the beginning of phase 2, VE and contn change from low level to high level; at the end of phase 2, VE and contn change from high level to low level. In addition, in phase 2, I MA , I MB Both I and I2 increased, and I MA >I2>I MB After Phase 2, I MA It will decrease but still be greater than I2, I MB It will increase but still be less than I2.

[0074] In the embodiment of the present application, when the difference between Vin and Vout is large, the slew rate enhancement circuit 10 is used to process large signals; when the difference between Vin and Vout is small, the slew rate enhancement circuit 10 is used to process small signals. A large signal refers to a large difference between Vout and Vin, and a small signal refers to a small difference between Vout and Vin. For example, the dividing point between large signals and small signals is a reference threshold α, and the reference threshold α is as follows:

[0075] As shown in formula 2:

[0076]

[0077] Among them, I SR represents the current value of the reference current, μ represents the carrier mobility of the transistor included in the reference current mirror circuit, C ox represents the gate oxide capacitance per unit area of ​​the transistor included in the reference current mirror circuit, W represents the channel width of the transistor included in the reference current mirror circuit, and L represents the channel length of the transistor included in the reference current mirror circuit.

[0078] Therefore, when the difference between Vout and Vin is greater than or equal to the above In the case of a large difference between Vout and Vin, the analog voltage signal generated by the voltage signal generating circuit controls the analog switch to turn on; when the difference between Vout and Vin is less than the above In the case of , the difference between Vout and Vin is small, and the analog voltage signal generated by the voltage signal generating circuit controls the analog switch to be disconnected.

[0079] In combination with the above formula 2, the demarcation point where the analog switch is turned on or off is little affected by the size of the transistor. Therefore, when using transistors to implement the reference current mirror circuit, the sizes of the transistors do not need to be consistent. The reference current mirror circuit can be implemented using transistors of the smallest size, thereby saving the area of ​​the reference current mirror circuit and further saving the area of ​​the slew rate enhancement circuit 10.

[0080] Furthermore, actual verification has shown that, based on the structure of the slew rate enhancement circuit 10 provided in the embodiment of the present application, the demarcation point is relatively small, approximately 0.3 V. In other words, the slew rate enhancement circuit 10 stops inputting the reference current to the operational amplifier 20 only when it detects that the voltage difference between the input signal and the output signal is less than 0.3 V.

[0081] Compared to using a MOS transistor as a slew rate enhancement circuit and using the threshold voltage of a MOS transistor as the dividing point (the threshold voltage is usually in the range of 0.8V to 1V), the slew rate enhancement circuit 10 provided in the embodiment of the present application inputs the reference current to the operational amplifier 20 for a longer time, and the effect of enhancing the slew rate of the operational amplifier 20 is better.

[0082] Figure 5 This is a schematic diagram of a voltage change provided by an embodiment of the present application. Figure 5 , for the rising edge of the same input signal, the output signal approaches the same value as the input signal more quickly than the output signal obtained by the slew rate enhancement circuit 10 provided in the embodiment of the present application. In other words, the slew rate of the operational amplifier 20 connected to the slew rate enhancement circuit 10 provided in the embodiment of the present application is greater.

[0083] Furthermore, if Figure 5 As shown, for the output signal obtained by the slew rate enhancement circuit 10 provided in the embodiment of the present application, the voltage of the output signal increases rapidly in the range of 60%-90% of the voltage of the input signal, that is, within this range, the effect of increasing the slew rate is more obvious.

[0084] In some embodiments, the signal amplification circuit further includes a startup control circuit, which is connected to the slew rate enhancement circuit 10 and is used to control whether the slew rate enhancement circuit 10 is turned on or off. Thus, the startup control circuit can be controlled based on demand to turn the slew rate enhancement circuit 10 on or off, making the timing of turning the slew rate enhancement circuit 10 on or off more flexible and in line with demand.

[0085] The startup control circuit can be implemented based on a MOS transistor and a control element that controls the gate voltage of the MOS transistor. The embodiment of the present application does not limit the specific implementation form of the control element. Figure 2 In the illustrated embodiment, the startup control circuit is implemented using an NMOS transistor and a control element. This NMOS transistor is represented by an SREN transistor. The source of the SREN transistor is connected to a reference, and the drain of the SREN transistor is connected to the gate of the SWN transistor. When the gate voltage of the SREN transistor is low, the slew rate enhancement circuit 10 is enabled, that is, the slew rate enhancement circuit 10 is turned on. When the gate voltage of the SREN transistor is high, the slew rate enhancement circuit 10 is disabled, that is, the slew rate enhancement circuit 10 is turned off.

[0086] The structure of the slew rate enhancement circuit 10 is as follows Figure 3 In the illustrated embodiment, the startup control circuit is implemented using a PMOS transistor and a control element. This PMOS transistor is represented by an SREN transistor. The source of the SREN transistor is connected to a reference, and the drain of the SREN transistor is connected to the gate of the SWP transistor. When the gate voltage of the SREN transistor is high, the slew rate enhancement circuit 10 is enabled, that is, the slew rate enhancement circuit 10 is turned on. When the gate voltage of the SREN transistor is low, the slew rate enhancement circuit 10 is disabled, that is, the slew rate enhancement circuit 10 is turned off.

[0087] Figure 6 This is a schematic diagram of the connection between a signal amplification circuit and a display panel provided in an embodiment of the present application.

[0088] The signal amplification circuit being connected to the display panel may refer to the operational amplifier 20 in the signal amplification circuit being connected to the display panel. For example, the operational amplifier is connected to the display panel via an output switch. The signal amplification circuit and the display panel may be located in the same display.

[0089] exist Figure 6 In the figure, the display panel is represented by the load resistance R L With the load capacitance C LThe output switch is turned on and off by a first control signal. When the first control signal is valid, the output switch is turned on; when the first control signal is invalid, the output switch is turned off. The signal amplifier circuit may also be connected to an input switch, and the input switch is turned on and off by a second control signal. When the second control signal is valid, the input switch is turned on; when the second control signal is invalid, the input switch is turned off. Both the first control signal and the second control signal may be analog signals or digital signals. Figure 6 When the second control signal is valid, the input switch is controlled to be turned on, and the input signal Vin is input to the signal amplification circuit; when the first control signal is valid, the output switch is controlled to be turned on, and the output signal Vout is output to the display panel.

[0090] Typically, the first control signal's active time is controlled to be 200 to 500 nanoseconds (ns) later than the second control signal's active time to optimize signal integrity, reduce power consumption, and smooth the output response to prevent transient voltage surges on the panel. In other words, there's a delay between the first control signal's active time and the second control signal's active time. While this delay can smooth the output response, it can also introduce significant transient current.

[0091] Combine Figure 6 The schematic diagram provided shows that by setting a delay between the effective time of the first control signal and the effective time of the second control signal, the input switch will be turned on before the output switch, the slew rate enhancement circuit 10 will start working, and the output voltage of the operational amplifier 20 will accumulate to a higher level. After the output switch is turned on, the output terminal of the operational amplifier 20 is connected to the load capacitor C of the display panel. L There will be a large voltage difference between the upper and lower ends of the capacitors. This large voltage difference will cause a large transient current. The large transient current will have a great impact on the load capacitance C. L To charge, the load capacitor C L The amount of electricity stored in the CMOS will cause a sudden change in current, which will cause fluctuations in the power supply network. This fluctuation will couple to the voltage signal output by the operational amplifier 20, generating switching noise. Switching noise will degrade the image quality of the display panel. Therefore, it is necessary to optimize the transient current to suppress switching noise.

[0092] In a possible implementation, when the operational amplifier 20 is connected to the display panel via an output switch, the startup control circuit is used to start the slew rate enhancement circuit 10 after the output switch is turned on. That is, during the delay period, although the input switch is turned on, the slew rate enhancement circuit 10 is not turned on. The slew rate enhancement circuit 10 is not turned on until the output switch is turned on under the control of the startup control circuit. For example, based on the first control signal being valid, the output switch is turned on, and the control element is pulled down. Figure 2 The gate voltage of the SREN tube is increased to turn on the slew rate enhancement circuit 10. Alternatively, based on the first control signal being valid, the output switch is turned on and the control element is pulled high. Figure 3 The gate voltage of the SREN transistor is increased to turn on the slew rate enhancement circuit 10. Therefore, during the delay period, the slew rate enhancement circuit 10 remains in the off state.

[0093] Compared to the situation where the slew rate enhancement circuit 10 remains on during the delay period, causing the voltage at the output of the operational amplifier 20 to quickly reach a high level during the delay period, by keeping the slew rate enhancement circuit 10 off during the delay period, the voltage at the output will rise only after the first control signal becomes valid, resulting in a lower output voltage value and a smaller transient current, thereby reducing switching noise. Furthermore, because the operating mode of the slew rate enhancement circuit 10 is not affected, the slew rate enhancement circuit 10 can still input a reference current to the operational amplifier 20 after being turned on, if the voltage difference between the input signal and the output signal of the operational amplifier 20 is greater than the reference threshold, thereby increasing the slew rate of the operational amplifier 20. Therefore, the solution provided by the embodiment of the present application can reduce switching noise while increasing the slew rate of the operational amplifier 20.

[0094] Figure 7 This is another schematic diagram of signal changes provided by the embodiment of the present application. Figure 7 As shown, compared to the method of turning on the slew rate enhancement circuit 10 before the output switch is turned on, by turning on the slew rate enhancement circuit 10 after the output switch is turned on, the time for contp to change from a high level to a low level and then from a low level to a high level is delayed, but the voltage of the output signal can still change quickly to be consistent with the voltage of the input signal, that is, the slew rate of the operational amplifier is higher; and the transient current can be reduced, that is, the switching noise is lower.

[0095] The embodiment of the present application also provides a signal amplification method, which is performed by a signal amplification circuit. The signal amplification circuit includes a slew rate enhancement circuit and an operational amplifier, and the slew rate enhancement circuit is connected to the operational amplifier. Figure 8 As shown, the method includes but is not limited to steps 801 to 802.

[0096] Step 801: Detect the voltage difference between the input signal and the output signal of the operational amplifier through a slew rate enhancement circuit.

[0097] In step 802 , when the voltage difference is greater than a reference threshold, a reference current is input to the operational amplifier through a slew rate enhancement circuit. The reference current is used to increase the slew rate of the operational amplifier. The reference threshold is determined based on the current value of the reference current.

[0098] Exemplarily, when the voltage difference between the input signal and the output signal of the operational amplifier is less than or equal to the reference threshold, the reference current is stopped from being input into the operational amplifier.

[0099] In one possible implementation, the slew rate enhancement circuit includes: a voltage signal generating circuit and an analog switch, the voltage signal generating circuit being connected to the operational amplifier through the analog switch; the voltage signal generating circuit being used to obtain a control current and detect a voltage difference between an input signal and an output signal of the operational amplifier; the voltage signal generating circuit being further used to generate an analog voltage signal based on the control current and the voltage difference, wherein, when the voltage difference is greater than a reference threshold, the analog voltage signal is used to control the analog switch to conduct, so as to input a reference current into the operational amplifier.

[0100] In one possible implementation, the control current includes a first current, a second current, and a third current; the voltage signal generating circuit includes: a reference current mirror circuit and a voltage control element, the voltage control element being connected to the reference current mirror circuit and the analog switch, respectively; the reference current mirror circuit is used to obtain the first current and the second current, and detect the voltage difference between the input signal and the output signal of the operational amplifier; the reference current mirror circuit is also used to control the input voltage of the voltage control element based on the voltage difference, the first current, and the second current; the voltage control element is used to generate an analog voltage signal based on the input voltage of the voltage control element and the third current.

[0101] Exemplarily, the voltage-controlled element is a transistor, which may be referred to as a first transistor. In this case, the output voltage of the voltage-controlled element may be the gate voltage of the first transistor. Thus, the reference current mirror circuit may be configured to control the gate voltage of the first transistor based on the voltage difference, the first current, and the second current. The first transistor may be configured to generate an analog voltage signal based on the gate voltage of the first transistor and the third current.

[0102] Exemplarily, the reference current mirror circuit includes: a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein, the gate voltage of the second transistor is the voltage of the input signal of the operational amplifier, the source of the second transistor is used to obtain the first current, and the drain of the second transistor is connected to the gates of the fourth transistor and the fifth transistor, respectively; the gate voltage of the third transistor is the voltage of the output signal of the operational amplifier, the source of the third transistor is used to obtain the first current, the drain of the third transistor is connected to the drain of the fifth transistor and the gate of the first transistor, respectively, and the gate of the first transistor is also used to obtain the second current; the source of the fourth transistor is connected to the reference base, the drain of the fourth transistor is connected to the drain of the second transistor, and the reference base is also connected to the source of the fifth transistor and the source of the first transistor; the drain of the first transistor is used to obtain the third current, and an analog voltage signal is generated based on the gate voltage of the first transistor and the third current.

[0103] For example, the first transistor, the fourth transistor, the fifth transistor, and the analog switch are all NMOS transistors; the second transistor and the third transistor are all PMOS transistors. For another example, the first transistor, the fourth transistor, the fifth transistor, and the analog switch are all PMOS transistors; the second transistor and the third transistor are all NMOS transistors.

[0104] In some embodiments, the slew rate enhancement circuit further includes at least one of a reference current source or a reference voltage source, wherein the at least one of the reference current source or the reference voltage source is connected to the voltage signal generation circuit and configured to provide a control current to the voltage signal generation circuit. For example, the control current includes the first current, the second current, and the third current described above.

[0105] For example, the direction of the control current is the direction of the current flowing into the voltage signal generating circuit, and the voltage signal generating circuit is used to generate an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is less than the voltage of the output signal. In this case, the structure of the slew rate enhancement circuit can be as follows: Figure 2 shown.

[0106] For example, the direction of the control current is the direction of flowing out of the voltage signal generating circuit, and the voltage signal generating circuit is used to generate an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is greater than the voltage of the output signal. In this case, the structure of the slew rate enhancement circuit can be as follows: Figure 3 shown.

[0107] In the signal amplification method provided in an embodiment of the present application, a slew rate enhancement circuit can detect the voltage difference between the input signal and the output signal of an operational amplifier. When the voltage difference is greater than a reference threshold, a reference current is input into the operational amplifier to increase the slew rate of the operational amplifier. The reference threshold is determined based on the current value of the reference current. Thus, by inputting the reference current into the operational amplifier, the slew rate of the operational amplifier can be increased.

[0108] In one possible implementation, the signal amplification circuit further includes a startup control circuit connected to the slew rate enhancement circuit. The method further includes: controlling the slew rate enhancement circuit to be turned on or off by the startup control circuit. Thus, the startup control circuit can be controlled based on demand to turn the slew rate enhancement circuit on or off, making the timing of turning the slew rate enhancement circuit on or off more flexible and meeting demand.

[0109] In one possible implementation, the operational amplifier is connected to the display panel via an output switch; and the slew rate enhancement circuit is turned on or off by a startup control circuit, including: turning on the slew rate enhancement circuit after the output switch is turned on by the startup control circuit.

[0110] By keeping the slew rate enhancement circuit off during the delay period, the voltage at the output of the operational amplifier will rise only after the first control signal becomes active. This results in a lower output voltage, smaller transient current, and thus lower switching noise. Furthermore, because the operating mode of the slew rate enhancement circuit is not affected, the slew rate enhancement circuit can still input a reference current to the operational amplifier when the analog switch is on, thereby increasing the slew rate of the operational amplifier. Therefore, this method can reduce switching noise while increasing the slew rate of the operational amplifier.

[0111] It should be understood that the above method embodiment and the signal amplifying circuit described above belong to the same concept, and the specific implementation process thereof is detailed in the embodiment of the signal amplifying circuit, which will not be repeated here.

[0112] In an exemplary embodiment, a chip is also provided, such as Figure 9 As shown, chip 900 includes the signal amplification circuit mentioned above, and the signal amplification circuit is used to perform the signal amplification circuit method mentioned above. The chip can be a display driver or a display driver chip. The display driver can be a source driver or a gate driver. The display driver chip can be a chip integrating a source driver and a gate driver. In one possible implementation, the chip is an integrated chip that integrates multiple functions. That is, the function of enhancing the slew rate of the operational amplifier is part of the function of the integrated chip, and the integrated chip also supports other functions.

[0113] In an exemplary embodiment, an electronic device is also provided, such as Figure 10As shown, the electronic device 1000 includes the chip 900 mentioned above, so that the electronic device 1000 includes the signal amplification circuit mentioned above, and the electronic device 1000 can implement the signal amplification method mentioned above. The electronic device 1000 is, for example, a terminal or a server. For example, the terminal can be any electronic product that can interact with the user through one or more methods such as a keyboard, touchpad, touch screen, remote control, voice interaction or handwriting device, such as a PC (Personal Computer), a mobile phone, a smart phone, a PDA (Personal Digital Assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a laptop computer, a desktop computer, a smart car machine, a smart TV, a smart speaker or player, etc. The terminal may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal, etc. Other names. The electronic device 1000 can also be a server, or a server cluster composed of multiple servers. Alternatively, the electronic device 1000 can be any other device that can be equipped with the above-mentioned chip 900.

[0114] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0115] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0116] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A signal amplification circuit, characterized in that: The signal amplification circuit includes a slew rate enhancement circuit and an operational amplifier, and the slew rate enhancement circuit is connected to the operational amplifier; The slew rate enhancement circuit is used to detect the voltage difference between the input signal and the output signal of the operational amplifier; The slew rate enhancement circuit is further used to input a reference current into the operational amplifier when the voltage difference is greater than a reference threshold value. The reference current is used to increase the slew rate of the operational amplifier. The reference threshold value is determined based on the current value of the reference current.

2. The signal amplifying circuit according to claim 1, wherein: The slew rate enhancement circuit includes: a voltage signal generating circuit and an analog switch, wherein the voltage signal generating circuit is connected to the operational amplifier via the analog switch; The voltage signal generating circuit is used to obtain the control current and detect the voltage difference between the input signal and the output signal of the operational amplifier; The voltage signal generating circuit is further used to generate an analog voltage signal based on the control current and the voltage difference, wherein when the voltage difference is greater than the reference threshold, the analog voltage signal is used to control the analog switch to be turned on to input the reference current into the operational amplifier.

3. The signal amplifying circuit according to claim 2, wherein: The control current includes a first current, a second current, and a third current; the voltage signal generating circuit includes: a reference current mirror circuit and a voltage control element, and the voltage control element is connected to the reference current mirror circuit and the analog switch respectively; The reference current mirror circuit is used to obtain the first current and the second current, and detect the voltage difference between the input signal and the output signal of the operational amplifier; The reference current mirror circuit is further configured to control an input voltage of the voltage control element based on the voltage difference, the first current, and the second current; The voltage control element is configured to generate the analog voltage signal based on an input voltage of the voltage control element and the third current.

4. The signal amplifying circuit according to claim 2, wherein: The slew rate enhancement circuit also includes at least one of a reference current source or a reference voltage source, and at least one of the reference current source or the reference voltage source is connected to the voltage signal generating circuit, and at least one of the reference current source or the reference voltage source is used to provide the control current to the voltage signal generating circuit.

5. The signal amplifying circuit according to claim 4, wherein: The direction of the control current is the direction of flowing into the voltage signal generating circuit, and the voltage signal generating circuit is used to perform an operation of generating an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is less than the voltage of the output signal.

6. The signal amplifying circuit according to claim 4, wherein: The direction of the control current is the direction of flowing out of the voltage signal generating circuit, and the voltage signal generating circuit is used to perform an operation of generating an analog voltage signal based on the control current and the voltage difference when the voltage of the input signal is greater than the voltage of the output signal.

7. The signal amplifying circuit according to any one of claims 1 to 6, characterized in that: The signal amplifying circuit further includes a startup control circuit, and the startup control circuit is connected to the slew rate enhancement circuit; The startup control circuit is used to control the opening or closing of the slew rate enhancement circuit.

8. The signal amplifying circuit according to claim 7, wherein: The operational amplifier is connected to the display panel via an output switch; The startup control circuit is used to start the slew rate enhancement circuit after the output switch is turned on.

9. A chip, characterized in that: The chip includes the signal amplification circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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