Pwm signal generation method, module and related apparatus

Abstract

This invention discloses a PWM signal generation method, module, and related apparatus. The PWM signal generation method includes: sampling a comparison signal based on a sampling period; determining the magnitude relationship between the actual current and the commanded current of the motor based on the comparison signal; selecting either the upper or lower switching transistor of the driver based on the determination result; determining whether the current on-time of the selected switching transistor has reached the minimum on-time; if so, generating an upper transistor control signal and / or a lower transistor control signal based on the determination result; otherwise, re-sampling the comparison signal based on the sampling period. According to the PWM signal generation method, module, and related apparatus of this invention, only the actual current and the commanded current need to be compared, making analog circuit calibration easier. Furthermore, the determination of the switching transistor's on-time and dead time is introduced, which can ensure the safety of the switching devices.

Description

Technical Field

[0001] This invention belongs to the field of servo drives, and specifically relates to a PWM signal generation method, module and related device. Background Technology

[0002] Current hysteresis control is a current control strategy applied to servo drives. The basic idea of ​​current hysteresis control is to give a three-phase current signal and compare it with the three-phase current measured by a current transformer. The comparison result is used to control the switching of power devices through a comparator, so that the actual current value follows the commanded current value.

[0003] Figure 1 A schematic diagram of a current hysteresis control principle is shown, taking phase U as an example; the V / W phases are similar. During current hysteresis control, one input to the current comparator is the actual current feedback Act_iu1, and the other is the command current Cmd_iu1. When the actual current value catches up with the command current value, the two inputs to the comparator are equal. At this time, the comparator outputs a comparison signal U_isens, which is a digital signal with a duty cycle of approximately 50%. Therefore, a comparison result of a digital signal with a duty cycle of approximately 50% can be considered one of the indicators of current following in the current hysteresis control method.

[0004] The FPGA control module is used to generate PWM switching signals based on the received comparison signal U_isens. It is a key component that enables the actual current to follow the command current, affecting the speed and accuracy of current following, as well as the safety of the switching devices.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a PWM signal generation method, module, and related device, which can generate PWM signals through simple judgment conditions, while also ensuring the safety of the driver.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0008] A PWM signal generation method for a driver includes: sampling a comparison signal based on a sampling period, the comparison signal being used to characterize the magnitude relationship between the actual current of the motor and the commanded current; determining the magnitude relationship between the actual current of the motor and the commanded current based on the comparison signal; selecting an upper switch or a lower switch of the driver based on the determination result; determining whether the current on-time of the selected switch has reached the minimum on-time; if yes, generating an upper switch control signal and / or a lower switch control signal based on the determination result; if no, re-sampling the comparison signal based on the sampling period.

[0009] In one or more embodiments of the present invention, sampling the comparison signal based on the sampling period includes: determining whether a new sampling period has been entered since the last sampling comparison signal; if so, sampling the comparison signal; if not, continuing to wait until a new sampling period is entered.

[0010] In one or more embodiments of the present invention, selecting the upper switch or the lower switch of the driver based on the determination result includes: if the actual current of the motor is less than the command current, then the lower switch of the driver is selected; if the actual current of the motor is greater than the command current, then the upper switch of the driver is selected.

[0011] In one or more embodiments of the present invention, generating an upper-side control signal and / or a lower-side control signal based on the determination result includes: if the actual current of the motor is less than the commanded current, generating a low-level lower-side control signal, and based on the state of the lower-side control signal, generating a high-level upper-side control signal or resampling the comparison signal based on the sampling period; if the actual current of the motor is greater than the commanded current, generating a low-level upper-side control signal, and based on the state of the upper-side control signal, generating a high-level lower-side control signal or resampling the comparison signal based on the sampling period.

[0012] In one or more embodiments of the present invention, when the actual current of the motor is less than the commanded current, selecting to generate the high-level lower-level control signal or resample the comparison signal based on the state of the lower-level control signal includes: determining whether the lower-level control signal is low at the end of the previous sampling period; if so, generating the high-level upper-level control signal; if not, determining whether the current time has exceeded a preset time since the generation of the low-level lower-level control signal; if so, generating the high-level upper-level control signal; if not, resampling the comparison signal based on the sampling period.

[0013] In one or more embodiments of the present invention, when the actual current of the motor is less than the commanded current, selecting to generate the high-level upper-side control signal or resample the comparison signal based on the state of the upper-side control signal includes: determining whether the upper-side control signal is low at the end of the previous sampling period; if so, generating the high-level lower-side control signal; if not, determining whether the current time has exceeded a preset time since the generation of the low-level upper-side control signal; if so, generating the high-level lower-side control signal; if not, resampling the comparison signal based on the sampling period.

[0014] In one or more embodiments of the present invention, the PWM signal generation method further includes: performing filtering preprocessing on the comparison signal.

[0015] A specific embodiment of the present invention also provides a PWM signal generation module, the PWM signal generation module including at least one processor; and a memory, the memory storing instructions, which, when executed by the at least one processor, cause the at least one processor to perform the PWM signal generation method as described above.

[0016] A specific embodiment of the present invention also provides a driver, including a comparison module, a PWM signal generation module, and a switching module. The comparison module is connected to a motor and a controller to compare the magnitude of the actual current and the commanded current to generate a comparison signal. The PWM signal generation module is connected to the comparison module to receive the comparison signal and generate an upper transistor control signal and a lower transistor control signal based on the above-described PWM signal generation method. The switching module includes an upper switch and a lower switch, which are connected to the motor. The upper switch is connected to the PWM signal generation module to control the switching on and off based on the upper transistor control signal, and the lower switch is connected to the PWM signal generation module to control the switching on and off based on the lower transistor control signal.

[0017] A specific embodiment of the present invention also provides a motor system, including a motor and a driver as described above, wherein the driver is connected to the motor.

[0018] Compared with existing technologies, the PWM signal generation method, module, and related devices of this invention only require comparing the actual current with the commanded current, making analog circuit calibration easier. Furthermore, the invention introduces the determination of the switching transistor's turn-on time and dead time, ensuring the safety of the switching devices. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the control principle of current hysteresis in existing technology.

[0021] Figure 2 This is a flowchart of a PWM signal generation method in one embodiment of the present invention.

[0022] Figure 3 This is a flowchart of some steps of a PWM signal generation method in one embodiment of the present invention.

[0023] Figure 4 This is a flowchart of a preferred embodiment of the PWM signal generation method according to one embodiment of the present invention.

[0024] Figure 5 This is a schematic diagram of the PWM signal generation module in one embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of the driver structure in one embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram of the switch module in one embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0028] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0029] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0030] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0031] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0032] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0033] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0034] Example 1

[0035] like Figure 2 As shown, a PWM signal generation method in one embodiment of the present invention is used for a driver, and the method specifically includes:

[0036] S1 is based on sampling comparison signals during the sampling period.

[0037] The comparison signal is used to characterize the relationship between the actual current of the motor and the commanded current.

[0038] S2 determines the relationship between the actual current of the motor and the commanded current based on the comparison signal.

[0039] S3 selects the upper or lower switch of the driver based on the judgment result, and determines whether the current turn-on time of the selected switch has reached the minimum turn-on time. If so, it generates the upper switch control signal and / or the lower switch control signal based on the judgment result. If not, it resamples the comparison signal based on the sampling period.

[0040] In one embodiment, the motor is connected to and driven by a driver, and the command current can be generated by a controller connected to the driver. A comparison signal is generated by comparing the actual current of the motor with the command current using a comparator. For example, if the command current is greater than the actual current, the comparison signal is high, which can be represented by "1"; if the command current is less than the actual current, the comparison signal is low, which can be represented by "0".

[0041] In one embodiment, the upper switch is turned on by a high-level upper switch control signal and turned off by a low-level upper switch control signal. The lower switch is turned on by a high-level lower switch control signal and turned off by a low-level lower switch control signal. In other embodiments, the high and low levels can be interchanged, and the control logic will be adjusted accordingly. It is understood that both the upper and lower switch control signals are PWM signals.

[0042] Understandably, for a three-phase motor, each phase corresponds to an actual current, a command current, and a comparison signal. Therefore, in this solution, after obtaining the comparison signal of a certain phase, the corresponding control signal and other actions should also be used for the corresponding phase in the driver.

[0043] Preferably, the PWM signal generation method in this embodiment may further include filtering the comparison signal to remove interference. In one embodiment, the comparison signal may be filtered before sampling based on the sampling period, resulting in a filtered comparison signal, and subsequent processes are also performed based on the filtered comparison signal. In other embodiments, the comparison signal may be filtered after sampling based on the sampling period, and subsequent processes are also performed based on the filtered comparison signal.

[0044] For example, the comparison signal can be filtered for a set duration (frequency) to filter out comparison signals whose duration is less than the set duration (frequency outside the set frequency bandwidth). The set duration is preferably 500ns (i.e., frequency exceeding 2MHz). Of course, the specific filtering parameters can also be set according to the actual situation.

[0045] Furthermore, in step S1, sampling the comparison signal based on the sampling period includes: determining whether a new sampling period has begun since the last acquisition of the comparison signal; if so, sampling the comparison signal; if not, continuing to wait until a new sampling period begins.

[0046] By setting a sampling period and sampling only one comparison signal in each sampling period, the comparison signal is avoided from being acquired too frequently, and it is also ensured that only one switching control action can be performed within one sampling period.

[0047] Furthermore, in step S3, selecting the upper switching transistor or the lower switching transistor of the driver based on the judgment result includes:

[0048] If the actual current of the motor is less than the commanded current (i.e., the comparison signal is high or the comparison signal is 1), then the lower switching transistor of the driver is selected.

[0049] If the actual current of the motor is greater than the command current (i.e., the comparison signal is low or the comparison signal is 0), then select the upper switching transistor of the driver.

[0050] Next, it is determined whether the selected switch has been on for the current time and reached the minimum on time. If the selected switch is currently off, then the current on time is 0 seconds. If the selected switch is currently on, then the current on time refers to the duration the selected switch has been on since it last switched to the on state until the current moment.

[0051] For example, the duration of continuous operation of the up / down switching transistor from the last time it switched to the on state until the current moment can be obtained by recording the time when the up / down transistor control signal is at a high level, thus eliminating the need to sample other signals.

[0052] like Figure 3 As shown, in step S3, generating the upper tube control signal and / or lower tube control signal based on the judgment result includes:

[0053] If the actual current of the motor is less than the commanded current (i.e., the comparison signal is high or the comparison signal is 1), S301 generates a low-level lower transistor control signal, and based on the state of the lower transistor control signal, selects to generate a high-level upper transistor control signal or resamples the comparison signal based on the sampling period.

[0054] Specifically, when the actual current of the motor is less than the commanded current, based on the state of the lower transistor control signal, the selection to generate a high-level lower transistor control signal or to resample the comparison signal based on the sampling period includes:

[0055] If the lower transistor control signal is low at the end of the previous sampling period, a high-level upper transistor control signal is generated.

[0056] If not, determine whether the current time has exceeded the preset time since the generation of the low-level lower transistor control signal. If yes, generate a high-level upper transistor control signal. If no, resample the comparison signal based on the sampling period.

[0057] If the actual current of the motor is greater than the commanded current (i.e., the comparison signal is low or the comparison signal is 0), S302 generates a low-level upper transistor control signal, and based on the state of the upper transistor control signal, selects to generate a high-level lower transistor control signal or resamples the comparison signal based on the sampling period.

[0058] Specifically, when the actual current of the motor is less than the commanded current, based on the state of the upper transistor control signal, the selection to generate a high-level upper transistor control signal or to resample the comparison signal based on the sampling period includes:

[0059] Determine whether the upper transistor control signal is low at the end of the previous sampling period. If so, generate a high-level lower transistor control signal.

[0060] If not, determine whether the current time has exceeded the preset time since the generation of the low-level upper-side control signal. If yes, generate a high-level lower-side control signal. If no, resample the comparison signal based on the sampling period.

[0061] Finally, if a high-level up / down control signal is generated, the process returns to the step of sampling the comparison signal based on the sampling period, and the up / down control signal is generated repeatedly.

[0062] In the above steps, by determining whether the upper / lower switching transistor has reached its minimum on-time, and only proceeding with subsequent switching control steps after reaching the minimum on-time, it is ensured that once the upper / lower switching transistor is turned on, it must reach the minimum on-time before the switching state can be changed, thus limiting the maximum switching frequency of the driver. While higher switching frequencies result in higher control accuracy and faster response, they also generate more heat from the switching devices, placing higher demands on them. By setting this step, different maximum frequency thresholds can be selected according to actual conditions to match different accuracy and configuration requirements.

[0063] Next, by setting up a status judgment step for the control signal, it is ensured that after one of the upper / lower switching transistors is turned off, the other transistor can only be turned on after a certain period of time, thus ensuring the dead time and preventing a short circuit caused by both transistors being in the on state at the same time.

[0064] By judging the state of the control signal from the previous cycle, if the control signal is already low, it means that the corresponding switch has been off for at least a period of time. At this point, it is no longer necessary to calculate or compare the actual off time; it can be directly assumed that a dead time has elapsed, and the process proceeds to the next step, generating a high-level corresponding control signal to turn on the corresponding switch. This reduces waiting time and calculation steps.

[0065] The table below shows preferred embodiments of the preset duration, minimum turn-on time of the upper switch, and minimum turn-on time of the lower switch corresponding to the maximum frequency threshold. The minimum turn-on time of the upper switch is set to 500 ns in all cases. This is to avoid imposing too many restrictions on the minimum turn-on time of the upper switch, preventing device damage due to excessively long turn-on times. Of course, the minimum turn-on time of the upper switch can also be increased as the maximum frequency threshold decreases. For example, when the maximum frequency threshold is 200 kHz, the minimum turn-on time of the upper switch is 500 ns. When the maximum frequency threshold is 100 kHz, the minimum turn-on time of the upper switch is 600 ns.

[0066] When the maximum frequency threshold is 50kHz, the minimum turn-on time of the upper switching transistor is 700ns.

[0067] Maximum frequency threshold 200kHz 100kHz 50kHz Preset duration 1us 1.5us 4us Minimum turn-on time of the upper switch transistor 500ns 500ns 500ns Minimum turn-on time of the lower switch transistor 3.5us 8us 15.5us

[0068] Example 2

[0069] Figure 4 The diagram shows an overall flowchart of a preferred embodiment of the PWM signal generation method in Example 1. The example used is the generation of a U-phase PWM signal with a maximum frequency threshold of 200kHz.

[0070] After starting, the comparison signal is first filtered and preprocessed. Figure 4 This step is not shown in the diagram, but it can be assumed that the sampled comparison signal is already the filtered comparison signal U_ISENS_F.

[0071] Next, it determines whether a new sampling period has begun. If so, the comparison signal is sampled. If not, it waits until a new sampling period begins.

[0072] Next, the comparison signal is used to determine the relationship between the actual motor current and the commanded current. If the comparison signal is high (U_ISENS_F = 1), meaning the actual motor current is less than the commanded current, the process branch on the left is selected. If the comparison signal is low (U_ISENS_F = 0), meaning the actual motor current is greater than the commanded current, the process branch on the right is selected.

[0073] When the comparison signal is high and enters the left-hand process branch, it then determines whether the current turn-on time of the lower switch transistor has reached the minimum turn-on time (3.5us). If yes, it proceeds to the next step; otherwise, it returns to determining whether to enter a new sampling cycle.

[0074] Next, a low-level down-transistor control signal PWM_UBOT is generated.

[0075] Next, it is determined whether the lower MOSFET control signal PWM_UBOT_LAST at the end of the previous sampling cycle is low. If it is, a high-level upper MOSFET control signal PWM_UTOP is generated. If not, the next step is performed.

[0076] Next, it is determined whether the preset time has elapsed since the low-level lower MOSFET control signal PWM_UBOT was generated. If so, a high-level upper MOSFET control signal PWM_UTOP is generated. If not, the process returns to determining whether to enter a new sampling cycle.

[0077] After generating a high-level control signal PWM_UTOP for the upper transistor, the process returns to the step of determining whether to enter a new sampling period, thus completing one loop.

[0078] In the above process, the comparison signal is the comparison signal of phase U, the up / down switch transistor is the up / down switch transistor of phase U, and the up / down switch transistor control signal is used to control the up / down switch transistor of phase U.

[0079] The above describes the PWM signal generation method in this embodiment when the comparison signal is high. The process is similar when the comparison signal is low, except that the implementation object is changed accordingly, which will not be elaborated on here.

[0080] Understandably, the method for generating the W / V phase PWM signal is the same as the method for generating the U phase PWM signal described above. It is only necessary to replace the comparison signal, the up / down switching transistor, and the up / down transistor control signal mentioned above with the comparison signal, the up / down switching transistor, and the up / down transistor control signal of the corresponding phase.

[0081] Example 3

[0082] like Figure 5As shown, this embodiment also discloses a PWM signal generation module. The PWM signal generation module 10 includes at least one processor 11, a memory 12 (e.g., non-volatile memory), a main memory 13, and a communication interface 14. The at least one processor 11, memory 12, main memory 13, and communication interface 14 are connected together via a bus 15. The at least one processor 11 executes at least one computer-readable instruction stored or encoded in the memory 12. In one embodiment, the processor 11 may be an FPGA. In other embodiments, the processor 11 may also be a DSP, MCU, or other control device.

[0083] Understandably, the computer-executable instructions stored in memory 12, when executed, cause at least one processor 11 to perform the various operations and functions described in Embodiment 1 or Embodiment 2.

[0084] Example 4

[0085] like Figure 6 As shown, this embodiment also discloses a driver, which includes a signal processing module 20, a comparison module, a PWM signal generation module, and a switching module.

[0086] The signal processing module is connected to the motor, controller, and comparison module to process the actual current and commanded current, and then sends the processed signal to the comparison module. The comparison module compares the magnitudes of the actual current and the commanded current to generate a comparison signal.

[0087] In other embodiments, a signal processing module may be omitted, and the comparison module may be directly connected to the motor and controller to receive the actual current and the command current.

[0088] The PWM signal generation module is connected to the comparison module to receive the comparison signal, and generates the upper MOSFET control signal and the lower MOSFET control signal based on the PWM signal generation method in Embodiment 1 or 2. In one embodiment, the PWM signal generation module in this embodiment can be the PWM signal generation module in Embodiment 3.

[0089] The switching module includes an upper switching transistor and a lower switching transistor, which are connected to the motor. The upper switching transistor is connected to a PWM signal generation module to control the motor to turn on and off based on the upper transistor control signal, and the lower switching transistor is connected to the PWM signal generation module to control the motor to turn on and off based on the lower transistor control signal.

[0090] like Figure 6 As shown, in one embodiment, the signal processing module 20 includes a current transformer, a first operational amplifier circuit, a digital-to-analog converter, and a second operational amplifier circuit.

[0091] The current transformer is connected to the motor, and the first operational amplifier circuit is connected to the current transformer and the current comparison module. The current transformer collects the actual current of the motor and transmits it to the first operational amplifier circuit for amplification and modulation, and finally outputs it to the comparison module.

[0092] The digital-to-analog converter is connected to the controller, and the second operational amplifier circuit is connected to the digital-to-analog converter and the current comparison module. The digital-to-analog converter converts the digital command current generated by the controller into an analog quantity, and the second operational amplifier circuit amplifies the analog command current and outputs it to the comparison module.

[0093] In one embodiment, the motor is a three-phase servo motor, which generates three-phase actual current, and the controller generates three-phase command current. The signal processing module 20 performs signal processing on the three-phase actual current and the three-phase command current respectively (the same applies to each device in the signal processing module 20).

[0094] The comparison module compares the actual three-phase currents and the commanded three-phase currents to generate three-phase comparison signals (U-phase comparison signal U_isense is generated by comparing the actual U-phase current and the commanded U-phase current; W-phase comparison signal W_isense is generated by comparing the actual W-phase current and the commanded W-phase current; and V-phase comparison signal V_isense is generated by comparing the actual V-phase current and the commanded V-phase current). The PWM signal generation module generates three sets of control signals based on the three-phase comparison signals: a first upper MOSFET control signal PWM_U_TOP and a first lower MOSFET control signal PWM_U_BOT are generated based on the U-phase comparison signal U_isense; a second upper MOSFET control signal PWM_W_TOP and a second lower MOSFET control signal PWM_W_BOT are generated based on the W-phase comparison signal W_isense; and a third upper MOSFET control signal PWM_V_TOP and a third lower MOSFET control signal PWM_V_BOT are generated based on the V-phase comparison signal V_isense.

[0095] like Figure 7 As shown, the switch module has three components, namely the first upper switch T1 and the first lower switch T4, the second upper switch T2 and the second lower switch T5, and the third upper switch T3 and the third lower switch T6.

[0096] The first upper switch T1, the first lower switch T4, the second upper switch T2, the second lower switch T5, the third upper switch T3, and the third lower switch T6 can be NPN transistors, PNP transistors, N-channel MOSFETs, P-channel MOSFETs, N-channel IGBTs, P-channel IGBTs, thyristors, etc. A diode can also be connected in series between the first and second terminals of each switch.

[0097] In this embodiment, the first upper switch T1, the first lower switch T4, the second upper switch T2, the second lower switch T5, the third upper switch T3, and the third lower switch T6 are N-channel MOSFETs.

[0098] The source of the first upper switch T1 is connected to the drain of the first lower switch T4 and to the first phase terminal of the motor's three-phase terminals. The source of the second upper switch T2 is connected to the drain of the second lower switch T5 and to the second phase terminal of the motor's three-phase terminals. The source of the third upper switch T3 is connected to the drain of the third lower switch T6 and to the third phase terminal of the motor's three-phase terminals. The drains of the first upper switch T1, the second upper switch T2, and the third upper switch T3 are connected to the P terminal, and the sources of the first lower switch T4, the second lower switch T5, and the third lower switch T6 are connected to the N terminal. The P terminal is generally connected to the power supply, and the N terminal is generally grounded.

[0099] In one embodiment, the three-phase terminals of the motor are U-phase terminal, W-phase terminal, and V-phase terminal.

[0100] The gate of the first upper switch T1 is used to receive the first upper switch control signal PWM_U_TOP, and the gate of the first lower switch T4 is used to receive the first lower switch control signal PWM_U_BOT. The gate of the second upper switch T2 is used to receive the second upper switch control signal PWM_W_TOP, and the gate of the second lower switch T5 is used to receive the second lower switch control signal PWM_W_BOT. The gate of the third upper switch T3 is used to receive the third upper switch control signal PWM_V_TOP, and the gate of the third lower switch T6 is used to receive the third lower switch control signal PWM_V_BOT.

[0101] When all control signals are high, the first upper switch T1, the first lower switch T4, the second upper switch T2, the second lower switch T5, the third upper switch T3, and the third lower switch T6 are turned on. When all control signals are low, the first upper switch T1, the first lower switch T4, the second upper switch T2, the second lower switch T5, the third upper switch T3, and the third lower switch T6 are turned off.

[0102] Example 5

[0103] This embodiment also discloses a motor system, including a motor and the driver from Embodiment 4. The driver is connected to the motor.

[0104] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0106] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0108] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0109] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A PWM signal generation method for a driver, characterized in that, include: The comparison signal is sampled based on the sampling period, and the comparison signal is used to characterize the relationship between the actual current and the commanded current of the motor. The relationship between the actual current and the commanded current of the motor is determined based on the comparison signal. Based on the judgment result, select the upper switch transistor or the lower switch transistor of the driver, and determine whether the current turn-on time of the selected switch transistor has reached the minimum turn-on time. If yes, generate the upper switch control signal and / or the lower switch control signal based on the judgment result. If no, resample the comparison signal based on the sampling period. The sampling comparison signal based on the sampling period includes: determining whether a new sampling period has begun since the last sampling comparison signal; if so, sampling comparison signal; if not, continuing to wait until a new sampling period begins. Selecting the upper or lower switch of the driver based on the judgment result includes: if the actual current of the motor is less than the commanded current, then the lower switch of the driver is selected; if the actual current of the motor is greater than the commanded current, then the upper switch of the driver is selected. Generating the upper control signal and / or lower control signal based on the judgment result includes: if the actual current of the motor is less than the commanded current, generating a low-level lower control signal, and generating a high-level upper control signal or resampling the comparison signal based on the state of the lower control signal; if the actual current of the motor is greater than the commanded current, generating a low-level upper control signal, and generating a high-level lower control signal or resampling the comparison signal based on the state of the upper control signal.

2. The PWM signal generation method according to claim 1, characterized in that, When the actual current of the motor is less than the commanded current, based on the state of the lower transistor control signal, the selection to generate the high-level lower transistor control signal or to resample the comparison signal based on the sampling period includes: If the lower control signal is low at the end of the previous sampling period, then the upper control signal is high. If not, determine whether the current time has exceeded the preset time since the generation of the low-level lower control signal. If yes, generate the high-level upper control signal. If no, resample the comparison signal based on the sampling period.

3. The PWM signal generation method according to claim 1, characterized in that, When the actual current of the motor is less than the commanded current, based on the state of the upper transistor control signal, the selection to generate the high-level upper transistor control signal or to resample the comparison signal based on the sampling period includes: If the upper transistor control signal is low at the end of the previous sampling period, then a high-level lower transistor control signal is generated. If not, determine whether the current time has exceeded the preset time since the generation of the low-level upper control signal. If yes, generate the high-level lower control signal. If no, resample the comparison signal based on the sampling period.

4. The PWM signal generation method according to claim 1, characterized in that, The PWM signal generation method further includes: performing filtering preprocessing on the comparison signal.

5. A PWM signal generating device, characterized in that, The PWM signal generation module includes at least one processor; and A memory that stores instructions that, when executed by the at least one processor, cause the at least one processor to perform the PWM signal generation method as described in any one of claims 1 to 4.

6. A driver, characterized in that, The device includes a comparison module, a PWM signal generation module, and a switching module. The comparison module is connected to the motor and the controller to compare the magnitude of the actual current and the commanded current to generate a comparison signal. The PWM signal generation module is connected to the comparison module to receive the comparison signal and generate an upper transistor control signal and a lower transistor control signal based on the PWM signal generation method according to any one of claims 1 to 4. The switching module includes an upper switch and a lower switch, which are connected to the motor. The upper switch is connected to the PWM signal generation module to control the switching on and off based on the upper transistor control signal, and the lower switch is connected to the PWM signal generation module to control the switching on and off based on the lower transistor control signal.

7. A motor system, characterized in that, It includes a motor and a driver as described in claim 6, wherein the driver is connected to the motor.

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