Preparation method of printed circuit board

Abstract

The invention discloses a preparation method of a printed circuit board, and relates to the technical field of electronic equipment, the printed circuit board comprises a plurality of sub-layers which are stacked, each sub-layer comprises a core area, and the core area is used for being connected with a ball grid array, that is, the core area is an area provided with a ball grid array (BGA). The preparation method comprises the following steps: before a process of laminating multiple sub-layers, performing expansion and shrinkage compensation on the core area of each sub-layer by taking the central point of the core area as an expansion and shrinkage central point, so that the problem that the core area of each sub-layer is subjected to expansion and shrinkage compensation on the whole sub-layer by taking the central point of the sub-layer as the expansion and shrinkage central point in the prior art is solved; in order to solve the problem that the BGA area has serious alignment deviation due to the fact that the expansion and contraction degree of the local BGA area in a sub-layer cannot be accurately controlled in the prior art, local refined expansion and contraction compensation is performed on the BGA area of the sub-layer, so that the alignment precision of the structure of the BGA area, such as a signal line, is improved, and the reliability of signal transmission of the BGA area is optimized.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a method for preparing a printed circuit board. Background Art

[0002] Printed circuit boards (PCBs), the core structure of electronic devices, are increasingly demanding high-density interconnects and ultra-high-speed signal transmission. Ball grid arrays (BGAs) are widely used in the connection between PCBs and chips due to their high I / O density and short path lengths.

[0003] With the rapid development of fifth-generation communications (5G), artificial intelligence (AI), and high-performance computing (HPC) technologies, electronic devices are placing increasingly stringent requirements on impedance consistency and signal integrity in signal transmission. However, in related technologies, significant misalignment exists between signal lines, vias, or other structures in the area of ​​a PCB used for connecting BGAs. This can easily lead to impedance fluctuations, signal reflections, or electromagnetic interference in signal lines, especially high-speed signal lines, affecting the reliability of signal transmission, particularly high-speed and ultra-high-speed signals. Summary of the Invention

[0004] The present application provides a method for preparing a printed circuit board, which aims to improve the alignment accuracy of the structure in the area of ​​the printed circuit board used to connect BGA, thereby reducing the probability of problems such as impedance mutation, signal reflection or electromagnetic interference occurring in the printed circuit board, and improving the reliability of signal transmission on the printed circuit board and even electronic equipment.

[0005] The present application provides a method for preparing a printed circuit board. The printed circuit board includes multiple sub-layers stacked together, each sub-layer includes a core area, and the core area is used to connect to a ball grid array.

[0006] The preparation method includes: using the center point of the core area as the expansion and contraction center point to compensate for the expansion and contraction of the core area of ​​each sub-layer, and stacking and pressing the multiple sub-layers into one to obtain a printed circuit board.

[0007] In the preparation method provided in the embodiment of the present application, before the process of pressing the multiple sub-layers, the core area of ​​each sub-layer is first compensated for expansion and contraction with the center point of the core area (the area of ​​the PCB used to connect the BGA) as the expansion and contraction center point, thereby avoiding the problem that the expansion and contraction of the local core area in the sub-layer cannot be accurately controlled when the center point of the sub-layer is used as the expansion and contraction center point for the entire sub-layer in the related art, thereby causing alignment deviation of the structure in the core area. That is, the preparation method provided in the embodiment of the present application improves the alignment accuracy of the structure in the core area, such as signal lines, through-holes or other structures, by performing local and refined expansion and contraction compensation on the core area of ​​the sub-layer (the area of ​​the PCB used to connect the BGA), thereby reducing the probability of impedance mutation, signal reflection or electromagnetic interference in the structure in the core area, and optimizing the reliability of signal transmission in the core area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 A top view of a printed circuit board provided in an embodiment of the present application; Figure 2 A cross-sectional view of a printed circuit board provided in an embodiment of the present application; Figure 3 A partial enlarged view of the core area of ​​the printed circuit board provided in an embodiment of the present application; Figure 4 A preparation flow chart of a printed circuit board provided in an embodiment of the present application; Figure 5 A top view of a printed circuit board in the related art; Figure 6 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 7 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 8 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 9 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 10 Another preparation flow chart of a printed circuit board provided in an embodiment of the present application; Figure 11 Other preparation flow charts of printed circuit boards provided in embodiments of the present application; Figure 12 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 13 for Figure 12 An enlarged view of the structure corresponding to the B region; Figure 14 A cross-sectional view of a sublayer provided in an embodiment of the present application; Figure 15 Other preparation flow charts of printed circuit boards provided in embodiments of the present application; Figure 16 for Figure 12 Another structural enlargement corresponding to region B in FIG; Figure 17 A schematic diagram of a computer processing preparation method provided in an embodiment of the present application; Figure 18 Another top view of the printed circuit board provided in an embodiment of the present application; Figure 19 Other preparation flow charts of printed circuit boards provided in embodiments of the present application; Figure 20 Another top view of the printed circuit board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0010] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0011] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0012] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0013] An embodiment of the present application provides a method for preparing a printed circuit board.

[0014] Figure 1A top view of a printed circuit board provided in an embodiment of the present application, Figure 2 For the Figure 1 Cross-sectional view along section line AA'.

[0015] The printed circuit board 100 (eg, PCB) can be used as a mounting substrate for electronic devices to achieve electrical connections between chips, electrical devices, and conductive structures, while also serving as a mechanical support.

[0016] See Figure 2 The printed circuit board 100 (eg, PCB) includes a plurality of sub-layers 10 stacked together.

[0017] It is understandable that Figure 1 The top view of the printed wiring board 100 may be represented, and the top view of a sub-layer 10 in the printed wiring board 100 may also be represented.

[0018] Among them, the sublayer 10 may include a wiring layer in the printed circuit board 100 for line wiring design, and multiple sublayers 10 are stacked so as to utilize the wiring layer in the sublayer 10 to achieve complex electrical connection requirements, thereby realizing functions such as high-speed signal transmission or complex power supply.

[0019] Exemplarily, the printed circuit board 100 may also include an outer layer structure covering the upper and lower surfaces of the multi-layer sub-layer 10. The outer layer structure may include a solder resist layer, or may also include a routing layer for realizing surface routing. That is, the multi-layer sub-layer 10 can be understood as the inner layer structure of the printed circuit board 100. After the inner layer structure is prepared, the outer layer structure is covered. The embodiments of the present application mainly explain the preparation method of the inner layer structure.

[0020] See Figure 2 Each sub-layer 10 includes a core area 1, which is used to connect to a ball grid array (BGA). That is, the core area 1 is the actual part of the printed circuit board 100 (or the sub-layer 10) used to connect to the BGA.

[0021] For example, see Figure 2 After the multiple sub-layers 10 are stacked together to form the printed circuit board 100, the core areas 1 of the multiple sub-layers 10 are overlapped so that the printed circuit board 100 can be connected to the BGA at the location of the core areas 1.

[0022] For example, see Figure 1 The core area 1 can be used to open a plurality of through holes with a high density distribution, so as to form a plurality of pads corresponding to the solder balls of the BGA in the core area 1 by utilizing the plurality of through holes.

[0023] For example, see Figure 1The plane shape of the core area 1 can be a rectangle, and the size and position of the rectangle are such that the rectangle can surround the multiple through holes.

[0024] For example, a printed circuit board 100 (or a sub-layer 10) may include multiple core areas 1. Figure 1 The structure of the printed circuit board 100 is explained by taking only one core area 1 as an example, and the number of core areas 1 is not limited.

[0025] Figure 3 A partially enlarged view of the core area 1 in the printed circuit board 100 provided in an embodiment of the present application.

[0026] For example, see Figure 3 In the multi-layer sub-layer 10, some sub-layers 10 may include a wiring layer L3 for designing the wiring of signal lines, and some sub-layers 10 may include a reference layer L4 (i.e., a ground layer or a power layer, which is a metal layer on the entire surface, such as a copper layer on the entire surface). Figure 3 The copper layer stacked adjacent to the wiring layer L3 can serve as the reference layer L4 of the signal line in the wiring layer L3, providing a return path for the signal line, shielding the interference of external noise signals, and controlling the characteristic impedance of the transmission line formed between the reference layer L4 and the signal line.

[0027] For example, see Figure 3 A plurality of through holes may be provided in the core area 1 of the sublayer 10, and conductive material may be provided in the through holes. The conductive material is used to electrically connect to the signal line, and an insulating material may be provided between the conductive material and the inner wall of the through hole to avoid unexpected electrical connection between the conductive material and the signal line connected thereto.

[0028] When designing the wiring of the sub-layer 10, the alignment accuracy of the signal line setting position in the sub-layer 10 and the alignment accuracy of the through-hole drilling position have a great influence on the electrical performance of the printed circuit board 100. For example, the drilling position (i.e. Figure 3 The location of the through hole (the location of the through hole) must at least avoid the routing location of the signal line to avoid disconnecting the signal line during drilling and causing the signal line function to fail. Or, for example, the routing location of the signal line needs to be located within the range of the reference layer L4 to avoid the impedance mutation problem of the signal transmitted by the signal line (especially the high-speed signal).

[0029] For example, see Figure 3The spacing Li between the signal line and the boundary of the reference layer (for example, the boundary of the reference layer close to the insulating material in the through-hole) can be designed to be greater than or equal to 2 mils to ensure that the reference layer L4 can cover the signal line. If the alignment of the wiring layer L3 and the reference layer L4 deviates, it is easy to cause part of the stacked material of the signal line to become insulating material, that is, the reference layer L4 will be discontinuous, resulting in a sudden impedance change, affecting the reliability of the signal transmitted by the printed circuit board 100.

[0030] To solve the aforementioned technical problems, an embodiment of the present application provides the following method for preparing a printed circuit board 100 .

[0031] Figure 4 A preparation flow chart of a printed circuit board 100 provided in an embodiment of the present application is shown below. Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 They are other top views of the printed circuit board 100 provided in the embodiments of the present application.

[0032] See Figure 4 , the preparation method may include step S1 and step S2: S1: See Figure 6 、 Figure 7 、 Figure 8 and Figure 9 , the expansion and contraction compensation is performed on the core area 1 of each sub-layer 10 with the center point 1a of the core area 1 as the expansion and contraction center point.

[0033] For example, the center point 1 a of the core area 1 may be the intersection of its diagonals.

[0034] For example, when the core area 1 is compensated for expansion and contraction, it can be shrunk or pulled outward from the expansion and contraction center point, so that the expansion and contraction degrees at different positions of the core area 1 are roughly the same.

[0035] S2: stacking and pressing the multiple sub-layers 10 into one piece (see Figure 2 ), and obtain a printed circuit board 100.

[0036] When the multi-layer sub-layer 10 is subjected to the lamination process, the sub-layer 10 will undergo a certain degree of expansion and contraction (deformation such as expansion or contraction of shape and size). This phenomenon can easily cause the wiring position of the signal line in the sub-layer 10 to move, which is not conducive to achieving the alignment of the positions of structures (such as signal lines or through-hole structures) between different sub-layers 10.

[0037] By pre-compensating the sub-layer 10 for expansion and contraction before lamination, the expansion and contraction deviation of the sub-layer 10 during subsequent wiring or lamination processes can be reduced or even offset, thereby helping to reduce alignment errors caused by expansion and contraction.

[0038] Figure 5 A top view of a printed circuit board 100 provided in the related art.

[0039] See Figure 5 In the related art, the intersection of the diagonals of the entire sub-layer 10 (i.e., the center point) is usually used as the expansion and contraction compensation center to compensate for the expansion and contraction of the entire sub-layer 10. However, due to the difference in physical properties (such as copper density, insulation layer thickness, etc.) between the core area 1 and other areas (conventional area 2), the related art cannot accurately control the local expansion and contraction of the core area 1, resulting in poor alignment accuracy of structures in the core area 1, such as high-speed signal lines, affecting the reliability of signals transmitted by the printed circuit board 100. For example, the impedance stability of the signal lines in the core area 1 with poor alignment accuracy is difficult to ensure, resulting in poor stability and reliability of signal transmission.

[0040] In the preparation method provided in the embodiment of the present application, the center point of the core area 1 is used as the expansion and contraction compensation center to perform local and refined expansion and contraction compensation on the core area 1, thereby improving the accuracy of expansion and contraction control of the core area 1 and ensuring the alignment accuracy of the structure in the core area 1, thereby reducing the impedance deviation of the signal line in the core area 1, reducing signal reflection and crosstalk problems, and improving the stability and reliability of signal transmission.

[0041] In some embodiments, see Figure 6 , the aforementioned step S1 may include: The expansion and contraction compensation of the sub-layer 10 is performed with the center point 1a of the core area 1 as the expansion and contraction center point.

[0042] That is, the sub-layer 10 is still compensated for its expansion and contraction as a whole, so that the expansion and contraction center point can be guaranteed to be located at the center point of the core area 1 while the expansion and contraction compensation difficulty is low and the efficiency is high, thereby ensuring the expansion and contraction compensation accuracy of the key component in the sub-layer 10 - the core area 1, thereby giving priority to ensuring the alignment accuracy of the structure of the core area 1.

[0043] In some embodiments, see Figure 7 and Figure 8 The sublayer 10 further includes a conventional area 2, which is arranged around the core area 1. That is, the conventional area 2 is the portion of the sublayer 2 other than the core area 1, that is, the conventional area is not used for connection with the ball grid array.

[0044] The aforementioned step S1 may further include: The expansion and contraction compensation of the conventional area 2 is performed with the center point 2a of the sub-layer 10 as the expansion and contraction center point.

[0045] That is, in this embodiment, the expansion and contraction compensation can be performed on the core area 1 and the conventional area 2 respectively, so that the core area 1 can be compensated for in a refined and local manner without affecting the expansion and contraction of the conventional area 2 in the sub-layer 10, thereby ensuring the alignment accuracy of the structure of the core area 1.

[0046] For example, a first expansion / shrinkage coefficient may be used to compensate for the expansion / shrinkage of the core area 1 , and a second expansion / shrinkage coefficient may be used to compensate for the expansion / shrinkage of the conventional area 2 , wherein the first expansion / shrinkage coefficient and the second expansion / shrinkage coefficient are different.

[0047] That is, different expansion and contraction coefficients can be designed according to the different physical structural characteristics of the core area 1 and the conventional area 2, so that the expansion and contraction compensation of the core area 1 and the conventional area 2 are decoupled, avoiding the problem of loss of expansion and contraction accuracy caused by the need to take into account the expansion and contraction compensation of the two. That is, the expansion and contraction compensation of the core area 1 and the conventional area 2 can be carried out in a targeted manner, thereby improving the alignment accuracy of the overall structure of the sub-layer 10.

[0048] For example, see Figure 8 In the case where the sub-layer 10 includes multiple core areas 1, multiple expansion and contraction compensations can be performed, that is, each core area 1 corresponds to an expansion and contraction center point and performs local refined expansion and contraction compensation.

[0049] In some embodiments, see Figure 9 The sublayer 10 further includes a transition region 3 , which is arranged around the core region 1 and is located between the core region 1 and the conventional region 2 .

[0050] The aforementioned step S1 may further include: The third expansion / contraction coefficient is used to compensate for the expansion / contraction of the transition zone 3 .

[0051] The third expansion coefficient is between the first expansion coefficient and the second expansion coefficient.

[0052] That is, the transition zone 3 is used to transition the expansion and contraction compensation of the core zone 1 and the conventional zone 2, so as to avoid the problem that the compensation coefficient of the core zone 1 and the conventional zone 2 is large due to the large difference in physical structure, and the expansion and contraction compensation still has mutual influence, thereby further improving the degree of precise control of the expansion and contraction compensation of the core zone 1, thereby improving the alignment accuracy of the structure therein.

[0053] Exemplarily, the transition zone 3 can be further divided into a plurality of sub-zones surrounding each other in sequence, and a gradient-changing expansion and contraction coefficient is used to compensate for the expansion and contraction of the plurality of sub-zones, thereby further reducing the impact of the expansion and contraction compensation of the conventional zone 2 on the expansion and contraction degree of the core zone 1, thereby further improving the alignment accuracy of the structure in the core zone 1.

[0054] For example, the expansion and contraction compensation of the transition zone 3 can be performed with the center point 1 a of the core zone 1 as the expansion and contraction center point.

[0055] The above embodiments improve the control over the expansion and contraction of the core area 1 by performing local expansion and contraction compensation on the core area 1, thereby optimizing the alignment accuracy of the structure in the core area 1. The following embodiments further improve the alignment accuracy of the core area 1 in subsequent batches of printed circuit boards 100 by dynamically feeding back the expansion and contraction of the previous batch of printed circuit boards 100.

[0056] Figure 10 Another preparation flow chart of the printed circuit board 100 provided in an embodiment of the present application.

[0057] In some embodiments, see Figure 10 The method for preparing the printed circuit board 100 further includes: S3: measuring the expansion and contraction differences between the core areas 1 of the multi-layer sub-layers 10 in the printed circuit board 100 (ie, after step S2).

[0058] The aforementioned step S1 includes: S11: Based on the expansion and contraction differences, the expansion and contraction coefficient of the core area 1 of each sub-layer 10 is determined.

[0059] S12: Using the expansion and contraction coefficient, the expansion and contraction compensation is performed on the core area 1.

[0060] Adopting step S12 can reduce the difference in expansion and contraction between different sub-layers 10 after the printed circuit board 100 is pressed together.

[0061] For example, if the expansion and contraction difference between two adjacent sub-layers 10 is large, the expansion and contraction coefficient of the sub-layer 10 that is prone to expansion and contraction is set to a smaller value when compensating for the expansion and contraction, and the expansion and contraction coefficient of the sub-layer 10 that is prone to expansion and contraction is set to a larger value when compensating for the expansion and contraction. In this way, different expansion and contraction compensation degrees are used to reduce the deformation difference that occurs after the subsequent pressing and expansion of the two, thereby reducing the alignment error between the two.

[0062] That is, the expansion and contraction differences between different sub-layers 10 of the printed circuit board 100 after lamination due to lamination and other processes are fed back to the preparation steps of subsequent batches of printed circuit boards 100, so that the expansion and contraction coefficients of subsequent batches of printed circuit boards 100 can be dynamically adjusted during the preparation process when performing expansion and contraction compensation, thereby further improving the control accuracy of the expansion and contraction compensation of the core area 1, thereby further improving the alignment accuracy of the structure in the core area 1.

[0063] For example, a detection device (such as an optical detection device, such as a high-precision CCD) can be used to scan the core area 1 after S2 in real time to obtain the actual deformation and expansion and contraction data of the core area 1 in each sub-layer 10, thereby obtaining the expansion and contraction differences between different sub-layers 10.

[0064] Exemplarily, the preparation step may further include: The data in the preparation process is transmitted to the processor, and the expansion and contraction coefficients of different sub-layers 10 are obtained by analysis and calculation using the processor, thereby further improving the accuracy of the expansion and contraction control of the core area 1.

[0065] For example, the actual deformation and expansion / contraction data of the core area 1 in each sub-layer 10 detected by the detection equipment can be uploaded to a processor (such as a computer system). The processor calculates the expansion / contraction differences between different sub-layers 10, and based on the expansion / contraction differences, obtains the expansion / contraction coefficient that needs to be adjusted for expansion / contraction compensation for each sub-layer 10.

[0066] Exemplarily, the processor may be equipped with an AI algorithm to perform intelligent calculation and data optimization on the data involved in the embodiments of the present application, thereby improving preparation accuracy.

[0067] For example, an automated expansion and shrinkage optimization program can be written and installed on the processor. Actual expansion and shrinkage data, expansion and shrinkage differences, and processor-predicted expansion and shrinkage data can be imported into the program for automatic comparison and optimization. This ensures more accurate expansion and shrinkage data for subsequent batches of production, thereby guaranteeing the alignment of the core area 1 of the printed circuit board 100 after lamination. Processing data from previous batches can also be recorded to form a database, facilitating data retrieval or reference for subsequent annotations of similar production processes.

[0068] Figure 11 Other preparation flow charts of the printed circuit board 100 provided in the embodiments of the present application are as follows: Figure 12 Another top view of the printed circuit board 100 provided in an embodiment of the present application, Figure 13 for Figure 12 The enlarged view of the structure corresponding to area B in FIG.

[0069] In some embodiments, see Figure 11 , the aforementioned step S3 may include steps S31 to S33: S31: See Figure 13 Before performing expansion and contraction compensation (before step S1 ), four first targets M1 are set in the core area 1 of the sub-layer 10 .

[0070] The target may be a Mark so that the target can be identified and detected by the detection device, and the same applies to the subsequent second target, third target, and so on.

[0071] Exemplarily, the diameter of the first target M1 may be 0.5 mm to 1 mm.

[0072] See Figure 12 and Figure 13 The four first targets M1 are respectively set close to the four corners of the core area 1.

[0073] It should be noted that the "four corners of the core area 1" means that the overall planar shape of the core area 1 can be a rectangle, and the four corners of the rectangle are the four corners of the core area 1. In addition, when the multiple through holes in the core area 1 are arranged in a circular ring shape, the part of the rectangle that can at least completely cover the multiple through holes is divided into the core area 1. At this time, the four corners of the core area 1 are still the four corners of the rectangle.

[0074] Here, “being arranged close to the four corners of the core area 1 ” means that the first target M1 arranged at the location of a certain corner is closer to the corner.

[0075] For example, the first target M1 may be set outside (outside a corner) of the rectangular area where the core area 1 is located, and the distance between the first target M1 and the nearest corner is small, for example, the distance may be less than or equal to 2 mm.

[0076] Or for example, the first target M1 may be set inside (inside a corner) of the rectangular area where the core area 1 is located, and the distance between the first target M1 and the nearest corner is small, for example, the distance may be less than or equal to 2 mm.

[0077] In summary, the first target M1 provided in the embodiment of the present application only needs to be set at the four directions of the core area 1 and close to the core area 1, without being restricted to the specific structural setting or shape setting in the core area 1.

[0078] S32: Measure the spacing between the four first targets M1 in each sub-layer 10 of the printed wiring board 100 to obtain a first spacing parameter.

[0079] Exemplarily, the first spacing parameter may include Figure 12 There are four spacing values, namely, the spacing between the two first targets M1 on the leftmost side, the spacing between the two first targets M1 on the rightmost side, the spacing between the two first targets M1 on the top side, and the spacing between the two first targets M1 on the bottom side. These four spacing values ​​can ensure the expansion and contraction states at different positions of the core area 1 in the sub-layer 10 of this layer.

[0080] Figure 13 In the figure, the first target M1 shown by the solid line is the first target M1 of the sub-layer 10 , and the first target M1 shown by the dotted line is the first target M1 in other sub-layers stacked with the sub-layer 10 .

[0081] See Figure 13In the printed circuit board 100, the first targets M1 in the multi-layer sub-layers 10 are staggered in the stacking direction of the multi-layer sub-layers 10, so that after the multi-layer sub-layers 10 are stacked and pressed, the first target M1 in each sub-layer 10 can still be detected individually, thereby detecting the expansion and contraction of the multi-layer sub-layers 10 after pressing.

[0082] For example, see Figure 13 , multiple first targets M1 located at the same position can be arranged along the circumference to achieve staggering.

[0083] Exemplarily, the order in which the plurality of first targets M1 are arranged along the circumference may be set according to the arrangement order of the sub-layers.

[0084] For example, a plurality of first targets M1 located at the same position may be arranged within a range of 0.6 mm, so that the first targets M1 can be removed when positioning holes are subsequently formed, thereby preventing the first targets M1 from remaining and interfering with the identification and measurement of other targets.

[0085] S33 : Based on the first spacing parameter of each sub-layer 10 , obtain the difference between the first spacing parameters in the multiple sub-layers 10 .

[0086] The difference between the first spacing parameters represents the difference in expansion and contraction between the core regions 1 of the multi-layer sub-layers 10 .

[0087] For example, in two adjacent sub-layers 10 , the difference between the distance between the two leftmost first targets M1 of one sub-layer 10 and the distance between the two leftmost first targets M1 of the other sub-layer 10 can indicate the difference in expansion and contraction between the two sub-layers 10 .

[0088] Exemplarily, step S32 and step S33 may be analyzed and calculated using a processor.

[0089] In this embodiment, a plurality of first targets M1 staggered with each other are used to measure the expansion and contraction of the core area 1 in each sub-layer 10, thereby obtaining the expansion and contraction differences between the core areas 1 in different sub-layers 10. This is to parameterize the expansion and contraction differences, thereby improving the accuracy of the expansion and contraction difference measurement, so as to further improve the accuracy of the expansion and contraction coefficient when calculating the expansion and contraction compensation based on the expansion and contraction differences, and facilitate further improving the alignment accuracy of the structure in the core area 1.

[0090] Figure 14 A cross-sectional view of the sub-layer 10 provided in an embodiment of the present application.

[0091] In some embodiments, see Figure 14 The sub-layer 10 may include a first wiring layer 11 , a second wiring layer 12 , and an insulating layer 13 interposed between the first wiring layer 11 and the second wiring layer 12 .

[0092] Exemplarily, the aforementioned step S31 may include: A first target M1 is provided on the first wiring layer 11 or the second wiring layer 12 of each sub-layer 10 .

[0093] That is, when the design space is insufficient, four first targets M1 may be set on only one wiring layer of the sub-layer 10 , taking into account both the design space and the control of the expansion and contraction of each sub-layer 10 .

[0094] Alternatively, for example, the aforementioned step S31 may include: A first target M1 is set on the first wiring layer 11 and the second wiring layer 12 of each sub-layer 10, thereby further refining the expansion and contraction control of each wiring layer in the sub-layer 10 and further improving the alignment accuracy of the core area 1 of the printed circuit board 100.

[0095] Exemplarily, the preparation method further includes: performing wiring design (ie, patterning, for example, designing and shaping a wiring pattern using an LDI exposure method) on the wiring layer (including the first wiring layer 11 and the second wiring layer 12 ) of the sub-layer 10 .

[0096] For example, when wiring, the first wiring layer 11 can be designed for wiring first, and at the same time, a positioning target can be formed at the position of the corresponding core area 1 of the second wiring layer 12. Then, the positioning target is used as a positioning reference to design the wiring of the second wiring layer 12, so that the core areas 1 of the upper and lower wiring layers in the same sub-layer 10 have better alignment accuracy, further improving the overall alignment accuracy of the core area 1 of the printed circuit board 100.

[0097] Exemplarily, the positioning target may reuse the aforementioned first target M1, or may reuse the second target M2 in subsequent embodiments.

[0098] The aforementioned embodiment improves the alignment accuracy of the structures in the core areas 1 of different sub-layers 10 by locally and finely controlling the expansion and contraction degree of the core area 1 in each sub-layer 10, thereby optimizing the electrical performance of the printed circuit board 100 (such as the reliability of the transmitted signal). In addition, the accuracy of the drilling position on the printed circuit board 100 also affects the reliability of the signal transmitted thereon. The following embodiment will explain the drilling process of the printed circuit board 100.

[0099] Figure 15 Other preparation flow charts of the printed circuit board 100 provided in the embodiments of the present application are as follows: Figure 16 After pressing Figure 12 Another enlarged view of the structure corresponding to area B in FIG.

[0100] In some embodiments, see Figure 15The method for preparing the printed circuit board 100 further includes the following steps S4 to S6: S4 : before performing expansion and contraction compensation (ie, before step S1 ), at least two second targets M2 are set on each sub-layer 10 .

[0101] For example, see Figure 12 and Figure 13 , this step S4 can be performed simultaneously with the aforementioned step S31.

[0102] Among them, see Figure 12 and Figure 13 The at least two second targets M2 are respectively arranged near the four corners of the core area 1, and two of the second targets M2 are respectively arranged near the two corners of the core area 1 arranged along the diagonal line.

[0103] The design method of the second target M2 provided in the embodiment of the present application can refer to the description of the first target M1 in the aforementioned embodiment, and will not be repeated here. That is, as long as the second target M2 can be set at the four directions of the core area 1 and is close to the core area 1, it will be sufficient.

[0104] Exemplarily, two second targets M2 can be set on each sub-layer 10. At this time, the two second targets M2 are set on the diagonal of the core area 1 (that is, they are set at two corners arranged along the diagonal close to the core area 1 respectively), so that the core area 1 can still be positioned with the minimum number of second targets M2, which facilitates subsequent drilling based on the positioning.

[0105] Or illustratively, four second targets M2 may be provided on each sub-layer 10 , and the four second targets M2 may be used to further improve the positioning accuracy of the core area 1 , thereby improving the subsequent drilling accuracy when drilling according to the positioning.

[0106] See Figure 13 , the second targets M2 in different sub-layers 10 are arranged at the same position in the sub-layer 10 where they are located ( Figure 13 In the figure, the second targets M2 of multiple sub-layers 10 are completely overlapped as an example for illustration).

[0107] That is, before the multiple sub-layers 10 are pressed together and the sub-layers 10 do not undergo expansion and contraction deformation, the second targets M2 in different sub-layers 10 are set at the same position. For example, when the multiple sub-layers 10 are stacked (not pressed, just simply stacked), the multiple second targets M2 in the multiple sub-layers 10 located at the same orientation of the core area 1 can overlap, that is, the second targets M2 in different sub-layers 10 can represent the same position information of the core area 1, so that whether the second targets M2 in different sub-layers 10 overlap can be used to represent whether the core areas 1 in different sub-layers 10 overlap, that is, to represent the alignment of the sub-layers 10 after stacking and pressing.

[0108] Figure 17 This is a schematic diagram of executing step S5 using a computer according to an embodiment of the present application.

[0109] S5: See Figure 16 and Figure 17 , the multiple second targets M2 that overlap with each other in the multi-layer sub-layer 10 in the printed circuit board 100 (ie after step S2 ) are fitted into a target circle N1 .

[0110] The target circle N1 is a circle that minimizes the sum of the squares of the distances from the plurality of second targets M2 to the center of the circle.

[0111] That is, the target circle N1 is an optimal circle after the positions of the multiple second targets M2 are fitted, and its position can represent the optimal overlapping position of the multiple second targets M2.

[0112] Figure 18 Another top view of the printed circuit board 100 provided in an embodiment of the present application.

[0113] S6: See Figure 18 Based on the position of the target circle N1, the printed circuit board 100 is drilled to obtain a positioning hole H1.

[0114] Exemplarily, it can be understood that the number of the positioning holes H1 is the same as the number of the second targets M2 in one sub-layer 10 , that is, there are at least two positioning holes H1 , and the two positioning holes H1 are arranged along the diagonal line of the core area 1 .

[0115] The positioning hole H1 is used to locate the position of the core area 1 of the printed circuit board 100. For example, the positioning hole H1 can be used as a physical fixing hole to achieve physical fixation of the processing equipment (such as a drilling rig), thereby ensuring the alignment accuracy of the multiple through holes drilled by the drilling rig in the core area 1 for connection with the ball grid array in the core area 1, and avoiding offset or misalignment of the through holes.

[0116] After step S2, the multiple sub-layers 10 expand and shrink to varying degrees, and the multiple second targets M2 that should ideally completely overlap overlap due to the influence of expansion and contraction (i.e., there is partial overlap, but not complete overlap). At this time, the positioning hole H1 is drilled using the position of the fitted target circle N1, which can reduce the alignment error of the positioning hole H1 in each sub-layer 10, thereby improving the alignment accuracy of multiple through holes subsequently formed in the core area 1 using the positioning hole H1.

[0117] Figure 19 These are some other preparation flow charts of the printed circuit board 100 provided in the embodiments of the present application.

[0118] In some embodiments, see Figure 19 , the aforementioned step S6 may include: S61: Measure the spacing change value of the four first targets M1 of each sub-layer 10 in the printed circuit board 100 (i.e., after step S2) to obtain the expansion and contraction state of the core area 1 of the printed circuit board 100 (i.e., the core area 1 after the multiple sub-layers 10 are pressed together).

[0119] The spacing change value is the difference between the spacing between the four first targets M1 before the expansion and contraction compensation step (step S1 ) and the spacing between the four first targets M1 after the pressing step (step S2 ).

[0120] The spacing change value of a sub-layer 10 can represent the expansion and contraction state of the core area 1 of the sub-layer 10. By fitting the spacing change values ​​of multiple sub-layers 10, the overall expansion and contraction state of the core area 1 of the printed circuit board 100 can be obtained.

[0121] S62: See Figure 16 , based on the expansion and contraction state, the position of the target circle N1 is adjusted to obtain the final positioning point N2.

[0122] See Figure 17 ,The position of the target circle N1 can be adjusted using a computer / processor to obtain the final positioning point N2.

[0123] S63: Based on the position of the final positioning point N2, drilling is performed on the printed circuit board 100 to obtain a positioning hole H1.

[0124] That is, in the embodiment of the present application, the first target M1 can also be used to obtain the expansion and contraction of the core area 1 as a whole (that is, not the core area 1 of one sub-layer 10, but the core areas 1 of all sub-layers 10 as a whole) after the multiple sub-layers 10 are stacked and pressed together, and the position of the aforementioned target circle N1 can be dynamically adjusted in real time according to the expansion and contraction of the core area 1 of the printed circuit board 100, thereby comprehensively considering the influence of the overall expansion and contraction of the core area 1 on the position of the target circle N1, fitting a better drilling path, eliminating the interference of the mark offset of the second target M2 of the single sub-layer 10 on the drilling positioning, and further improving the alignment accuracy of the positioning hole H1.

[0125] For example, a detection device (such as a CCD device) can be used to collect the deformation (i.e., expansion and contraction) of the core area 1, and based on the deformation, the drilling position can be automatically calculated and updated (i.e., the coordinates of the target circle N1 are updated to the coordinates of the final positioning point N2).

[0126] Figure 20 Another top view of the printed circuit board 100 provided in an embodiment of the present application.

[0127] In some embodiments, see Figure 20After step S6, the preparation method may further include: S7 : Based on the positioning of the positioning holes H1 , a plurality of through holes H2 are opened in the core area 1 of the printed wiring board 100 .

[0128] The plurality of through holes H2 are used for connection with a ball grid array (BGA).

[0129] For example, the diameter of the positioning hole H1 may be 0.6 mm, and the diameter of the through hole H2 may be 2 mm.

[0130] For example, see Figure 13 The first target M1 and the second target M2 located at the same orientation (near the same corner) of the core area 1 are spaced apart to avoid mutual interference during measurement.

[0131] For example, the first target M1 and the second target M2 located at the same orientation (near the same corner) of the core area 1 can be within the 0.6 mm area, so that when drilling the positioning hole N1, the first target M1 and the second target M2 can be removed to prevent the first target M1 and the second target M2 from affecting the identification and positioning at other positions of the printed circuit board 100.

[0132] Exemplarily, the position of the positioning hole H1 (i.e., the setting position of the first target M1 and the second target M2) can be the position where an opening (including the through hole H1 or the second through hole H4) needs to be formed on the printed circuit board 100, so that the positioning hole H1 can be covered after the opening is formed, thereby maximizing the utilization of the design space in the printed circuit board 100.

[0133] In some embodiments, the preparation method may further include: S8: See Figure 12 , third targets M3 are set at the four corners of the sub-layer 10.

[0134] S9: See Figure 18 After step S2, a second positioning hole H3 is obtained using the third target M3.

[0135] S10: See Figure 20 Based on the positioning of the second positioning hole H3, a plurality of second through holes H4 are opened in the regular area 2 of the printed circuit board 100. The plurality of second through holes H4 are used to realize some other connections in the regular area 2 of the printed circuit board 100 except for those before the BGA.

[0136] Exemplarily, step S8 may be performed simultaneously with step S4.

[0137] Exemplarily, step S10 and step S7 may be performed separately, and the order of the two is not limited.

[0138] In summary, the embodiment of the present application can improve the alignment accuracy of the core area 1 by performing local expansion and contraction compensation on the core area 1, and can utilize the collaborative innovation of real-time dynamic compensation (adjusting the expansion and contraction coefficient during expansion and contraction compensation according to the expansion and contraction difference) technology and intelligent detection technology to achieve fine control of the expansion and contraction coefficient during local expansion and contraction compensation of the core area 1, thereby further improving the alignment accuracy of the core area 1. In addition, the second target M2 is used to achieve high-precision positioning of the drilling position, and the real-time monitoring of the expansion and contraction situation is used to dynamically adjust and refine the drilling position, further improving the alignment accuracy of the core area 1, breaking through the reliability bottleneck of BGA interconnection in high-frequency scenarios, and reducing the difficulty of mass production yield control in the core area 1 of the printed circuit board 100 due to material thermal expansion coefficient mismatch, lamination alignment error and drilling accuracy fluctuation.

[0139] The above is a detailed introduction to the method for preparing a printed circuit board provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for preparing a printed circuit board, characterized in that: The printed circuit board comprises a plurality of stacked sub-layers, each sub-layer comprising a core area, and the core area is used for connecting to a ball grid array; The preparation method comprises: Taking the center point of the core area as the expansion and contraction center point, the core area of ​​each sub-layer is compensated for expansion and contraction; The multiple sub-layers are stacked and pressed into one body to obtain the printed circuit board.

2. The preparation method according to claim 1, characterized in that The performing expansion and contraction compensation on the core area of ​​each sub-layer by taking the center point of the core area as the expansion and contraction center point comprises: The expansion and contraction compensation of the sublayer is performed with the center point of the core area as the expansion and contraction center point.

3. The preparation method according to claim 1, characterized in that The sublayer further includes a regular area, and the regular area is arranged around the core area; The performing expansion and contraction compensation on the core area of ​​each sub-layer with the center point of the core area as the expansion and contraction center point further comprises: The expansion and contraction compensation is performed on the conventional area with the center point of the sub-layer as the expansion and contraction center point.

4. The preparation method according to claim 3, characterized in that A first expansion / contraction coefficient is used to compensate for the expansion / contraction of the core area, and a second expansion / contraction coefficient is used to compensate for the expansion / contraction of the conventional area; the first expansion / contraction coefficient and the second expansion / contraction coefficient are different.

5. The preparation method according to claim 4, characterized in that The sublayer further includes a transition region, the transition region being arranged around the core region and between the core region and the conventional region; The performing expansion and contraction compensation on the core area of ​​each sub-layer with the center point of the core area as the expansion and contraction center point further comprises: A third expansion / contraction coefficient is used to compensate for the expansion / contraction of the transition zone; the third expansion / contraction coefficient is between the first expansion / contraction coefficient and the second expansion / contraction coefficient.

6. The preparation method according to any one of claims 1 to 5, characterized in that Also includes: Measuring the difference in expansion and contraction between core areas of multiple sub-layers in the printed circuit board; The step of compensating the expansion and contraction of the core area of ​​each sub-layer by taking the center point of the core area as the expansion and contraction center point includes: Determining the expansion and contraction coefficient of the core area of ​​each sub-layer based on the expansion and contraction difference; The expansion and contraction coefficient is used to compensate for the expansion and contraction of the core area, so that the expansion and contraction difference is reduced.

7. The preparation method according to claim 6, characterized in that The measuring of the expansion and contraction differences between the core areas of the multiple sub-layers in the printed circuit board comprises: Before performing expansion and contraction compensation, four first targets are set in the core area of ​​the sublayer; the four first targets are respectively set near the four corners of the core area; Measuring the spacing between the four first targets in each sub-layer of the printed circuit board to obtain a first spacing parameter; in the printed circuit board, the first targets in the multiple sub-layers are staggered in a stacking direction of the multiple sub-layers; Based on the first spacing parameter of each sub-layer, a difference between the first spacing parameters in multiple sub-layers is obtained; the difference between the first spacing parameters represents the expansion and contraction difference between the core areas of the multiple sub-layers.

8. The preparation method according to claim 7, characterized in that The sub-layer includes a first wiring layer, a second wiring layer, and an insulating layer interposed between the first wiring layer and the second wiring layer; Wherein, the setting of four first targets in the core area of ​​the sublayer includes: The first target is disposed on the first wiring layer and / or the second wiring layer of each sub-layer.

9. The preparation method according to any one of claims 1 to 5, characterized in that Also includes: Before performing expansion and contraction compensation, at least two second targets are set on each sub-layer; the at least two second targets are respectively set near the four corners of the core area, and two of the second targets are respectively set near two diagonally arranged corners of the core area; the second targets in different sub-layers are set at the same position in the sub-layer in which they are located; Fitting the multiple second targets overlapping each other in the multiple sub-layers of the printed circuit board into a target circle; the target circle is a circle that minimizes the sum of the squares of the distances from the multiple second targets to the center of the circle; Based on the position of the target circle, positioning holes are drilled into the printed circuit board.

10. The preparation method according to claim 9, characterized in that The core area of ​​each sub-layer is equipped with four first targets; The step of drilling holes in the printed circuit board based on the position of the target circle to obtain positioning holes includes: Measuring a spacing change value of the four first targets in each sub-layer of the printed circuit board to obtain an expansion / contraction state of a core area of ​​the printed circuit board; the spacing change value is a difference between the spacing of the four first targets before the expansion / contraction compensation step and the spacing of the four first targets after the lamination step; Adjusting the position of the target circle based on the expansion and contraction state to obtain a final positioning point; Based on the position of the final positioning point, the printed circuit board is drilled to obtain positioning holes.

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